Back contact solar cell

Abstract

The utility model discloses a back contact solar cell, and relates to the technical field of solar cell manufacturing. Comprising a silicon substrate, first carrier collecting layers and second carrier collecting layers which are alternately arranged on a first main surface of the silicon substrate, first insulating layers which are located on the outer sides of the second carrier collecting layers and are arranged close to the first carrier collecting layers at intervals, and second insulating layers arranged on the outer sides of the first insulating layers, wherein the type of the first current carrier collection layer is opposite to that of the second current carrier collection layer, and no electric connection exists between the first current carrier collection layer and the second current carrier collection layer; an electrode groove is formed between every two adjacent first insulating layers, and each electrode groove corresponds to the first carrier collection layer or the second carrier collection layer; a metal electrode stacked on the outer side of the first carrier collection layer or the second carrier collection layer is further arranged in the electrode groove, and the second insulation layer is located on the outer side of the metal electrode. According to the embodiment, the appearance beautification degree of the solar cell is improved while the metal electrode is protected.

Description

TECHNICAL FIELD

[0001] The utility model relates to solar cell manufacturing technical field especially relates to a back contact solar cell. BACKGROUND

[0002] The existing back contact cell usually carries out the preparation of doped layer and tunneling oxide structure first, and after the preparation of the outermost passivation layer is completed, the metal paste coated by sintering is used to make the metal paste penetrate the passivation layer and realize the electrical connection with the doped layer, so that the solar cell structure with the metal electrode located in the outermost layer and exposed is obtained. SUMMARY

[0003] Therefore, the utility model discloses a back contact solar cell, the first insulating layer containing electrode groove is arranged outside the carrier collection layer, and the second insulating layer is arranged outside the metal electrode and the first insulating layer, the back contact solar cell structure with the metal electrode embedded in the insulating layer is obtained, so that the metal electrode is directly connected with the carrier collection layer, the current is exported, the appearance of the solar cell is improved when the second insulating layer protects the metal electrode, and the embedding structure of the metal electrode saves the double processes of silk screen printing and sintering in the prior art.

[0004] In order to solve the above technical problems, the utility model provides the following technical scheme:

[0005] In a first aspect, the utility model provides a back contact solar cell, which comprises a silicon base, a first carrier collection layer and a second carrier collection layer arranged alternately on a first main surface of the silicon base, a first insulating layer arranged outside the second carrier collection layer and close to the first carrier collection layer, and a second insulating layer arranged outside the first insulating layer, wherein the type of the first carrier collection layer is opposite to the type of the second carrier collection layer, and there is no electrical connection between the first carrier collection layer and the second carrier collection layer; an electrode groove is formed between every two adjacent first insulating layers, wherein each electrode groove corresponds to the first carrier collection layer or the second carrier collection layer; a metal electrode is arranged outside the first carrier collection layer or the second carrier collection layer in the electrode groove, and the second insulating layer is arranged outside the metal electrode to embed the metal electrode inside the second insulating layer.

[0006] Optionally, the first carrier collecting layer comprises a first doped layer and a tunneling oxide structure arranged in a stack; the second carrier collecting layer comprises a second doped layer and a tunneling oxide structure arranged in a stack, and the tunneling oxide structure does not cover an edge region of the second doped layer close to the first doped layer, and the first insulating layer is arranged at the edge region.

[0007] Optionally, the edge region has a width of 10-100 nm.

[0008] Optionally, the tunneling oxide structure comprises a tunneling oxide layer and an intrinsic polysilicon layer arranged in a stack.

[0009] Optionally, the tunneling oxide layer has a thickness of 1-2 nm; and / or, the intrinsic polysilicon layer has a thickness of 110-150 nm.

[0010] Optionally, the first insulating layer comprises at least one of silicon nitride or silicon dioxide; and / or, the second insulating layer comprises at least one of silicon nitride or silicon dioxide.

[0011] Optionally, an electrode lead-out groove corresponding to the metal electrode is further arranged on the second insulating layer.

[0012] Optionally, the metal electrode has a size not greater than that of the electrode groove.

[0013] Optionally, the electrode groove has a depth of 5-10 μm; and / or, the electrode groove has a width of 16-26 μm.

[0014] Optionally, the metal electrode comprises at least one of copper, titanium, nickel, silver, and aluminum.

[0015] The technical scheme of the first aspect of the utility model has the following advantages or beneficial effects: by arranging the first insulating layer containing the electrode groove outside the carrier collecting layer, and arranging the second insulating layer outside the metal electrode and the first insulating layer, a back contact solar cell structure with the metal electrode pre-embedded in the insulating layer is obtained, so that the metal electrode is directly connected with the carrier collecting layer, not only achieving current output, but also improving the appearance beautification degree of the solar cell while protecting the metal electrode by the second insulating layer, and the pre-embedded structure of the metal electrode also saves the double processes of screen printing and sintering in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are used to better understand the utility model, and do not constitute improper limitation on the utility model. Among them:

[0017] Figure 1Is a preparation method of a back contact solar cell according to an embodiment of the utility model discloses a flow chart schematic drawing of preparation method of back contact solar cell;

[0018] Figure 2 Is a preparation first carrier collection layer and second carrier collection layer according to an embodiment of the utility model discloses a flow chart schematic drawing;

[0019] Figure 3 Is the silicon matrix section structure schematic drawing that prepares according to an embodiment of the utility model step S201 obtains;

[0020] Figure 4 Is the silicon matrix section structure schematic drawing that prepares according to an embodiment of the utility model step S202 obtains;

[0021] Figure 5 Is the flow chart schematic drawing of preparation first doped layer and second doped layer in step S201 according to an embodiment of the utility model;

[0022] Figure 6 Is the silicon matrix section structure schematic drawing that prepares according to an embodiment of the utility model step S501 obtains;

[0023] Figure 7 Is the silicon matrix section structure schematic drawing that prepares according to an embodiment of the utility model step S502 obtains;

[0024] Figure 8 Is the silicon matrix section structure schematic drawing that obtains after using protective layer 7 to prepare second doped layer 31 in step S503 according to an embodiment of the utility model;

[0025] Figure 9 Is the flow chart schematic drawing of preparation protective layer in step S502 according to an embodiment of the utility model;

[0026] Figure 10 Is the flow chart schematic drawing of preparation tunneling oxide structure in step S202 according to an embodiment of the utility model;

[0027] Figure 11 Is the silicon matrix section structure schematic drawing that prepares according to an embodiment of the utility model step S1001 obtains;

[0028] Figure 12 Is the silicon matrix section structure schematic drawing that prepares according to an embodiment of the utility model step S1002 obtains;

[0029] Figure 13 Is the silicon matrix section structure schematic drawing that obtains after preparation first insulating layer according to an embodiment of the utility model step S102;

[0030] Figure 14is a silicon substrate section structure schematic diagram obtained after the step S102 of preparing the spaced electrode groove according to the embodiment of the utility model;

[0031] Figure 15 is a section structure schematic diagram of a back contact solar cell according to the embodiment of the utility model.

[0032] The signs are as follows:

[0033] 1-silicon substrate; 11-first region; 12-second region; 121-edge region; 2-first carrier collection layer; 21-first doped layer; 3-second carrier collection layer; 31-second doped layer; 4-electrode groove; 5-metal electrode; 6-tunneling oxide structure; 61-tunneling oxide layer; 62-intrinsic polysilicon layer; 7-protective layer; 71-passivation layer; 72-photolithography layer. DETAILED DESCRIPTION

[0034] Solar cell is a kind of photovoltaic semiconductor wafer using sunlight to generate electricity, also called "solar chip" or "photocell", it can output voltage and produce current in the case of loop as long as being illuminated by light of certain illumination condition.In physics, it is called solar photovoltaic (Photovoltaic, abbreviated as PV), simply called photovoltaic.In order to conveniently and clearly describe the preparation method of solar cell and solar cell of the utility model, the exemplary embodiments of the utility model are described below in conjunction with drawings, including various details of the embodiments of the utility model to help understanding, they should be considered only as exemplary.Therefore, those skilled in the art should realize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the utility model.Similarly, in order to be clear and concise, the description is omitted in the following description.

[0035] In an embodiment of the utility model, as Figure 15The utility model discloses a back contact solar cell structure, which comprises a silicon substrate, a first carrier collection layer and a second carrier collection layer arranged alternately on a first main surface of the silicon substrate, a first insulating layer arranged on an outer side of the second carrier collection layer and close to the first carrier collection layer, and a second insulating layer arranged on an outer side of the first insulating layer.

[0036] The first carrier collection layer and the second carrier collection layer can be a multi-layer structure, and in an optional embodiment, the first carrier collection layer comprises a first doped layer and a tunneling oxide structure arranged in layers, and the second carrier collection layer comprises a second doped layer and a tunneling oxide structure arranged in layers, and the tunneling oxide structure does not cover an edge region of the second doped layer close to the first doped layer, and the first insulating layer is arranged on the edge region.

[0037] Further, the tunneling oxide structure comprises a tunneling oxide layer and an intrinsic polysilicon layer arranged in layers, and the tunneling oxide layer has a thickness of 1-2 nm and separates electrons and holes, and a too thick tunneling oxide layer will hinder the tunneling transmission of most carriers, resulting in a decrease in open circuit voltage (OCV) of the battery and affecting the energy conversion efficiency of the battery.

[0038] In a further optional embodiment, the edge region has a width of 10-100 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 70 nm, 80 nm, 100 nm, etc.

[0039] For the selection of the first insulating layer and the second insulating layer, in an optional embodiment, the first insulating layer comprises at least one of the following materials: silicon nitride or silicon dioxide; and the second insulating layer comprises at least one of the following materials: silicon nitride or silicon dioxide.

[0040] In an optional embodiment, the depth of the electrode groove 4 is 5 μm ~ 10 μm, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.; and for the width of the electrode groove 4, in another optional embodiment, the width of the electrode groove 4 is 16 μm ~ 26 μm, for example, 16 μm, 20 μm, 24 μm, 26 μm, etc.

[0041] It can be understood that the growth of the metal electrode 5 is limited by the width and depth of the electrode groove 4, and therefore in a further optional embodiment, the size of the metal electrode 5 is not greater than the size of the electrode groove 4. In the actual preparation process, the metal ions are not necessarily completely deposited in the electrode groove 4, and therefore the thickness of the metal electrode 5 can be different from the electrode groove 4, and in a further optional embodiment, the metal electrode 5 in the utility model fills the electrode groove 4, that is, the thickness of the metal electrode 5 is 5 μm ~ 10 μm, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc. And its growth width is often limited by the width of the electrode groove 4, and therefore in an optional embodiment, the width of the metal electrode 5 is also 16 μm ~ 26 μm, for example, 16 μm, 20 μm, 24 μm, 26 μm, etc.

[0042] In addition, the metal electrode 5 in the electrode groove 4 can only correspond to the first carrier collection layer 2 or the second carrier collection layer 3, and cannot be arranged in the intersection area of the first carrier collection layer 2 and the second carrier collection layer 3.

[0043] In order to facilitate the communication of the metal electrode 5 with the external power supply or wire, an electrode lead-out groove corresponding to the metal electrode 5 is further arranged on the second insulating layer. And the metal electrode 5 is led out by coating metal paste in the electrode lead-out groove. Wherein, for the opening position of the electrode lead-out groove, as long as it is ensured to correspond to each metal electrode 5, the shape of the electrode lead-out groove opening can be circular, oval, rectangular, trapezoidal, etc., and the utility model does not make specific limitation hereon.

[0044] In conclusion, the back contact solar cell provided by the embodiment of the utility model, by setting the first insulating layer containing electrode groove outside the carrier collection layer, and setting the second insulating layer outside the metal electrode and the first insulating layer, the back contact solar cell structure with the metal electrode pre-buried inside the insulating layer is obtained, so that the metal electrode is directly connected with the carrier collection layer, not only realizes the current export, but also improves the appearance beautification degree of the solar cell while protecting the metal electrode by the second insulating layer.

[0045] In an embodiment of the utility model, the back contact solar cell shown above Figure 15 The back contact solar cell is prepared by the following preparation method, specifically, as shown in Figure 1 The preparation method can include the following steps:

[0046] Step S101, the first carrier collection layer 2 and the second carrier collection layer 3 are prepared on the first main surface of the silicon base 1 in alternation, wherein the type of the first carrier collection layer 2 and the type of the second carrier collection layer 3 are opposite, and there is no electrical connection between the first carrier collection layer 2 and the second carrier collection layer 3;

[0047] Step S102, the first insulating layer is prepared outside the first carrier collection layer 2 and the second carrier collection layer 3, and the spaced electrode groove 4 is prepared on the first insulating layer, wherein each electrode groove 4 corresponds to the first carrier collection layer 2 or the second carrier collection layer 3;

[0048] Step S103, the metal electrode 5 is formed in the electrode groove 4, so that the metal electrode 5 is stacked outside the first carrier collection layer 2 or the second carrier collection layer 3;

[0049] Step S104, the second insulating layer is prepared outside the metal electrode 5 and outside the first insulating layer, so that the metal electrode 5 is buried inside the second insulating layer.

[0050] In the prior art solar cell preparation process, a passivation layer is usually prepared directly outside the first carrier collection layer 2 and the second carrier collection layer 3, and then metal paste is coated on the passivation layer in an interval manner, and the metal paste is penetrated into the passivation layer to connect with the first carrier collection layer 2 and the second carrier collection layer 3 respectively through sintering, so as to realize the current export. In the process of coating the metal paste, a screen or a screen plate is inevitably used, and with the increasing use times, more and more metal paste will be adhered on the screen or the screen plate, so that more metal paste needs to be consumed in the coating process to realize effective coating, and there is a risk of broken grid. Therefore, the electrode groove 4 is arranged in step S103, so that the metal electrode 5 located in the electrode groove 4 can be directly connected with the first carrier collection layer 2 or the second carrier collection layer 3, and the process of coating the metal paste and sintering in the prior art is no longer needed, which not only simplifies the preparation process, but also saves the consumption of the metal paste in the coating process. In addition, the second insulating layer is prepared outside the metal electrode 5 and the first insulating layer in step S104, which can further improve the overall aesthetic appearance of the solar cell compared with the prior art of exposing the metal electrode 5, and since the metal electrode 5 in the embodiment of the utility model does not directly contact with the outside world, other metals (such as copper) with certain activity but more inexpensive can be selected in addition to silver, which greatly reduces the overall cost of the solar cell.

[0051] The preparation method of the embodiment of the utility model will be described in detail below.

[0052] For the process of preparing the first carrier collection layer 2 and the second carrier collection layer 3 in step S101, an optional embodiment includes: Figure 2 As shown in the figure, it includes:

[0053] Step S201, a first doped layer 21 doped with a first element is prepared on part of the first main surface of the silicon substrate 1, and a second doped layer 31 doped with a second element is prepared on the area of the first main surface where the first doped layer 21 is not arranged, to obtain a first area 11 with the first doped layer 21 and a second area 12 with the second doped layer 31;

[0054] Step S202, a tunneling oxide structure 6 is prepared outside the first doped layer 21 and the second doped layer 31, and the tunneling oxide structure 6 of the edge area 121 of the second area 12 close to the first doped layer 21 is removed, to form a first carrier collection layer 2 including the first doped layer 21 and the tunneling oxide structure 6, and a second carrier collection layer 3 including the second doped layer 31 and the tunneling oxide structure 6.

[0055] Exemplarily, the cross-sectional structure of the silicon substrate prepared in step S201 is as shown in the figure.Figure 3 As shown in FIG. 2, the cross-sectional structure of the silicon substrate obtained in step S202 is as shown in FIG. 3. Figure 4 As shown in FIG. 4, the cross-sectional structure of the silicon substrate obtained in step S203 is as shown in FIG. 5. Figure 3 As shown in FIG. 6, the cross-sectional structure of the silicon substrate obtained in step S204 is as shown in FIG. 7. Figure 4 As can be seen, the first doped layer 21 is prepared on the back surface of the silicon substrate 1 by lamination, and the second doped layer 31 is formed on the surface of the silicon substrate 1 by doping the second element on the back surface of the silicon substrate 1. Specifically, when the silicon substrate 1 is an n-type silicon substrate, the first element can be boron element, and the second element can be phosphorus element.

[0056] For step S201, in a further optional embodiment, the first doped layer 21 can be prepared first and then the second doped layer 31 is prepared, as shown in FIG. 8, which includes: Figure 5

[0057] Step S501, preparing a first doped layer 21 doped with a first doped element on a first main surface of a silicon substrate 1;

[0058] Step S502, removing the first doped layer 21 corresponding to the second region 12, and preparing a protective layer 7 outside the remaining first doped layer 21;

[0059] Step S503, doping a second element on the first main surface to form a second doped layer 31 on the second region 12 by using the protective layer 7, and removing the protective layer 7 after the doping is completed.

[0060] Exemplarily, Figures 6 to 8 FIG. 9 shows a cross-sectional structure of a silicon substrate obtained in step S501, FIG. 10 shows a cross-sectional structure of a silicon substrate obtained in step S502, and FIG. 11 shows a cross-sectional structure of a silicon substrate obtained in step S503. Figure 6 As shown in FIG. 9, the cross-sectional structure of the silicon substrate obtained in step S501 is as shown in FIG. 10. Figure 7 As shown in FIG. 11, the cross-sectional structure of the silicon substrate obtained in step S503 is as shown in FIG. 12. Figure 8 As shown in FIG. 11, the cross-sectional structure of the silicon substrate obtained in step S503 is as shown in FIG. 12. Figures 6 to 8 As can be seen, the protective layer 7 outside the first region 11 is used to protect the first doped layer 21 prepared in advance, avoiding the influence of the second element on the first doped layer 21 in the doping process, thereby realizing the process of preparing the first doped layer 21 and the second doped layer 31 in different regions. It can be understood that after the protective layer 7 is removed in step S503, the cross-sectional structure of the silicon substrate shown in FIG. 13 can be obtained. Figure 3 As shown in FIG. 11, the cross-sectional structure of the silicon substrate obtained in step S503 is as shown in FIG. 12.

[0061] ​Specifically, the protective layer 7 can be further divided into a multi-layered structure. Since the protective layer 7 does not exist in the final solar cell structure, but only serves to protect the first doped layer 21 during the fabrication of the second doped layer 31, the structure of the protective layer 7 also needs to facilitate subsequent removal processes. In a further optional embodiment, the process of fabricating the protective layer 7 in step S502 is as follows: Figure 9 As shown, it includes:

[0062] Step S901: Use a laser to remove the first doped layer 21 corresponding to the second region 12, and prepare a passivation layer 71 on the outside of the second region 12 and the remaining first doped layer 21.

[0063] Step S902: Coat a photoresist layer 72 on the outside of the passivation layer 71, and perform intermittent exposure on the photoresist layer 72.

[0064] In step S903, the portion of the photoresist layer 72 corresponding to the first region 11 and the portion of the passivation layer 71 corresponding to the first region 11 are removed respectively to obtain the protective layer 7.

[0065] The positions of the passivation layer 71 and the photoresist layer 72 are already... Figure 8 As indicated in this embodiment of the invention, the passivation layer 71 is relatively thin, which makes it easier to remove and protects the first doped layer 21 from the influence of the photoresist layer 72 during the polymerization reaction. In an optional embodiment, the passivation layer 71 is made of silicon dioxide and has a thickness between 0.5 nm and 1.5 nm, preferably 1 nm.

[0066] For the photoresist layer 72, depending on the type of photoresist, it is divided into positive photoresist and negative photoresist, and their reactions to light are also different. For example, when the photoresist is negative, by exposing the first region 11, the photoresist in the first region 11 undergoes a polymerization reaction, becoming a solid photoresist layer 72 that does not dissolve. For the photoresist in the second region 12, only cleaning with a developer is needed to remove the photoresist solution in the second region 12 that has not undergone polymerization. Compared to the laser process commonly used in the prior art for film opening, this embodiment of the invention utilizes the photoresist layer 72 to not only achieve the same regional preparation of the first carrier collection layer 2 and the second carrier collection layer 3, but also avoids laser damage to the silicon substrate caused by the laser process. Furthermore, the removal process is simple; simply immersing the cured photoresist layer 72 in a remover solution is sufficient for quick and effective removal.

[0067] It can be seen that, through the above Figures 2 to 9The embodiment of the utility model realizes the preparation of the first carrier collection layer 2 and the second carrier collection layer 3 of the alternating arrangement in the first main surface of the silicon base 1 by the protection layer 7 including the photoresist layer 72, not only need not the laser film opening process in the prior art, avoids the laser damage to the silicon base, and the process flow is simple.

[0068] For the tunneling oxidation structure 6 in step S202, a multilayer structure can also be provided, and in an optional embodiment, the specific process of step S202 is as shown in the figure, which comprises the following steps. Figure 10

[0069] Step S1001, a tunneling oxidation layer 61 and an intrinsic polysilicon layer 62 are prepared outside the first doped layer 21 and the second doped layer 31 in a stacked manner to obtain a tunneling oxidation structure 6.

[0070] Step S1002, the tunneling oxidation structure 6 corresponding to the edge area 121 is removed by using a laser process.

[0071] It can be seen that in the embodiment of the utility model, the tunneling oxidation structure 6 is composed of the tunneling oxidation layer 61 and the intrinsic polysilicon layer 62 provided in a stacked manner, wherein the tunneling oxidation layer 61 is used to separate electrons and holes, and the thickness is 1nm-2nm. If the tunneling oxidation layer 61 is too thick, it will hinder the tunneling transmission of most carriers, resulting in a decrease in the open-circuit voltage (OCV) of the battery, thereby affecting the energy conversion efficiency of the battery. At the same time, uneven thickness or excessive thickness will cause problems in the use process of the battery, affecting its long-term stability. The intrinsic polysilicon layer 62 is responsible for transmitting electrons or holes, and through the selection of its doping concentration and crystal structure, efficient carrier transmission is realized; at the same time, carrier recombination is reduced, the open-circuit voltage and the fill factor of the battery are improved, and the overall photoelectric conversion efficiency is also improved.

[0072] Exemplarily, Figures 11 to 12 The cross-sectional structure of the silicon base prepared by the above steps S1001 and S1002 is shown in the figure. Figure 11 As shown in the figure, the preparation of the tunneling oxidation layer 61 on the back surface of the silicon base 1 can be carried out by a CVD deposition method in an oxygen environment, that is, the tunneling oxidation layer 61 is formed outside the first doped layer 21 and the second doped layer 31. Then, the intrinsic polysilicon layer 62 is deposited outside the tunneling oxidation layer 61 in an SiH4 environment, so as to obtain the tunneling oxidation structure 6 outside the first doped layer 21 and the second doped layer 31. Figure 12 ​As shown, in order to ensure that the current between the first carrier collection layer 2 and the second carrier collection layer 3 does not appear to be a conduction short circuit problem, in the second area 12 in the recessed position, the edge area 121 close to the two sides of the first area 11 needs to be slotted to ensure the spacing between the first carrier collection layer 2 and the second carrier collection layer 3. Therefore, in step S1002 of the embodiment of the utility model, the corresponding tunneling oxidation structure 6 of the edge area 121 needs to be removed by using a laser process.

[0073] For step S102, since the corresponding tunneling oxidation structure 6 of the edge area 121 is actually removed in step S1002, in an optional embodiment, after the first insulating layer is prepared in step S102, the cross-sectional structure of the silicon substrate obtained is as shown in Figure 13 As shown, and after the spaced electrode grooves 4 are prepared on the first insulating layer, the cross-sectional structure obtained is as shown in Figure 14 As shown in Figure 13 And Figure 14 It can be seen that only the first insulating layer in the edge area 121 is actually retained, which is to isolate the electron transmission between the first carrier collection layer 2 and the second carrier collection layer 3, and to provide a preparation space for the metal electrode 5 through the electrode grooves 4 arranged in the first area 11 and the second area 12. In an optional embodiment, the material of the first insulating layer is silicon nitride, and the silicon nitride is removed at intervals by using a laser technology to obtain the spaced electrode grooves 4.

[0074] For step S103, in an optional embodiment of the utility model, at least one of the CVD deposition technology and the ALD deposition technology can be used to deposit the metal electrode 5 in the electrode groove 4. The advantage of this preparation method is that, compared with the use of noble metal silver in the prior art, the embodiment of the utility model can grow inexpensive metal as the metal electrode 5 in the electrode groove 4 by deposition, such as depositing copper ions. In the sintering process of the prior art, it is not possible to sinter copper ions with high activity, but only inert metals can be sintered.

[0075] In an optional embodiment, the depth of the electrode groove 4 is 5 μm ~ 10 μm, such as 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc. For the width of the electrode groove 4, in another optional embodiment, the width of the electrode groove 4 is 16 μm ~ 26 μm, such as 16 μm, 20 μm, 24 μm, 26 μm, etc.

[0076] It is understood that the growth of the metal electrode 5 is limited by the width and depth of the electrode groove 4. Therefore, in a further optional embodiment, the size of the metal electrode 5 is not greater than the size of the electrode groove 4. In the actual preparation process, metal ions are not necessarily completely deposited in the electrode groove 4. Therefore, the thickness of the metal electrode 5 may differ from that of the electrode groove 4. In a further optional embodiment, the metal electrode 5 in this invention fills the electrode groove 4, that is, the thickness of the metal electrode 5 is 5μm~10μm, such as 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc. The width of its growth is often limited by the width of the electrode groove 4. Therefore, in an optional embodiment, the width of the metal electrode 5 is also 16μm~26μm, such as 16μm, 20μm, 24μm, 26μm, etc.

[0077] In addition, the metal electrode 5 in the electrode groove 4 can only correspond to the first carrier collection layer 2 or the second carrier collection layer 3, and cannot be set in the intersection area of ​​the first carrier collection layer 2 and the second carrier collection layer 3.

[0078] The following is based on Figure 15 The cross-sectional structure of the silicon substrate obtained in step S104 will be explained using an example. Figure 15 As shown, the second insulating layer is disposed outside the first insulating layer and the metal electrode 5, completely covering the back of the solar cell, thereby achieving the effect of embedding the metal electrode 5 and improving the aesthetics of the solar cell. In an optional embodiment, the second insulating layer can be made of the same material as the first insulating layer, so that after the second insulating layer is prepared, it can be combined with the first insulating layer to form a complete insulating layer, realizing the encapsulation of the metal electrode 5 and ensuring the sealing of the metal electrode 5.

[0079] It should be noted that, to facilitate the subsequent connection of the metal electrodes 5, in a further optional embodiment, grooves can be made in the second insulating layer to obtain electrode lead-out grooves, and metal paste can be applied to the electrode lead-out grooves to conduct the current in the metal electrodes 5. The location of the electrode lead-out grooves only needs to correspond to each metal electrode 5, and the shape of the electrode lead-out groove openings can be circular, elliptical, rectangular, trapezoidal, etc., and this invention does not impose specific limitations on this.

[0080] The preparation method of the solar cell provided by the embodiment of the utility model, through the first insulating layer containing electrode groove prepared outside the carrier collection layer, and the second insulating layer prepared outside the metal electrode and the first insulating layer, the back contact solar cell structure with the metal electrode pre-buried in the insulating layer is obtained, so that the metal electrode can be directly connected with the carrier collection layer without the silk screen printing and sintering process, the double process of the silk screen printing and sintering in the prior art is saved. The second insulating layer arranged outside the metal electrode can encapsulate the metal electrode, protect the metal electrode, and improve the appearance beautification degree of the solar cell.

[0081] The above steps are provided for helping to understand the structure, method and core idea of the utility model. For ordinary skilled in the art, without departing from the principle of the utility model, the utility model can be improved and modified in several ways, and these improvements and modifications also belong to the protection scope of the utility model claims.

Claims

1. A back contact solar cell, characterized by, Comprise: a silicon substrate (1), a first carrier collection layer (2) and a second carrier collection layer (3) arranged alternately on a first main surface of the silicon substrate, a first insulating layer arranged outside the second carrier collection layer (3) and spaced from the first carrier collection layer (2), and a second insulating layer arranged outside the first insulating layer; wherein the type of the first carrier collection layer (2) and the type of the second carrier collection layer (3) are opposite, and there is no electrical connection between the first carrier collection layer (2) and the second carrier collection layer (3); an electrode groove (4) is formed between each adjacent two first insulating layers, wherein each electrode groove (4) corresponds to the first carrier collection layer (2) or the second carrier collection layer (3); a metal electrode (5) is further arranged in the electrode groove (4) and is arranged outside the first carrier collection layer (2) or the second carrier collection layer (3), and the second insulating layer is arranged outside the metal electrode (5) to embed the metal electrode (5) inside the second insulating layer.

2. The back contact solar cell according to claim 1, wherein the first carrier collection layer (2) comprises a first doped layer (21) and a tunneling oxide structure (6) arranged in layers; the second carrier collection layer (3) comprises a second doped layer (31) and a tunneling oxide structure (6) arranged in layers, and the tunneling oxide structure (6) does not cover an edge region (121) of the second doped layer (31) close to the first doped layer (21), and the first insulating layer is arranged at the edge region (121).

3. The back contact solar cell according to claim 2, wherein the width of the edge region (121) is 10nm-100nm.

4. The back contact solar cell according to claim 2, wherein the tunneling oxide structure (6) comprises a tunneling oxide layer (61) and an intrinsic polysilicon layer (62) arranged in layers.

5. The back contact solar cell according to claim 4, wherein the thickness of the tunneling oxide layer (61) is 1nm-2nm; and / or the thickness of the intrinsic polysilicon layer (62) is 110nm-150nm.

6. The back contact solar cell according to any one of claims 1-5, wherein the first insulating layer comprises at least one of the following materials: silicon nitride or silicon dioxide; and / or the second insulating layer comprises at least one of the following materials: silicon nitride or silicon dioxide.

7. The back contact solar cell according to claim 1, wherein an electrode lead-out groove corresponding to the metal electrode (5) is further arranged on the second insulating layer.

8. The back contact solar cell according to claim 1, wherein the size of the metal electrode (5) is not greater than the size of the electrode groove (4).

9. The back contact solar cell according to claim 1 or 8, wherein The depth of the electrode groove (4) is 5-10 μm; And / or, The width of the electrode groove (4) is 16-26 μm.

10. The back contact solar cell of claim 1, wherein, The material of the metal electrode (5) comprises at least one of copper, titanium, nickel, silver and aluminum.

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