Reference voltage buffer and analog-to-digital converter
By optimizing the reference voltage buffer through closed-loop feedback and open-loop output unit, increasing the charging current, reducing the charging time constant, and using passive circuits and voltage regulation circuits to accelerate the output voltage recovery, the problem of slow response speed of the reference voltage buffer is solved, and higher-speed analog-to-digital converter performance is achieved.
Patent Information
- Application Number
- CN202520033328.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2035-01-07
AI Technical Summary
Existing reference voltage buffers have a slow response speed, especially when pulled down by capacitive loads, resulting in slow output voltage recovery and affecting the high-speed and high-precision performance of analog-to-digital converters.
By employing a closed-loop feedback unit and an open-loop output unit, the output voltage is controlled through error amplification, the charging current is increased, the charging time constant is reduced, and passive circuits and voltage regulator circuits are used to accelerate the voltage recovery speed of the output capacitor, thus optimizing the open-loop output structure of the subsequent stage.
It significantly shortens the output voltage recovery time, improves the conversion speed and accuracy of the analog-to-digital converter, reduces circuit power consumption, and reduces chip area.
Smart Images
Figure CN223650936U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of reference voltage design, specifically relating to a reference voltage buffer and an analog-to-digital converter. Background Technology
[0002] As people's demands for communication speed and audio / video clarity increase, analog-to-digital converters (ADCs), as essential front-ends for digital signal processing, determine the performance of digital systems. With the increasing pursuit of high-speed, low-noise signals, high-speed, high-precision ADCs have become a research hotspot in the IC industry.
[0003] The reference voltage buffer is a core module in ADC design. The signal characteristics of the reference voltage determine the ADC's speed, noise, and power consumption. To achieve high-speed conversion and high accuracy, the reference voltage needs to recover its original value and remain stable within a very short time. This means the reference voltage buffer needs to provide a large current to compensate for the drawn charge within a very short time. Therefore, designing a stable and fast reference voltage buffer is of great significance. Utility Model Content
[0004] To address the technical problem of slow stabilization speed of reference voltage buffers in existing technologies, this invention proposes a reference voltage buffer and an analog-to-digital converter, comprising:
[0005] A closed-loop feedback unit amplifies the error between the reference voltage and the feedback voltage to control the output of a first output voltage, wherein the feedback voltage characterizes the first output voltage.
[0006] An open-loop output unit includes an output circuit and an adjustment circuit. The output circuit generates a second output voltage following the first output voltage. When a capacitive load pulls down the second output voltage, the adjustment circuit accelerates the recovery speed of the voltage of the output capacitor in the output circuit.
[0007] Furthermore, the adjustment circuit accelerates the recovery speed by increasing the charging current of the output capacitor and decreasing the charging time constant of the output capacitor.
[0008] Furthermore, when the capacitive load pulls down the second output voltage, the regulating circuit controls the output impedance of the output circuit to decrease, thereby reducing the charging time constant.
[0009] Furthermore, the output terminal of the output circuit is located between the power supply terminal and the ground terminal. When the capacitive load pulls down the second output voltage, the regulating circuit controls the current flowing from the output terminal to the ground terminal to decrease, thereby increasing the charging current.
[0010] Furthermore, the closed-loop feedback unit includes a first power transistor, and the output circuit includes a second power transistor. The gate of the first power transistor receives a compensation voltage, and the gate of the second power transistor is connected to the gate of the first power transistor. The first terminals of the first power transistor and the second power transistor are output terminals.
[0011] The reference voltage and the feedback voltage are amplified to generate the compensation voltage. The first power transistor and the second power transistor are of the same type and operate in the saturation region. The currents of the first power transistor and the second power transistor are in a first ratio, and the width-to-length ratio of the first power transistor and the second power transistor is in a first ratio.
[0012] Furthermore, the open-loop output unit also includes a voltage regulator circuit, through which the gate of the second power transistor is connected to the gate of the first power transistor. When the second output voltage is pulled down, the voltage regulator circuit stabilizes the gate voltages of the second power transistor and the first power transistor.
[0013] Furthermore, the regulating circuit and the voltage stabilizing circuit are passive circuits.
[0014] Preferably, the voltage regulator circuit includes a first resistor and a first capacitor connected in series, the gate of the first power transistor is connected to the gate of the second power transistor through the first resistor, and the gate of the second power transistor is connected to the positive terminal of the first capacitor.
[0015] Preferably, the output circuit includes a third power transistor connected between the output terminal and the ground terminal, and the adjustment circuit includes a second capacitor connected between the output terminal and the gate of the third power transistor.
[0016] Furthermore, the closed-loop feedback unit also includes a first current generating circuit that outputs a first current, and the output circuit includes a second current generating circuit that outputs a second current. The output terminal of the first current generating circuit is connected to the first terminal of the first power transistor, and the output terminal of the second current generating circuit is connected to the first terminal of the second power transistor. The first current and the second current are in a first ratio.
[0017] Furthermore, the first current generating circuit includes a first current mirror, the second current generating circuit includes a second current mirror, and the first current mirror and the second current mirror include a basic current mirror and a common-source cascode current mirror.
[0018] Furthermore, the first current mirror includes a reference circuit and a first mirror circuit connected together, and the second current mirror includes the reference circuit and the second mirror circuit connected together. The reference circuit generates a reference current, and the second mirror circuit is connected to the reference circuit through a second resistor.
[0019] An analog-to-digital converter (ADC) wherein the reference voltage output by the reference voltage buffer described above charges the capacitor array of the ADC.
[0020] Furthermore, the reference voltage buffer and the analog-to-digital converter are integrated on a single chip.
[0021] The reference voltage buffer proposed in this invention optimizes the open-loop output structure of the subsequent stage. When the output voltage of the open-loop output structure of the subsequent stage is pulled down by the analog-to-digital converter, the regulating circuit controls the output voltage of the open-loop output structure of the subsequent stage to be quickly established. Therefore, the reference voltage buffer can be applied to higher speed analog-to-digital converters. Attached Figure Description
[0022] Figure 1 It is a traditional reference voltage buffer;
[0023] Figure 2 The setup time for the existing reference voltage buffer;
[0024] Figure 3 This is a structural diagram of the reference voltage buffer proposed in this utility model;
[0025] Figure 4 This is a circuit diagram of the reference voltage buffer in the first embodiment;
[0026] Figure 5 This is a circuit diagram of the reference voltage buffer in the second embodiment;
[0027] Figure 6 The settling time of the reference voltage buffer proposed in this utility model. Detailed Implementation
[0028] To facilitate understanding of this utility model, a more comprehensive description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this utility model. However, this utility model can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this utility model.
[0029] like Figure 1The conventional reference voltage buffer shown uses an operational amplifier (OPA), power transistor M1, and resistor R1 to form a closed-loop feedback structure in the front stage, while power transistor M2 and resistor R2 form an open-loop source follower structure in the rear stage. Through adjustment of the closed-loop feedback structure, the voltage VFB_OUT stabilizes at VREF. Simultaneously, by setting the current and aspect ratio of power transistors M1 and M2 to be proportional, both operating in the saturation region, and sharing a common gate, VBUF_OUT follows VFB_OUT, thus enabling the open-loop source follower structure to output VREF. The open-loop output of the reference voltage buffer allows for higher bandwidth and faster response speed.
[0030] However, in traditional reference voltage buffers, the output current varies significantly with PVT (process corner, voltage, temperature), leading to large fluctuations in output current and consequently, significant power consumption fluctuations. Therefore, some existing reference voltage buffers have been improved by replacing resistors R1 and R2 with a current mirror structure to reduce the output current variation with PVT. However, the improved reference voltage buffer still has a slow response time; when the output is pulled down, it takes a relatively long time to build up VREF.
[0031] To address the issue of slow response speed in existing reference voltage buffers, this invention proposes a reference voltage buffer comprising: a front-end closed-loop feedback unit and a rear-end open-loop output unit, wherein...
[0032] The closed-loop feedback unit amplifies the error between the reference voltage and the feedback voltage to control the output of the first output voltage, and the feedback voltage characterizes the first output voltage.
[0033] The open-loop output unit includes an output circuit and a regulation circuit, wherein,
[0034] The output circuit generates a second output voltage following the first output voltage. An output capacitor is connected to the output terminal of the output circuit. Under steady-state conditions, the voltage across the output capacitor serves as a reference voltage, acting as the output of a reference voltage buffer.
[0035] When a capacitive load pulls down the second output voltage, the regulating circuit speeds up the recovery of the output capacitor voltage. It should be noted that this reference voltage buffer is suitable for capacitive loads; if a resistive load is connected to the output terminal, it will cause a deviation in the output voltage.
[0036] Furthermore, the regulating circuit accelerates the voltage recovery speed of the output capacitor by increasing the charging current of the output capacitor and decreasing the charging time constant of the output capacitor.
[0037] Preferably, when the capacitive load rapidly pulls down the second output voltage (which can be considered as the output terminal receiving a high-frequency AC signal), the regulating circuit controls the output impedance of the output circuit to decrease, thereby reducing the charging time constant of the output capacitor and accelerating the voltage recovery speed of the output capacitor. Simultaneously, since the output terminal of the output circuit is located between the power supply terminal and the ground terminal, when the second output voltage is rapidly pulled down, the regulating circuit reduces the current flowing from the output terminal to the ground terminal, thereby increasing the current flowing out of the output terminal, i.e., increasing the charging current of the output capacitor, and further accelerating the voltage recovery speed of the output capacitor.
[0038] Therefore, compared with the reference voltage buffer in the prior art, the reference voltage buffer proposed in this invention optimizes the open-loop output structure of the subsequent stage. When the output voltage of the open-loop output structure of the subsequent stage is pulled down by the analog-to-digital converter, the regulating circuit controls the output voltage of the open-loop output structure of the subsequent stage to be quickly established. Thus, the reference voltage buffer can be applied to higher speed analog-to-digital converters.
[0039] Furthermore, the regulation circuit is a passive circuit. Passive circuits can avoid increasing circuit power consumption when the reference voltage buffer speeds up the voltage recovery of the output capacitor. At the same time, compared with active circuits, it can also effectively reduce the chip area occupied.
[0040] Specifically, such as Figure 3 As shown, the closed-loop feedback unit includes a power transistor M1 and a first current generation circuit. The output circuit includes a power transistor M2 and a second current generation circuit. The output terminal of the first current generation circuit is connected to the first terminal of the power transistor M1, and the first current generation circuit generates a first current. The output terminal of the second current generation circuit is connected to the first terminal of the power transistor M2, and the second current generation circuit generates a second current. The first terminal of the power transistor M1 is the output terminal of the closed-loop feedback unit, and the first terminal of the power transistor M2 is the output terminal of the output circuit. The gate of the power transistor M2 is connected to the gate of the power transistor M1, and the gate of the power transistor M1 receives a compensation voltage (the result of a differential operational amplifier of the reference voltage and the feedback voltage). Power transistors M1 and M2 are of the same type and both operate in the saturation region. The ratio of the first current flowing through power transistor M1 to the second current flowing through power transistor M2 is equal to k1, and the ratio of the width-to-length ratio of power transistor M1 to the width-to-length ratio of power transistor M2 is also equal to k1. Therefore, according to the formula for calculating the saturation region current: It is obvious that the second output voltage can follow the first output voltage, that is, the second output voltage can be equal to the reference voltage under steady state.
[0041] However, it is undeniable that due to the gate-source parasitic capacitance Cgs of power transistor M2, when the second output voltage is pulled down by the analog-to-digital converter, the gate voltage of power transistor M2 will be affected and reduced, thus slowing down the build-up speed of the output capacitor voltage. To address the problem of slow output build-up speed caused by the gate-source parasitic capacitance Cgs of power transistor M2 when the second output voltage is pulled down, this invention also includes a voltage regulator circuit in the open-loop output unit. The gate of power transistor M2 is connected to the gate of power transistor M1 via the voltage regulator circuit. When the second output voltage is pulled down, the voltage regulator circuit stabilizes the gate voltages of power transistors M1 and M2, and further increases the gate-source voltage of power transistor M1. This prevents the gate voltages of power transistors M1 and M2 from fluctuating as the second output voltage decreases, and further improves the build-up speed of the output capacitor voltage.
[0042] Furthermore, voltage regulator circuits are also passive circuits. Passive circuits can avoid the reference voltage buffer increasing circuit power consumption when the voltage regulator circuit is regulating voltage, and can also effectively reduce the chip area occupied.
[0043] Preferred, such as Figure 4 As shown, in the first embodiment, the first current generating circuit and the second current generating circuit are basic current mirrors. Specifically, the closed-loop feedback unit includes an operational amplifier OPA, power transistors M1 and M4, the output circuit includes power transistors M2 and M3, the adjustment circuit includes capacitor C2, and the voltage regulator circuit includes resistor R1 and capacitor C1. The specific connection relationships of each device are as follows: Figure 4 As shown, power transistor M5, power supply VDD, and reference current source Iref constitute a reference circuit to generate a reference current. Power transistor M4 mirrors the reference current to output the first current I1, and power transistor M3 mirrors the reference current to output the second current I2. The detailed operation of this reference voltage buffer is as follows:
[0044] Assuming Vout1 and Vout2 are initially zero, the operational amplifier (OPA) amplifies VREF and Vout1 to output a compensation voltage Vc. This compensation voltage Vc controls the gate of power transistor M1, causing it to operate in the saturation region. Through multiple feedback adjustments, at time t1, the voltage of power transistor M1 stabilizes at V1, and Vout1 eventually stabilizes at VREF. Simultaneously, the OPA outputs the compensation voltage Vc again initially. At this time, the gate voltages of capacitor C1 and power transistor M2 are zero, creating a voltage difference across resistor R1. This causes capacitor C1 to charge, increasing the gate voltage of power transistor M2. Vout2 then follows Vout1. After the aforementioned feedback adjustment, at time t1, the gate voltages of power transistor M2 and M1 are equal. At this point, there is no voltage difference across resistor R1, and no current flows through it. Vout2 is stabilized at VREF, and the voltage across capacitor C1 equals V1.
[0045] At time t2, Vout2 charges the capacitor array in the analog-to-digital converter, causing Vout2 to be pulled down rapidly and significantly. Since the gate-source parasitic capacitance Cgs of power transistor M2 leads to a decrease in its gate voltage, but the voltage of capacitor C1 is charged and stabilized to V1 at time t1, capacitor C1 can stabilize the gate voltage of power transistor M2 when Vout2 is pulled down. This further increases the gate-source voltage of power transistor M2, thereby improving the setup speed of Vout2 recovering to VREF. Simultaneously, considering that capacitor C1 cannot ideally stabilize the gate voltage of power transistor M2 to V1 in practice, resistor R1 can reduce the impact of changes in the gate voltage of power transistor M2 on the gate voltage of power transistor M1, improving the stability of the gate voltage of power transistor M1 and thus improving the stability of the operational amplifier (OPA). Furthermore, the presence of resistor R1 avoids connecting a large capacitor C1 between the outputs of the OPA, as the phase margin of the OPA is limited, and direct connection of capacitor C1 to the OPA would lead to an unstable feedback loop. Meanwhile, when Vout2 is rapidly pulled down, capacitor C2 is effectively short-circuited, thus power transistor M3 is short-circuited as a diode. This changes the output impedance of the output circuit from 1 / gmM2 / / Rds_M3 to 1 / gmM2 / / 1 / gmM3. The significantly reduced output impedance decreases the charging time constant of output capacitor Cout, allowing Vout2 to quickly recover to VREF. Simultaneously, because the voltage of capacitor C2 cannot change abruptly, the gate voltage of power transistor M3 is also pulled down synchronously. This reduces the current flowing through power transistor M3 (equivalent to a decrease in the current flowing from the output terminal to ground), thus increasing the current flowing from the output terminal to output capacitor Cout. This again allows Vout2 to quickly recover to VREF.
[0046] Meanwhile, considering that power transistors M3 and M4 share the same reference circuit, the voltage of the first node Vx will be affected when the adjustment circuit is working. Therefore, resistor R2 is also set to stabilize the voltage of the first node Vx. Thus, when Vout2 is pulled down quickly, resistor R2 prevents Vout2 from directly pulling down the voltage of the first node Vx due to the influence of capacitor C2, thereby improving the stability of the operational amplifier OPA.
[0047] like Figure 2 and Figure 6 The simulation results shown are as follows: Figure 2 The figure shows the setup time for the output voltage of the existing reference voltage buffer to be restored to VREF after being pulled down. Figure 6 The diagram shows the settling time for the output voltage of the reference voltage buffer proposed in this invention to recover to VREF after being pulled down. The comparison shows that the settling time of the reference voltage buffer proposed in this invention is significantly shortened, and the settling speed is significantly accelerated.
[0048] Preferred, such as Figure 5 As shown, in the second embodiment, the first current generating circuit and the second current generating circuit are common-source cascode current mirrors, which have higher mirror accuracy to reduce the error of the second output voltage. Specifically, the closed-loop feedback unit includes an operational amplifier OPA, power transistors M1, M8, and M9; the output circuit includes power transistors M2, M6, and M7; the adjustment circuit includes capacitor C2; and the voltage regulator circuit includes resistor R1 and capacitor C1. The specific connection relationships of each component are as follows: Figure 5 As shown, power transistors M10 and M11, the power supply VDD, and the reference current source Iref constitute a reference circuit to generate a reference current. Power transistors M8 and M9 mirror the reference current to output the first current I1, and power transistors M6 and M7 mirror the reference current to output the second current I2. Furthermore, considering that the two current mirror structures share the same reference circuit, the voltage at the first node Vx will be affected during circuit adjustment. Therefore, resistor R2 is also included to stabilize the voltage at the first node Vx. For detailed information on the specific operation of the reference voltage buffer, please refer to [link to relevant documentation]. Figure 4 The reference voltage buffers shown are only different in the specific type of current mirror structure, and the output impedance of the corresponding output circuit is also different. Specifically, after adjustment by the adjustment circuit, the output impedance changes from gmM4*Rds_M4*Rds_M5 to 1 / gmM5.
[0049] In addition, this invention proposes an analog-to-digital converter (ADC) in which the aforementioned reference voltage buffer charges the capacitor array of the ADC. Because the build-up speed of the aforementioned reference voltage buffer is significantly improved, this ADC can be applied to applications with higher input frequencies, thus increasing the conversion speed. Furthermore, the ADC and the reference voltage buffer are integrated on a single chip. Compared to using off-chip capacitors, chip-integrated reference voltage buffers can achieve higher conversion speeds and lower power consumption.
[0050] It should be noted that the specific implementation and corresponding illustrations provided are merely one way of describing the implementation method of this utility model, and are not intended to limit the specific structure of the implementation scheme of this utility model. Various changes or modifications can be made to these implementation methods without departing from the principles and essence of this utility model, but all such changes and modifications fall within the protection scope of this utility model.
[0051] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.
[0052] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.
Claims
1. A reference voltage buffer, characterized in that, include: A closed-loop feedback unit amplifies the error between the reference voltage and the feedback voltage to control the output of a first output voltage, wherein the feedback voltage characterizes the first output voltage. An open-loop output unit includes an output circuit and an adjustment circuit. The output circuit generates a second output voltage following the first output voltage. When a capacitive load pulls down the second output voltage, the adjustment circuit accelerates the recovery speed of the voltage of the output capacitor in the output circuit.
2. The reference voltage buffer as described in claim 1, characterized in that, The regulating circuit accelerates the recovery speed by increasing the charging current of the output capacitor and decreasing the charging time constant of the output capacitor.
3. The reference voltage buffer as described in claim 2, characterized in that, When the capacitive load pulls down the second output voltage, the regulating circuit controls the output impedance of the output circuit to decrease, thereby reducing the charging time constant.
4. The reference voltage buffer as described in claim 2, characterized in that, The output terminal of the output circuit is located between the power supply terminal and the ground terminal. When the capacitive load pulls down the second output voltage, the regulating circuit controls the current flowing from the output terminal to the ground terminal to decrease, so as to increase the charging current.
5. The reference voltage buffer as described in claim 1, characterized in that, The closed-loop feedback unit includes a first power transistor, and the output circuit includes a second power transistor. The gate of the first power transistor receives a compensation voltage, and the gate of the second power transistor is connected to the gate of the first power transistor. The first terminals of the first power transistor and the second power transistor are output terminals. The reference voltage and the feedback voltage are amplified to generate the compensation voltage. The first power transistor and the second power transistor are of the same type and operate in the saturation region. The currents of the first power transistor and the second power transistor are in a first ratio, and the width-to-length ratio of the first power transistor and the second power transistor is in a first ratio.
6. The reference voltage buffer as described in claim 5, characterized in that, The open-loop output unit further includes a voltage regulator circuit. The gate of the second power transistor is connected to the gate of the first power transistor through the voltage regulator circuit. When the second output voltage is pulled down, the voltage regulator circuit stabilizes the gate voltages of the second power transistor and the first power transistor.
7. The reference voltage buffer as described in claim 6, characterized in that, The regulating circuit and the voltage stabilizing circuit are passive circuits.
8. The reference voltage buffer as described in claim 6, characterized in that, The voltage regulator circuit includes a first resistor and a first capacitor connected in series. The gate of the first power transistor is connected to the gate of the second power transistor through the first resistor, and the gate of the second power transistor is connected to the positive terminal of the first capacitor.
9. The reference voltage buffer as described in claim 2, characterized in that, The output circuit includes a third power transistor connected between the output terminal and the ground terminal, and the adjustment circuit includes a second capacitor connected between the output terminal and the gate of the third power transistor.
10. The reference voltage buffer as claimed in claim 5, characterized in that, The closed-loop feedback unit further includes a first current generating circuit that outputs a first current, and the output circuit includes a second current generating circuit that outputs a second current. The output terminal of the first current generating circuit is connected to the first terminal of the first power transistor, and the output terminal of the second current generating circuit is connected to the first terminal of the second power transistor. The first current and the second current are in a first ratio.
11. The reference voltage buffer as claimed in claim 10, characterized in that, The first current generating circuit includes a first current mirror, and the second current generating circuit includes a second current mirror. The first current mirror and the second current mirror include a basic current mirror and a common-source cascode current mirror.
12. The reference voltage buffer as claimed in claim 11, characterized in that, The first current mirror includes a reference circuit and a first mirror circuit connected together, and the second current mirror includes the reference circuit and the second mirror circuit connected together. The reference circuit generates a reference current, and the second mirror circuit is connected to the reference circuit through a second resistor.
13. An analog-to-digital converter, characterized in that, The reference voltage output by the reference voltage buffer according to any one of claims 1-12 charges the capacitor array of the analog-to-digital converter, and the reference voltage buffer and the analog-to-digital converter are integrated on a single chip.