CAN module of Loongson platform

Abstract

The utility model discloses a CAN (Controller Area Network) module of a Loongson platform, which relates to the field of communication and comprises a connector used for connecting a CPU (Central Processing Unit) and a PFGA (Field Programmable Gate Array); the FPGA chip is used for generating multiple paths of CAN signals and outputting the multiple paths of CAN signals to the CAN port chip; the CAN port chip is used for converting the CAN signal into a complete CAN port for outputting; the CAN output module is used for realizing electromagnetic interference suppression and improving signal quality; the connector is connected with the FPGA chip, the FPGA chip is connected with the CAN port chip, and the CAN port chip is connected with the CAN output module; compared with the prior art, the utility model has the beneficial effects that the CPU is connected with the FPGA chip through the connector LIO port, the FPGA chip generates multiple paths of CAN signals, and the CAN signals are converted into complete CAN ports through the CAN port chips to be output.

Description

Technical Field

[0001] This utility model relates to the field of communications, specifically a CAN module for the Loongson platform. Background Technology

[0002] Currently, Loongson CPUs only have two native CAN ports. When using multiple CAN ports in industrial applications, additional expansion is required, necessitating the use of dedicated PCIe port chips for conversion. Furthermore, adding a CAN port requires an additional chip for conversion, resulting in high cost and large size when Loongson CPUs require multiple CAN ports, which necessitates improvement. Utility Model Content

[0003] The purpose of this invention is to provide a CAN module for the Loongson platform to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model provides the following technical solution:

[0005] A CAN module for the Loongson platform, comprising:

[0006] Connector for connecting the CPU and PFGA;

[0007] The FPGA chip is used to generate multiple CAN signals and output them to the CAN port chip.

[0008] CAN port chip, used to convert CAN signals into complete CAN port output;

[0009] The CAN output module is used to suppress electromagnetic interference and improve signal quality.

[0010] The connector connects to the FPGA chip, the FPGA chip connects to the CAN port chip, and the CAN port chip connects to the CAN output module.

[0011] There are multiple CAN port chips and CAN output modules, and the number of CAN port chips and CAN output modules corresponds to the number of CAN output modules.

[0012] As a further improvement of this utility model: the connector model is FPCE30-P5R, the connector is externally connected to the CPU, and pins 1-24 of the connector are connected to the FPGA chip.

[0013] As a further embodiment of this utility model: the FPGA chip includes chip U3, the model of chip U3 is GW1N-UV9QN48C6 / I5, pins 38 to 46, pins 14 to 24, pin 29, and pins 31 to 33 of chip U3 are connected to a connector, and pins 34, 35, 27, 28, 10, and 11 of chip U3 are connected to a CAN port chip.

[0014] As a further improvement of this utility model: the CAN port chip includes chip U1, the model of chip U1 is SIT1040T, pins 1 and 4 of chip U1 are connected to the FPGA chip, and pins 6 and 7 of chip U1 are connected to the CAN output module.

[0015] As a further embodiment of this utility model: the CAN output module includes a resistor R17, a common-mode inductor CHK1, a protection transistor D1, and a protection transistor D2. The first end of the common-mode inductor CHK1 is connected to one end of the resistor R17 and the CAN port chip. The fourth end of the common-mode inductor CHK1 is connected to the other end of the resistor R17 and the CAN port chip. The second end of the common-mode inductor CHK1 is connected to the first end of the protection transistor D2, and the second end of the protection transistor D2 is grounded. The third end of the common-mode inductor CHK1 is connected to the first end of the protection transistor D1, and the second end of the protection transistor D1 is grounded.

[0016] Compared with the prior art, the beneficial effects of this utility model are: this utility model connects the CPU and FPGA chip through the LIO connector, the FPGA chip generates multiple CAN signals, and converts the CAN signals into complete CAN signals for output through the CAN port chip. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a CAN module for the Loongson platform.

[0018] Figure 2 This is the circuit diagram for the connector.

[0019] Figure 3 This is the circuit diagram of an FPGA chip.

[0020] Figure 4 This is a circuit diagram of the CAN port chip and CAN output module. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0022] Please see Figure 1 A CAN module for the Loongson platform, comprising:

[0023] Connector for connecting the CPU and PFGA;

[0024] The FPGA chip is used to generate multiple CAN signals and output them to the CAN port chip.

[0025] CAN port chip, used to convert CAN signals into complete CAN port output;

[0026] The CAN output module is used to suppress electromagnetic interference and improve signal quality.

[0027] The connector connects to the FPGA chip, the FPGA chip connects to the CAN port chip, and the CAN port chip connects to the CAN output module.

[0028] There are multiple CAN port chips and CAN output modules, and the number of CAN port chips and CAN output modules corresponds to the number of CAN output modules.

[0029] In this embodiment: Please refer to Figure 2 The connector model is FPCE30-P5R. The connector is connected to the CPU, and pins 1-24 of the connector are connected to the FPGA chip.

[0030] Here, the CPU and FPGA chips are connected via the LIO port of the connector FPCE30-P5R.

[0031] In this embodiment: Please refer to Figure 3 The FPGA chip includes chip U3, model number GW1N-UV9QN48C6 / I5. Pins 38 to 46, 14 to 24, 29, and 31 to 33 of chip U3 are connected to the connector, and pins 34, 35, 27, 28, 10, and 11 of chip U3 are connected to the CAN port chip.

[0032] The FPGA chip will generate multiple CAN signals, three of which are shown in the attached diagram: CAN1-TX, CAN1-RX, CAN2-TX, CAN2-RX, and CAN3-TX, CAN3-RX. In actual use, additional CAN signal outputs can be added through unused I / O ports. The FPGA chip also includes a programming interface, power supply, crystal oscillator circuit, etc., which are common FPGA chip supporting circuits and will not be described in detail again.

[0033] In this embodiment: Please refer to Figure 4 The CAN port chip includes chip U1, model SIT1040T. Pins 1 and 4 of chip U1 are connected to the FPGA chip, and pins 6 and 7 of chip U1 are connected to the CAN output module.

[0034] The SIT1040T chip converts the CAN signal into a complete CAN port for output, supplying the CAN output module.

[0035] In this embodiment: Please refer to Figure 4The CAN output module includes a resistor R17, a common-mode inductor CHK1, a protection transistor D1, and a protection transistor D2. The first end of the common-mode inductor CHK1 is connected to one end of the resistor R17 and the CAN port chip. The fourth end of the common-mode inductor CHK1 is connected to the other end of the resistor R17 and the CAN port chip. The second end of the common-mode inductor CHK1 is connected to the first end of the protection transistor D2, and the second end of the protection transistor D2 is grounded. The third end of the common-mode inductor CHK1 is connected to the first end of the protection transistor D1, and the second end of the protection transistor D1 is grounded.

[0036] The complete readable signal output from the CAN port passes through the photosensitive inductor CHK1 to suppress electromagnetic interference and improve signal quality. The protective transistors D1 and D2 are designed to conduct to ground and discharge current when the signal suddenly increases, thus preventing damage to the circuit components.

[0037] The working principle of this utility model is as follows: the connector is used to connect the CPU and FPGA; the FPGA chip is used to generate multiple CAN signals and output them to the CAN port chip; the CAN port chip is used to convert the CAN signals into complete CAN port outputs; the CAN output module is used to suppress electromagnetic interference and improve signal quality.

[0038] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects.

[0039] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A CAN module for a Loongson platform, characterized in that, The CAN module of the Loongson platform includes: Connector for connecting the CPU and PFGA; The FPGA chip is used to generate multiple CAN signals and output them to the CAN port chip. CAN port chip, used to convert CAN signals into complete CAN port output; The CAN output module is used to suppress electromagnetic interference and improve signal quality. The connector connects to the FPGA chip, the FPGA chip connects to the CAN port chip, and the CAN port chip connects to the CAN output module. There are multiple CAN port chips and CAN output modules, and the number of CAN port chips and CAN output modules corresponds to the number of CAN output modules.

2. The CAN module of the Loongson platform according to claim 1, characterized in that, The connector model is FPCE30-P5R. The connector is connected to the CPU, and pins 1-24 of the connector are connected to the FPGA chip.

3. The CAN module of the Loongson platform according to claim 1, characterized in that, The FPGA chip includes chip U3, model number GW1N-UV9QN48C6 / I5. Pins 38 to 46, 14 to 24, 29, and 31 to 33 of chip U3 are connected to the connector, and pins 34, 35, 27, 28, 10, and 11 of chip U3 are connected to the CAN port chip.

4. The CAN module of the Loongson platform according to claim 1, characterized in that, The CAN port chip includes chip U1, model SIT1040T. Pins 1 and 4 of chip U1 are connected to the FPGA chip, and pins 6 and 7 of chip U1 are connected to the CAN output module.

5. The CAN module of the Loongson platform according to claim 4, characterized in that, The CAN output module includes a resistor R17, a common-mode inductor CHK1, a protection transistor D1, and a protection transistor D2. The first end of the common-mode inductor CHK1 is connected to one end of the resistor R17 and the CAN port chip. The fourth end of the common-mode inductor CHK1 is connected to the other end of the resistor R17 and the CAN port chip. The second end of the common-mode inductor CHK1 is connected to the first end of the protection transistor D2, and the second end of the protection transistor D2 is grounded. The third end of the common-mode inductor CHK1 is connected to the first end of the protection transistor D1, and the second end of the protection transistor D1 is grounded.

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