Chip packaging structure

Abstract

The utility model provides a chip packaging structure. The chip packaging structure comprises a base island, a chip, a pin, a heat dissipation frame and a plastic packaging material. The chip is fixed to the base island. The pins are located on the periphery of the base island and are electrically connected with the chip. The heat dissipation frame is located on the edge of at least one side of the base island and is of a hollow structure, the top of the heat dissipation frame is higher than the top of the chip, and the bottom of the heat dissipation frame and the chip are arranged at intervals. The molding compound wraps the chip and fills the hollow structure of the heat dissipation frame. And four-side heat dissipation is realized through the heat dissipation frame in a chip packaging process, so that the service life and the reliability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and more specifically, to a chip packaging structure. Background Technology

[0002] In traditional packaging structures, chips generate significant internal heat when operating at high speeds or performing heavy workloads. If this heat is not dissipated effectively and promptly, it can lead to a series of serious consequences. First, the accumulated heat causes the chip's operating temperature to rise, resulting in a significant performance degradation, including slower processing speeds and increased response latency. Furthermore, excessively high temperatures may activate the chip's overheat protection mechanisms, causing the system to automatically slow down or shut down to prevent further damage—unacceptable in mission-critical applications. In extreme cases, sustained high temperatures can even directly burn out the chip's internal circuitry, causing permanent physical damage and resulting in high repair and replacement costs.

[0003] In traditional designs, heat dissipation primarily relies on the bottom region of the chip. This design approach has historical reasons and practicality, as the bottom of the chip needs to establish a stable physical connection with the printed circuit board (PCB) to enable the transmission of electrical signals and secure chip mounting. This connection is typically achieved through precision soldering processes or the use of dedicated sockets, methods that offer excellent electrical performance and mechanical stability. However, it is precisely these connection materials and structures themselves that constitute a significant heat dissipation bottleneck.

[0004] Specifically, soldering materials and connectors have inherent thermal resistance, meaning they impede the smooth transfer of heat from the bottom of the chip to the PCB and even the external environment. As chip performance continues to improve and power consumption increases, the limitations of this heat dissipation path become increasingly apparent. Particularly in high-density packaging and compact designs, space constraints make traditional bottom-heat dissipation methods increasingly inadequate, leading to more prominent chip overheating issues. For example, DFN / PDFN / TOLL / SOP / SOT are common packaging technologies. Using these technologies places higher demands on the heat dissipation performance of the chip packaging structure, thus requiring a chip packaging structure with superior heat dissipation capabilities. Utility Model Content

[0005] In view of the problems existing in the prior art described above, this application provides a chip packaging structure. This structure enables heat dissipation from all four sides during chip packaging, thereby improving the lifespan and reliability of the packaged device.

[0006] To achieve the above and other related objectives, this utility model provides a chip packaging structure, comprising: a base island; a chip fixed to the base island; pins located on the periphery of the base island and electrically connected to the chip; a heat dissipation frame located at at least one edge of the base island, the heat dissipation frame being formed as a hollow structure, the top of the heat dissipation frame being higher than the top of the chip, and the bottom of the heat dissipation frame being spaced apart from the chip; and a molding compound encapsulating the chip and filling the hollow structure of the heat dissipation frame.

[0007] Optionally, the heat dissipation frame is connected to the base island, and the bottom of the heat dissipation frame is part of the base island.

[0008] Optionally, the hollow portion of the hollow structure is rectangular.

[0009] Optionally, the wall thickness of the hollow structure is between 152 μm and 2000 μm.

[0010] Optionally, an adhesive layer is also provided between the chip and the base island, and the adhesive material of the adhesive layer is solder wire material, solder paste material, conductive adhesive material or non-conductive adhesive material.

[0011] Optionally, the thickness of the adhesive layer is between 10 μm and 50 μm.

[0012] Optionally, the heat dissipation frame is a metal frame.

[0013] Optionally, the minimum distance between the edge of the chip and the edge of the base island is between 100μm and 300μm.

[0014] Optionally, the chip package structure also includes leads that connect to the chip and pins, with the leads covered by molding compound.

[0015] Optionally, the lead wire may be gold wire, copper wire, gold-palladium-copper wire, aluminum wire, or a clamp.

[0016] In another aspect, this utility model also provides a chip packaging structure, including: a base island, including a first side, a second side, a third side and a fourth side disposed opposite to each other; pins, located on the second side, the third side and the fourth side of the base island; a heat dissipation frame, located on the first side of the base island, extending upward from the portions of the second side and the fourth side of the base island near the first side and connecting at the top of the chip packaging structure, the heat dissipation frame forming a hollow structure.

[0017] Optionally, the hollow portion of the hollow structure is rectangular.

[0018] Optionally, the heat dissipation frame is a metal frame.

[0019] Optionally, the chip package structure also includes: a chip located on a base island, the top of the chip including solder joints connected to pins via leads.

[0020] Optionally, the chip packaging structure also includes: molding compound, a hollow structure that encapsulates the chip and leads and fills the heat dissipation frame.

[0021] As described above, the chip packaging structure provided by this utility model has at least the following beneficial technical effects: The chip packaging structure of this utility model includes a base island, a chip, pins, a heat sink frame, and a molding compound. The chip is fixed to the base island. The pins are located on the periphery of the base island and are electrically connected to the chip. The heat sink frame is located at at least one edge of the base island, and the heat sink frame is formed as a hollow structure, with the top of the heat sink frame higher than the top of the chip, and the bottom of the heat sink frame spaced apart from the chip. The molding compound encapsulates the chip and fills the hollow structure of the heat sink frame. During the chip packaging process, heat dissipation is achieved on all four sides through the heat sink frame, thereby improving device lifespan and reliability. Attached Figure Description

[0022] Figure 1 The diagram shown is a schematic diagram of a chip packaging structure without molding compound provided in Embodiment 1 of this utility model.

[0023] Figure 2 The image shown is a side view of the unfilled molding compound chip packaging structure provided in Embodiment 1 of this utility model.

[0024] Figure 3 This utility model is shown. Figure 2 A cross-sectional view of the provided chip package structure.

[0025] Figure 4 The image shown is a side view of the chip packaging structure filled with molding compound provided in Embodiment 1 of this utility model.

[0026] Figure 5 This utility model is shown. Figure 4 A cross-sectional view of the provided chip package structure.

[0027] Figure 6 The image shown is an internal top view of the QFN package provided in Embodiment 1 of this utility model.

[0028] Figure 7 The image shown is an internal top view of the TOLL package provided in Embodiment 1 of this utility model.

[0029] Figure 8 The image shown is a top view of the DFN package provided in Embodiment 1 of this utility model.

[0030] Figure 9 The diagram shown is a schematic of the heat dissipation frame provided in Embodiment 1 of this utility model located at the two edges of the base island.

[0031] Figure 10 The diagram shown is a schematic of the heat dissipation frame provided in Embodiment 1 of this utility model located at the three edges of the base island.

[0032] Figure 11 The diagram shown is a flowchart illustrating the manufacturing process of the heat dissipation frame provided in Embodiment 1 of this utility model.

[0033] Figure 12 The image shown is a top view of the internal structure of the QFN package provided in Embodiment 2 of this utility model.

[0034] Figure 13 The diagram shown is a schematic diagram of the unfilled molding compound chip packaging structure provided in Embodiment 2 of this utility model.

[0035] Figure 14 This utility model is shown. Figure 11 A cross-sectional view of the provided chip package structure.

[0036] Figure 15 The diagram shown is a schematic diagram of a chip packaging structure filled with molding compound provided in Embodiment 2 of this utility model.

[0037] Figure 16 This utility model is shown. Figure 13 A cross-sectional view of the provided chip package structure. Detailed Implementation

[0038] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0039] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Although the illustrations only show components related to this utility model and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this utility model, and the layout of the components may also be more complex.

[0040] In traditional packaging structures, chips generate significant heat when operating at high speeds or performing heavy workloads. If this heat is not dissipated effectively and promptly, it can not only degrade chip performance but also trigger overheat protection mechanisms and even damage the chip. In traditional designs, heat dissipation primarily relies on the bottom of the chip. However, this heat dissipation path has significant limitations: the bottom of the chip needs to be physically connected to the printed circuit board (PCB) for electrical signal transmission and chip fixation. This connection is typically achieved through soldering or the use of sockets, and these connection materials and structures themselves have thermal resistance, hindering the smooth dissipation of heat.

[0041] To address the above problems, this application provides a chip packaging structure that achieves four-sided heat dissipation through a heat dissipation frame during chip packaging, thereby improving device lifespan and reliability. A detailed description is now provided in conjunction with the following embodiments and accompanying drawings.

[0042] Example 1

[0043] This embodiment provides a chip packaging structure, referring to... Figure 1 and Figure 4 The chip packaging structure includes a base island 1, a heat dissipation frame 2, a chip 3, pins 5, leads 6, and molding compound 7.

[0044] like Figure 6 As shown, pin 5 is located on the periphery of base island 1 and is electrically connected to chip 3 via lead 6. Lead 6 can be gold wire, copper wire, gold-palladium-copper wire, aluminum wire, or a clamp. Figure 1 As shown, chip 3 is mounted to base island 1 via adhesive layer 4. During mounting, chip 3 must avoid contact with the heat dissipation frame 2 to prevent chip 3 from breaking. To ensure safe mounting of chip 3, while considering the compactness of the chip package structure and heat dissipation efficiency, the minimum distance between the edge of chip 3 and base island 1 is between 100μm and 300μm. Various options are provided for the material selection of adhesive layer 4 to meet different application requirements. Optionally, the adhesive material of adhesive layer 4 can be solder wire, solder paste, conductive adhesive, or non-conductive adhesive. The thickness of adhesive layer 4 is between 10μm and 50μm, and its thickness can be specifically set according to the different materials of the adhesive layer. Specifically, for example, when the adhesive layer is solder wire, the thickness of the solder wire is between 20μm and 50μm; for example, when the adhesive layer is solder paste, the thickness of the solder paste is between 10μm and 20μm; for example, when the adhesive layer is conductive adhesive or non-conductive adhesive, the thickness of the conductive adhesive and non-conductive adhesive is between 10μm and 30μm. To prevent the adhesive material of the adhesive layer 4 from adhering to the top of the chip 3 and causing a short circuit in the chip package structure, the height of the adhesive layer 4 on the side of the chip 3 must be controlled to be less than or equal to 90% of the thickness of the chip 3. This ensures that the adhesive material will not accidentally cover the top of the chip 3, thereby ensuring the reliability of the chip package structure. The thickness of the chip 3 is typically between 80μm and 300μm. This thickness range ensures that the chip 3 has sufficient mechanical strength, while the chip 3 will not be too thick and affect the overall package height and performance of the chip package structure.

[0045] Reference Figure 11 The manufacturing process of heat dissipation frame 2 includes stamping, cleaning, film pressing, exposure, development, etching, and film stripping. (Refer to...) Figure 1 and Figure 2The heat dissipation frame 2 is located at at least one edge of the base island 1. The heat dissipation frame 2 is formed as a hollow structure 21 and includes a top 22, a bottom 23, a left side wall 24, and a right side wall 25 arranged opposite to each other. The bottom 23 of the heat dissipation frame 2 is spaced apart from the chip 3. This design avoids potential physical interference and provides additional space for heat dissipation. The design of the heat dissipation frame 2 needs to consider not only its heat dissipation performance but also its impact on the overall package size, compatibility with the base island 1 and the chip 3, and manufacturing costs. Because different chip 3 packages have different forms, the placement of the heat dissipation frame 2 varies. For example, in the optional embodiment of this first embodiment, such as... Figure 6 As shown, wire bonding is performed on chip 3 along the solder points 31 on three sides of chip 3, and multiple leads 6 connect pins 5 to the solder points 31 of chip 3. At this time, the heat dissipation frame 2 is located on one side of the base island 1 where the side of chip 3 that does not require wire bonding is located. Due to its excellent heat dissipation performance, the chip packaging structure of this application is particularly suitable for devices with high heat dissipation requirements. For example, in DFN / PDFN / TOLL / SOP / SOT packaging forms, refer to... Figures 7 to 10 In TOLL and DFN packaging, only one side requires wire bonding. In this case, the heat dissipation frame 2 can be placed on one side of the base island 1 where any side of the chip 3 that does not require wire bonding is located, or it can be placed on both sides of the base island 1 where both sides of the chip 3 that does not require wire bonding are located, or on three sides of the base island 1 where three sides of the chip 3 that does not require wire bonding are located. However, placing the heat dissipation frame 2 on the edges of both sides or three sides of the base island 1 would significantly increase the package size, which would affect the overall design and manufacturing cost of the electronic product. Therefore, from the perspective of practicality and economy, it is preferable to place the heat dissipation frame 2 only on one edge of the base island 1.

[0046] Reference Figure 1The design of the heat dissipation frame 2 is the core of the four-sided heat dissipation strategy, allowing heat to be effectively dissipated from multiple directions of the chip 3. To ensure four-sided heat dissipation, the top 22 of the heat dissipation frame 2 is higher than the top of the chip 3, ensuring sufficient space for heat diffusion. In an optional embodiment of this example, the hollow portion of the hollow structure 21 is rectangular. However, the shape of the hollow portion of the hollow structure 21 is not limited to this; as long as four-sided heat dissipation is achieved, this embodiment does not restrict the shape of the hollow structure 21. For example, the hollow portion of the hollow structure can be a pyramidal hollow. The material of the heat dissipation frame 2 typically has high thermal conductivity to ensure effective heat transfer from the chip 3 to the external environment. The heat dissipation frame 2 is a metal frame. In this embodiment, copper has good heat dissipation properties, and copper is currently the material used for frames in the industry; therefore, the heat dissipation frame 2 is a copper frame. In the prior art, the frame thickness typically ranges from 152 μm to 2000 μm, with 152 μm and 203 μm being commonly used thicknesses. Therefore, the wall thickness of the hollow structure 21 in this embodiment is also between 152 μm and 2000 μm. In one optional embodiment of this embodiment, the wall thickness of the hollow structure 21 is 152 μm. In another optional embodiment of this embodiment, the wall thickness of the hollow structure 21 is 203 μm.

[0047] In one optional embodiment of this example, refer to Figure 2 and Figure 3 The heat dissipation frame 2 is connected to the base island 1, and the bottom 23 of the heat dissipation frame 2 is part of the base island 1. The heat dissipation frame 2 and the base island 1 are bonded together with an adhesive material. This design not only ensures the accurate positioning of the heat dissipation frame 2 on the base island 1, but also further enhances the heat transfer efficiency from the chip 3 to the heat dissipation frame 2 through the conduction effect of the adhesive material. The selection of the adhesive material is crucial. It must not only have sufficient bonding strength to ensure the stability of the structure, but also have good thermal conductivity so that heat can be smoothly transferred from the chip 3 to the heat dissipation frame 2 and finally dissipated into the surrounding environment.

[0048] Reference Figure 4 and Figure 5 To ensure stable operation of chip 3 in complex and ever-changing external environments, unaffected by dust, moisture, and other potential interference factors, molding compound 7 encapsulates chip 3 and leads 6. This molding compound 7 effectively isolates external interference and possesses good mechanical strength and thermal stability, providing a robust and reliable protective layer for chip 3. Furthermore, the molding compound 7 fills the hollow structure 21 of the heat dissipation frame 2. The heat dissipation frame 2 provides a certain degree of constraint to the molding compound 7 filling the hollow structure 21, thus reducing deformation caused by the difference in thermal expansion coefficients between the heat dissipation frame 2 and the molding compound 7. This reduces the probability of delamination between the heat dissipation frame 2 and the molding compound 7, further improving the reliability of the chip packaging structure.

[0049] The chip packaging structure in this embodiment achieves four-sided heat dissipation through the setting of a heat dissipation frame, which greatly improves the device lifespan and reliability.

[0050] Example 2

[0051] This embodiment also provides a chip packaging structure, see reference. Figures 12 to 16 The chip package in this embodiment includes a base island 1, pins 5, and a heat dissipation frame 2. The similarities between this embodiment and Embodiment 1 will not be repeated, except that the heat dissipation frame 2 extends upwards from the base island 1. Specifically, refer to... Figures 12 to 14 The base island 1 includes a first side 11, a second side 12, a third side 13, and a fourth side 14 arranged opposite to each other. Pins 5 are located on the second side 12, the third side 13, and the fourth side 14 of the base island 1. A heat dissipation frame 2 is located on the first side 11 of the base island 1, extending upwards from the portions of the second side 12 and the fourth side 14 near the first side 11 and connecting at the top of the chip package structure. The heat dissipation frame 2 is also formed as a hollow structure. This design eliminates the need to connect the heat dissipation frame 2 and the base island 1, abandoning the traditional bonding method using adhesive materials and achieving integration of the heat dissipation frame 2 and the base island 1. This design not only simplifies the packaging process and reduces manufacturing costs, but more importantly, it eliminates the thermal resistance that adhesive materials may introduce, allowing heat to be dissipated more directly and efficiently through the heat dissipation frame 2. Furthermore, this integrated design helps improve the overall strength and stability of the chip package structure, which is significant for improving the reliability and extending the lifespan of the chip package structure.

[0052] In this embodiment, the heat dissipation frame 2 and the base island 1 of the chip packaging structure are integrated into one design, which further improves the heat dissipation performance of the chip packaging structure.

[0053] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A chip packaging structure, characterized in that, include: Base Island; The chip is fixed to the base island; Pins are located on the periphery of the base island and are electrically connected to the chip; A heat dissipation frame is located at at least one edge of the base island. The heat dissipation frame is formed as a hollow structure. The top of the heat dissipation frame is higher than the top of the chip, and the bottom of the heat dissipation frame is spaced apart from the chip. A molding compound that encapsulates the chip and fills the hollow structure of the heat dissipation frame.

2. The chip packaging structure according to claim 1, characterized in that, The heat dissipation frame is connected to the base island, and the bottom of the heat dissipation frame is part of the base island.

3. The chip packaging structure according to claim 1, characterized in that, The hollow portion of the hollow structure is rectangular.

4. The chip packaging structure according to claim 1, characterized in that, The wall thickness of the hollow structure is between 152 μm and 2000 μm.

5. The chip packaging structure according to claim 4, characterized in that, An adhesive layer is also provided between the chip and the base island. The adhesive material of the adhesive layer is solder wire, solder paste, conductive adhesive, or non-conductive adhesive.

6. The chip packaging structure according to claim 5, characterized in that, The thickness of the adhesive layer is between 10 μm and 50 μm.

7. The chip packaging structure according to claim 1, characterized in that, The heat dissipation frame is a metal frame.

8. The chip packaging structure according to claim 1, characterized in that, The minimum distance between the edge of the chip and the edge of the base island is between 100μm and 300μm.

9. The chip packaging structure according to claim 1, characterized in that, It also includes leads that are connected to the chip and the pins, and the molding compound covers the leads.

10. The chip packaging structure according to claim 9, characterized in that, The lead wire is a gold wire, copper wire, gold-palladium-copper wire, aluminum wire, or a clamp.

11. A chip packaging structure, characterized in that, include: The base island includes a first side, a second side, a third side, and a fourth side that are arranged opposite to each other; Pins are located on the second side, the third side, and the fourth side of the base island; A heat dissipation frame, located on the first side of the base island, extends upward from the portions of the second and fourth sides of the base island near the first side and connects at the top of the chip package structure, and the heat dissipation frame is formed as a hollow structure.

12. The chip packaging structure according to claim 11, characterized in that, The hollow portion of the hollow structure is rectangular.

13. The chip packaging structure according to claim 11, characterized in that, The heat dissipation frame is a metal frame.

14. The chip packaging structure according to claim 11, characterized in that, Also includes: A chip located on the base island, the top of the chip including solder joints connected to the pins via leads.

15. The chip packaging structure according to claim 14, characterized in that, Also includes: The molding compound encapsulates the chip and the leads and fills the hollow structure of the heat dissipation frame.

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