Chip packaging structure
By using system-in-package technology, the FPGA, ADC, and DAC chipsets are connected to the substrate, solving the problems of large size and high power consumption of traditional optical gyroscope signal processing boards, and realizing a miniaturized, low-power, and high-performance chip packaging structure.
Patent Information
- Application Number
- CN202422551002.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2034-10-22
AI Technical Summary
Traditional optical fiber gyroscope signal processing boards suffer from problems such as large size, high power consumption, poor consistency, and low reliability, which limit the application of optical fiber gyroscopes in practical business scenarios.
By employing system-in-package (SIP) technology, FPGA chips, ADC chipsets, and DAC chipsets are connected to the substrate via wire bonding, achieving internal packaging of multiple chips and forming a miniaturized chip packaging structure.
It achieves miniaturization of chip packaging, meets business requirements in terms of performance, functionality and reliability, and effectively reduces power consumption.
Smart Images
Figure CN223651404U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of chip packaging technology, and in particular relates to a chip packaging structure. Background Technology
[0002] Interferometric fiber optic gyroscopes are widely used in aerospace, defense, and industrial control. Traditional optical gyroscope signal processing boards are made by combining independent digital and analog chips, which has problems such as large size, high power consumption, poor consistency, and low reliability, which seriously restricts the application of fiber optic gyroscopes in actual business scenarios.
[0003] Therefore, in response to the application requirements of fiber optic gyroscopes, system-in-package (SiP) encapsulates the chip in a bare die manner and connects them inside the chip through wire bonding. Based on self-developed EDA software, chip pins are reallocated and IP soft cores are customized to achieve a small-size, low-power, and cost-effective chip packaging structure that meets the requirements of small size, low power consumption, and low cost for fiber optic gyroscopes, while also enabling mass production. Utility Model Content
[0004] The purpose of this invention is to provide a chip packaging structure that addresses the above-mentioned problems by connecting the FPGA chip, ADC chip group, and DAC chip group to the substrate through wire bonding, thereby achieving internal packaging of multiple chips. While meeting the miniaturization requirements, the performance, functionality, and reliability can meet business needs, and power consumption can be effectively reduced.
[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0006] A chip packaging structure, comprising:
[0007] substrate;
[0008] The first chip is disposed on the upper surface of the substrate, and a second chip group and a third chip group are respectively disposed on both sides;
[0009] The second chipset includes three vertically arranged second chips;
[0010] The third chipset includes three vertically arranged third chips;
[0011] And, a fourth chip and a fifth chip symmetrically arranged on the other two sides of the first chip;
[0012] A molding layer is located on the upper side of the substrate, covering the chip on the upper side of the substrate and the space on the upper side of the substrate not occupied by the chip.
[0013] The second chipset and the third chipset are symmetrically distributed on the left and right sides of the first chip, and there is a gap between them.
[0014] The chips in the second chipset are evenly arranged, and the chip spacing of the third chipset is the same as that of the second chipset.
[0015] The second chip corresponds one-to-one with the third chip according to the vertical arrangement order, and the second chip and the third chip are of different types.
[0016] The first chip is an FPGA chip;
[0017] The second chip and the third chip are analog-to-digital converter chips or digital-to-analog converter chips.
[0018] The substrate is a square substrate;
[0019] The first chip is placed in the middle of the upper surface of the substrate;
[0020] The second and third chipsets are placed on the left and right sides of the first chip, and are spaced apart from the edge of the substrate.
[0021] The chips on the upper side of the substrate are wire bonded to the substrate by bonding wires.
[0022] The molding layer covers the substrate and has the same shape and size as the substrate.
[0023] The substrate has a plurality of solder balls evenly distributed on its lower surface.
[0024] The dimensions of the packaging structure are less than or equal to 17mm*17mm.
[0025] The beneficial effects of this utility model are:
[0026] This invention connects the FPGA chip, ADC chipset, and DAC chipset to the substrate via wire bonding, achieving multi-chip internal packaging. While meeting miniaturization requirements, the performance, functionality, and reliability can meet business needs, and power consumption is effectively reduced.
[0027] To make the above and other objects, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the specific embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a top view of a chip packaging structure provided in an embodiment of this application.
[0030] Figure 2 A front view of a chip packaging structure provided in the embodiments of this application. Figure 1 .
[0031] Figure 3 This is a schematic diagram illustrating the working principle of a chip packaging structure provided in an embodiment of this application.
[0032] Figure 4 A front view of a chip packaging structure provided in the embodiments of this application. Figure 2 .
[0033] Figure 5 This is a bottom view of a chip packaging structure provided in an embodiment of this application.
[0034] Figure 6 This is a schematic diagram of the ADC signal acquisition provided in an embodiment of this application.
[0035] Figure 7 The waveform diagram of the DAC output signal provided in the embodiment of this application. Detailed Implementation
[0036] The foregoing and other technical contents, features, and effects of this utility model will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this utility model.
[0037] This invention connects the FPGA chip, ADC chipset, and DAC chipset to the substrate via wire bonding, achieving multi-chip internal packaging. While meeting miniaturization requirements, the performance, functionality, and reliability can meet business needs, and power consumption is effectively reduced.
[0038] Example:
[0039] Figure 1 The image shown is a top view of a chip packaging structure provided in an embodiment of this application.
[0040] like Figure 1As shown, a chip packaging structure includes:
[0041] Substrate 1, Substrate 1 is a square substrate;
[0042] The first chip 2 is placed in the middle of the upper surface of the substrate 1, and the second chip group 3 and the third chip group 4 are respectively provided on both sides.
[0043] The second chipset 3 and the third chipset 4 are placed on the left and right sides of the first chip 2, and there is a gap between them and the edge of the substrate 1.
[0044] The second chipset 3 includes three vertically arranged second chips, namely second chip 31, second chip 32 and second chip 33;
[0045] The third chipset 4 includes three vertically arranged third chips, namely the third chip 41, the second chip 42, and the second chip 43.
[0046] And, the fourth chip 5 and the fifth chip 6 are symmetrically arranged on the other two sides of the first chip 2;
[0047] Specifically, such as Figure 1 As shown, the second chipset 3 and the third chipset 4 are symmetrically distributed on the left and right sides of the first chip 2, and there is a gap between them.
[0048] The second chips 31, 32 and 33 of the second chipset 3 are evenly arranged, and the chip spacing of the third chipset 4 is the same as that of the second chipset 3.
[0049] The chips in the second chipset 3 correspond one-to-one with the chips in the third chipset 4 according to the vertical arrangement order. That is, the second chip 31 and the third chip 41 form a set of analog-to-digital conversion channels, corresponding to the three single channels XYZ of the gyroscope. The three single channels need to be isolated during wiring. If the second chip 31 is an ADC chip, then the third chip 41 is a DAC chip.
[0050] In a preferred embodiment of the present invention, the first chip in this embodiment is an FPGA chip, model EQ6HL45 of Zhongke Yihai Microelectronics, with a size of 9mm*9mm.
[0051] The second chip is an ADC chip, model SC9245, with dimensions of 1.974mm*2.034mm;
[0052] The third chip is a DAC chip, model MS9714, with dimensions of 1.63mm*1.83mm;
[0053] The substrate size is 17mm*17mm;
[0054] The fourth chip is the RS422 communication interface chip, model MS2583, with dimensions of 1.4mm*1.24mm;
[0055] The fifth chip is a FLASH chip, model E25064A, with dimensions of 2.651mm*1.868mm.
[0056] Figure 2 The image shown is a front view of a chip packaging structure provided in an embodiment of this application. Figure 1 .
[0057] like Figure 2 As shown, the chip packaging structure also includes a molding layer 7;
[0058] The molding layer 7 is located on the upper side of the substrate 1, covering the chip on the upper side of the substrate 1 and the space on the upper side of the substrate 1 not occupied by the chip, and has the same shape and size as the substrate 1.
[0059] The chip on the upper side of substrate 1 is wire bonded to the substrate by bonding wires (usually gold, copper or aluminum wires) to connect the electrodes on the chip to the pads on the substrate.
[0060] First, a small metal ball is formed at the first solder joint, typically by melting the end of a metal wire using an electric spark or electron beam. Then, this metal ball is pressed onto the contact point on the chip and held in place by ultrasonic energy and / or thermal energy. Next, the machine pulls out a section of metal wire and moves it to the location of the second solder joint, forming a predetermined arc shape. Finally, ultrasonic energy and / or thermal energy are applied again at the second solder joint (usually a pad on the package substrate) to ensure good mechanical and electrical contact.
[0061] like Figure 2 As shown, multiple solder balls 8 are evenly distributed on the lower surface of the substrate 1, which can increase the number of I / O pins, simplify the PCB layout design, further reduce the length of external pins, and reduce electromagnetic radiation and reception that may be generated during signal transmission.
[0062] The bottom of the package structure has a large area of solder joints (solder balls), which can better disperse external impacts and improve overall stability and durability.
[0063] Figure 3 The diagram shown is a schematic diagram illustrating the working principle of a chip packaging structure provided in an embodiment of this application.
[0064] like Figure 3As shown, three 14-bit 125MSPS ADCs are responsible for signal acquisition, the FPGA is responsible for data processing, three 14-bit 125MSPS DACs provide modulation signals, a 64Mbit memory is used to store data, and an internal RS422 is used for external data interaction.
[0065] Among them, the DAC chip and ADC chip mainly complete the generation of the conversion signal, the FPGA chip demodulates the feedback phase error signal, and performs digital integration of the demodulated phase error, generates a digital phase ladder wave from the gyroscope output rate value, and superimposes the bias modulation signal to provide it to the DAC output to realize closed-loop feedback.
[0066] The FPGA chip in this application adopts a 40nm CMOS process, 42,500 4-input LUTs, 392 4.5Kbit on-chip memory cells, and 56 high-speed 18bitx18bit multipliers, which can realize high-speed clock management.
[0067] Figure 4 The image shown is a bottom view of a chip packaging structure provided in an embodiment of this application.
[0068] like Figure 4 As shown, the package structure is 17mm*17mm in size and the solder ball (pin) pitch is 0.8mm. Compared with the traditional fiber optic gyroscope's size of 1000mm*1000mm, it can be reduced by 90%. This package structure represents a significant advancement in the miniaturization and micro-miniaturization of fiber optic gyroscopes.
[0069] Figure 6 The image shows a 1M waveform acquired by an ADC at 50MSPS. The sampling is stable and the signal-to-noise ratio reaches 70dB.
[0070] Figure 7 The image shows the DAC output signal captured by the oscilloscope. The refresh rate is 50MHz, the resolution is 14bit, the transmission delay is less than 1ns, and the signal-to-noise ratio is 69dB.
[0071] Compared to traditional PCB-level designs, this package structure shortens the connection between multiple bare chips and the signal transmission distance, greatly reducing EMC between chips.
[0072] This invention connects the FPGA chip, ADC chipset, and DAC chipset to the substrate via wire bonding, achieving multi-chip internal packaging. While meeting miniaturization requirements, the performance, functionality, and reliability can meet business needs, and power consumption is effectively reduced.
[0073] Although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
[0074] The detailed descriptions listed above are merely specific descriptions of feasible implementations of this utility model, and are not intended to limit the scope of protection of this utility model. All equivalent implementations or modifications made without departing from the spirit of this utility model should be included within the scope of protection of this utility model.
Claims
1. A chip packaging structure, characterized in that, include: substrate; The first chip is disposed on the upper surface of the substrate, and a second chip group and a third chip group are respectively disposed on both sides; The second chipset includes three vertically arranged second chips; The third chipset includes three vertically arranged third chips; And, a fourth chip and a fifth chip symmetrically arranged on the other two sides of the first chip; A molding layer is located on the upper side of the substrate, covering the chip on the upper side of the substrate and the space on the upper side of the substrate not occupied by the chip.
2. The chip packaging structure according to claim 1, characterized in that, The second chipset and the third chipset are symmetrically distributed on the left and right sides of the first chip, and there is a gap between them.
3. The chip packaging structure according to claim 2, characterized in that, The chips in the second chipset are evenly arranged, and the chip spacing of the third chipset is the same as that of the second chipset.
4. A chip packaging structure according to claim 2, characterized in that, The second chip corresponds one-to-one with the third chip according to the vertical arrangement order, and the second chip and the third chip are of different types.
5. A chip packaging structure according to claim 4, characterized in that, The first chip is an FPGA chip; The second chip and the third chip are analog-to-digital converter chips or digital-to-analog converter chips.
6. A chip packaging structure according to claim 1, characterized in that, The substrate is a square substrate; The first chip is placed in the middle of the upper surface of the substrate; The second and third chipsets are placed on the left and right sides of the first chip, and are spaced apart from the edge of the substrate.
7. A chip packaging structure according to claim 1, characterized in that, The chips on the upper side of the substrate are wire bonded to the substrate by bonding wires.
8. A chip packaging structure according to claim 1, characterized in that, The molding layer covers the substrate and has the same shape and size as the substrate.
9. A chip packaging structure according to claim 1, characterized in that, The substrate has a plurality of solder balls evenly distributed on its lower surface.
10. A chip packaging structure according to claim 1, characterized in that, The dimensions of the packaging structure are less than or equal to 17mm*17mm.