Over-current turn-off circuit and motor controller

Abstract

The utility model provides an overcurrent turn-off circuit and a motor controller. The overcurrent turn-off circuit comprises a control circuit, a gate drive circuit, an IGBT circuit, a voltage detection circuit, a voltage comparison circuit, a time delay circuit and a desaturation trigger circuit. The output end of the gate drive circuit is connected with the grid electrode of the IGBT circuit, and the second input end is connected with the third end of the desaturation trigger circuit; the drain electrode of the IGBT circuit is connected with the positive electrode of the high-voltage bus and the first end of the desaturation trigger circuit, and the source electrode is connected with the negative electrode of the high-voltage bus and the input end of the voltage detection circuit; the output end of the voltage detection circuit is connected with the input end of the voltage comparison circuit; the output end of the voltage comparison circuit is connected with the input end of the time delay circuit and the second end of the desaturation trigger circuit. According to the over-current turn-off circuit provided by the invention, the turn-off time can be prolonged by triggering the desaturation turn-off of the gate drive circuit through the desaturation trigger circuit when the IGBT circuit is over-current, and the over-current protection effect on the IGBT circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of motor control, and particularly relates to an overcurrent shutdown circuit and a motor controller. BACKGROUND

[0002] The motor controller occupies a very key position in the three-electricity system of a new energy vehicle, and the failure of an insulated gate bipolar transistor (IGBT) circuit used for chopper may cause power interruption during driving, so it is very important to protect the IGBT circuit.

[0003] When the IGBT circuit works, if the current flowing through the IGBT circuit exceeds the rated current, the trigger signal of the IGBT circuit needs to be shut down to switch the IGBT circuit from the on state to the off state, so as to protect the IGBT circuit. Figure 1 Figure 1 FIG. 1 is a structural schematic diagram of an overcurrent shutdown circuit in the prior art. As shown in FIG. 1, when the existing overcurrent shutdown circuit detects an overcurrent, the voltage detection circuit detects the voltage rise caused by the overcurrent to make the voltage comparison circuit flip and output a low level, the control circuit is made invalid in the low level to block the pulse width modulation (PWM) signal from being input into the gate drive circuit, and then the gate drive circuit quickly shuts down the trigger signal of the IGBT circuit to realize the overcurrent shutdown of the IGBT circuit. However, when the IGBT circuit is quickly shut down by blocking the PWM signal, the rapidly changing current may cause a large peak voltage in the inductance of the circuit, and if the peak voltage exceeds the bearing range of the IGBT circuit, the IGBT circuit may be damaged. Therefore, the existing overcurrent shutdown circuit has poor protection effect on the IGBT circuit. Figure 1 In view of this, the present application aims to provide an overcurrent shutdown circuit and a motor controller, which can prolong the shutdown time by triggering the desaturation shutdown of the gate drive circuit through the desaturation trigger circuit when the IGBT circuit overflows, and improve the overcurrent protection effect on the IGBT circuit.

[0004]

[0005] ​​​In a first aspect, the embodiments of the present application provide an over-current shutdown circuit, comprising: a control circuit, a gate drive circuit, an IGBT circuit, a voltage detection circuit, a voltage comparison circuit, a delay circuit and a desaturation trigger circuit; wherein a first input terminal of the control circuit is connected with a pulse width modulation signal, an output terminal of the control circuit is connected with a first input terminal of the gate drive circuit; an output terminal of the gate drive circuit is connected with a gate of the IGBT circuit; a drain of the IGBT circuit is connected with a positive pole of a high-voltage bus and a first terminal of the desaturation trigger circuit respectively, a source of the IGBT circuit is connected with a negative pole of the high-voltage bus and an input terminal of the voltage detection circuit respectively; an output terminal of the voltage detection circuit is connected with an input terminal of the voltage comparison circuit; an output terminal of the voltage comparison circuit is connected with an input terminal of the delay circuit and a second terminal of the desaturation trigger circuit respectively; an output terminal of the delay circuit is connected with a second input terminal of the control circuit; and a third terminal of the desaturation trigger circuit is connected with a second input terminal of the gate drive circuit.

[0006] In a possible implementation, the desaturation trigger circuit comprises a first NMOS transistor, a first resistor, a first voltage source and a photoelectric coupler; wherein a gate of the first NMOS transistor is connected with the second terminal of the desaturation trigger circuit, a drain of the first NMOS transistor is connected with a first terminal of the first resistor, a second terminal of the first resistor is connected with the first voltage source, and a source of the first NMOS transistor is connected with a first input terminal of the photoelectric coupler; a second input terminal of the photoelectric coupler is grounded, a first output terminal of the photoelectric coupler is connected with the first terminal of the desaturation trigger circuit, and a second output terminal of the photoelectric coupler is connected with the third terminal of the desaturation trigger circuit.

[0007] Optionally, the photoelectric coupler is a photoelectric coupler of model PC817.

[0008] In a possible implementation, the desaturation trigger circuit comprises a capacitor isolator, a second voltage source, a third voltage source, a first capacitor, a second resistor and a second NMOS transistor; wherein an input terminal of the capacitor isolator is connected with the second terminal of the desaturation trigger circuit, an input power terminal of the capacitor isolator is connected with the second voltage source, an output terminal of the capacitor isolator is connected with a first terminal of the first capacitor and a first terminal of the second resistor respectively, and an output power terminal of the capacitor isolator is connected with the third voltage source; a second terminal of the first capacitor is grounded; a second terminal of the second resistor is connected with a gate of the second NMOS transistor; a drain of the second NMOS transistor is connected with the third terminal of the desaturation trigger circuit, and a source of the second NMOS transistor is connected with the first terminal of the desaturation trigger circuit.

[0009] Optionally, the capacitor isolator is a capacitor isolator with model number NSI822X-Q1.

[0010] Furthermore, the delay circuit includes a third resistor and a second capacitor; wherein, the first end of the third resistor is connected to the input terminal of the delay circuit, and the second end of the third resistor is connected to the first end of the second capacitor and the output terminal of the delay circuit respectively; the second end of the second capacitor is grounded.

[0011] Furthermore, the gate driver circuit includes a gate driver chip, a third capacitor, and a fourth resistor; wherein, the gate driver chip is an NCV57101DWR2G gate driver chip; the IN pin of the gate driver chip is connected to the first input terminal of the gate driver circuit, the DESAT pin of the gate driver chip is connected to the first terminal of the third capacitor and the second input terminal of the gate driver circuit respectively, the G pin of the gate driver chip is connected to the first terminal of the fourth resistor; the GND pin of the gate driver chip is grounded; the second terminal of the third capacitor is grounded; and the second terminal of the fourth resistor is connected to the output terminal of the gate driver circuit.

[0012] Furthermore, the overcurrent shutdown circuit also includes a fifth resistor, a first diode, and a fourth capacitor; wherein, the first end of the fifth resistor is connected to the first end of the desaturation trigger circuit, and the second end of the fifth resistor is connected to the input end of the first diode; the output end of the first diode is connected to the drain of the IGBT circuit; the first end of the fourth capacitor is connected to the drain of the IGBT circuit, and the second end of the fourth capacitor is connected to the source of the IGBT circuit.

[0013] Optionally, the voltage detection circuit is a Hall sensor of model HC5F900-S.

[0014] Secondly, embodiments of this application also provide a motor controller, including the overcurrent shutdown circuit described above.

[0015] This application provides an overcurrent shutdown circuit and a motor controller. The overcurrent shutdown circuit includes a control circuit, a gate drive circuit, an IGBT circuit, a voltage detection circuit, a voltage comparator circuit, a delay circuit, and a desaturation trigger circuit. The first input terminal of the control circuit is connected to a pulse width modulation signal, and the output terminal of the control circuit is connected to the first input terminal of the gate drive circuit. The output terminal of the gate drive circuit is connected to the gate of the IGBT circuit. The drain of the IGBT circuit is connected to the positive terminal of the high-voltage bus and the first terminal of the desaturation trigger circuit, respectively. The source of the IGBT circuit is connected to the negative terminal of the high-voltage bus and the input terminal of the voltage detection circuit, respectively. The output terminal of the voltage detection circuit is connected to the input terminal of the voltage comparator circuit. The output terminal of the voltage comparator circuit is connected to the input terminal of the delay circuit and the second terminal of the desaturation trigger circuit, respectively. The output terminal of the delay circuit is connected to the second input terminal of the control circuit. The third terminal of the desaturation trigger circuit is connected to the second input terminal of the gate drive circuit. The overcurrent shutdown circuit provided in this application can extend the shutdown time by triggering the desaturation shutdown of the gate drive circuit through the desaturation trigger circuit when the IGBT circuit experiences overcurrent, thereby improving the overcurrent protection effect of the IGBT circuit.

[0016] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the overcurrent shutdown circuit in the prior art is shown;

[0019] Figure 2 This illustration shows one of the structural schematic diagrams of an overcurrent shutdown circuit provided in an embodiment of this application;

[0020] Figure 3 This is a second schematic diagram of an overcurrent shutdown circuit provided in an embodiment of this application;

[0021] Figure 4 The third schematic diagram shows the structure of an overcurrent shutdown circuit provided in an embodiment of this application.

[0022] Figure reference numerals: 200 - Overcurrent shutdown circuit; 210 - Control circuit; 220 - Gate drive circuit; 230 - IGBT circuit; 240 - Voltage detection circuit; 250 - Voltage comparator circuit; 260 - Delay circuit; 270 - Desaturation trigger circuit; Q1 - First NMOS transistor; R1 - First resistor; U1 - First voltage source; OPT - Optocoupler; ISO - Capacitor isolator; U2 - Second voltage source; U3 - Third voltage source; C1 - First capacitor; R2 - Second resistor; Q2 - Second NMOS transistor; R3 - Third resistor; C2 - Second capacitor; GD - Gate drive chip; C3 - Third capacitor; R4 - Fourth resistor; R5 - Fifth resistor; D1 - First diode; C4 - Fourth capacitor. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] In the description of the embodiments of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use. They are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0027] To enable those skilled in the art to utilize the content of this application, and in conjunction with the specific application scenario of "overcurrent turn-off of IGBT circuits," the following implementation methods are provided. For those skilled in the art, the general principles defined herein can be applied to other embodiments and application scenarios without departing from the spirit and scope of this application. Although this application primarily describes "overcurrent turn-off of IGBT circuits," it should be understood that this is merely an exemplary embodiment.

[0028] like Figure 1 As shown, existing overcurrent shutdown circuits, when rapidly turning off the IGBT circuit by blocking the PWM signal, experience significant voltage spikes due to rapidly changing current. If these spikes exceed the IGBT circuit's tolerance, they can damage it. Therefore, existing overcurrent shutdown circuits offer poor protection for the IGBT circuit.

[0029] To overcome the above-mentioned defects, this application provides an overcurrent shutdown circuit and a motor controller, which can extend the shutdown time by triggering the gate drive circuit to desaturate and turn off when the IGBT circuit is overcurrent, thereby improving the overcurrent protection effect of the IGBT circuit.

[0030] Please see Figure 2 , Figure 2 This is one of the structural schematic diagrams of an overcurrent shutdown circuit provided in an embodiment of this application. For example... Figure 2 As shown, the overcurrent shutdown circuit 200 provided in this application embodiment includes: a control circuit 210, a gate drive circuit 220, an IGBT circuit 230, a voltage detection circuit 240, a voltage comparison circuit 250, a delay circuit 260, and a desaturation trigger circuit 270.

[0031] In this circuit, the first input terminal of the control circuit 210 is connected to the pulse width modulation signal, and the output terminal of the control circuit 210 is connected to the first input terminal of the gate drive circuit 220. The output terminal of the gate drive circuit 220 is connected to the gate of the IGBT circuit 230. The drain of the IGBT circuit 230 is connected to the positive terminal of the high voltage bus and the first terminal of the desaturation trigger circuit 270, respectively. The source of the IGBT circuit 230 is connected to the negative terminal of the high voltage bus and the input terminal of the voltage detection circuit 240, respectively. The output terminal of the voltage detection circuit 240 is connected to the input terminal of the voltage comparator circuit 250. The output terminal of the voltage comparator circuit 250 is connected to the input terminal of the delay circuit 260 and the second terminal of the desaturation trigger circuit 270, respectively. The output terminal of the delay circuit 260 is connected to the second input terminal of the control circuit 210. The third terminal of the desaturation trigger circuit 270 is connected to the second input terminal of the gate drive circuit 220.

[0032] In this embodiment, the control circuit 210 provides a pulse width modulation signal, i.e., a PWM wave, to the first input terminal of the gate drive circuit 220 when the circuit is operating normally. It also stops providing the PWM wave to the gate drive circuit 220 upon receiving a low-level invalid signal from the delay circuit 260, thereby causing the gate drive circuit 220 to turn off the trigger signal of the IGBT circuit 230. Specifically, the control circuit 210 can be a data cache chip of model 74AHC541PW-Q100.

[0033] In this embodiment, the gate drive circuit 220 is used to output a corresponding trigger signal to the gate of the IGBT circuit 230 at its output terminal according to the PWM wave sent by the control circuit 210 received at the first input terminal, so as to control the conduction of the IGBT circuit 230; it is also used to turn off the trigger signal output to the gate of the IGBT circuit 230 after a first duration when the PWM wave is stopped being received; and it is also used to turn off the trigger signal output to the gate of the IGBT circuit 230 after a second duration when a desaturation trigger signal is detected at the second input terminal. The desaturation trigger signal is the voltage at the collector-emitter (CE) terminal of the IGBT circuit that rises rapidly when a short-circuit fault occurs in the IGBT circuit, causing the IGBT circuit to exit the saturation region and enter the linear operating region. The gate drive circuit 220 determines the trigger signal of the IGBT circuit experiencing an oversaturation short-circuit fault by monitoring the voltage rise at the second input terminal or the disappearance of the current flowing into the second input terminal. When an oversaturation short-circuit fault occurs in the IGBT circuit, the gate drive circuit 220 turns off the trigger signal output to the gate of the IGBT circuit 230 after a second duration. Here, the second duration is several times longer than the first duration of PWM turn-off, which can effectively reduce the rate of change of current during turn-off, thereby reducing the peak voltage and protecting the IGBT circuit from damage caused by excessively high peak voltage. However, when an overcurrent fault occurs in the IGBT circuit, the circuit is far from meeting the trigger condition for desaturation turn-off and cannot execute the turn-off for the second duration. Therefore, this embodiment considers artificially introducing a desaturation trigger circuit 270 when an overcurrent fault is detected in the IGBT circuit 230, disconnecting the second input terminal of the gate drive circuit 220 from the source terminal of the IGBT circuit 230, and triggering the desaturation turn-off of the gate drive circuit by causing the current flowing into the second input terminal to disappear, thereby realizing the turn-off of the IGBT circuit 230 for the second duration during an overcurrent fault.

[0034] In this embodiment, the IGBT circuit 230 is a power device used for chopping in the motor controller. Specifically, the IGBT circuit 230 can be an IGBT of model FS820.

[0035] In this embodiment, the voltage detection circuit 240 is used to detect the phase current flowing through the IGBT circuit 230 and convert the phase current into a voltage signal, which is then sent to the voltage comparison circuit 250. Optionally, the voltage detection circuit 240 is a Hall sensor of model HC5F900-S.

[0036] In this embodiment, the voltage comparator circuit 250 compares the voltage signal sent by the voltage detection circuit 240 with a preset voltage threshold. When the voltage signal is greater than the voltage threshold, the output of the voltage comparator circuit 250 flips from high to low and is sent to the input of the delay circuit 260 and the second terminal of the desaturation trigger circuit 270, respectively. Specifically, the voltage comparator circuit 250 can be a voltage comparator of model LM339LVQPWRQ1.

[0037] In this embodiment, the delay circuit 260 is used to delay the low-level signal output by the voltage comparison circuit 250 to the second input terminal of the control circuit 210, so that the time when the low-level signal arrives at the control circuit 210 is later than the time when the low-level signal arrives at the desaturation trigger circuit 270, so that the gate drive circuit 220 first triggers the desaturation turn-off for the second duration and then triggers the PWM turn-off for the first duration, thereby achieving a relatively smooth combined turn-off of the IGBT circuit 230.

[0038] In this embodiment, the desaturation trigger circuit 270 is used to receive a low-level signal sent by the voltage comparator circuit 250, cut off the second input terminal of the gate drive circuit 220 and the source terminal of the IGBT circuit 230, and cause the current flowing into the second input terminal to disappear to trigger the desaturation turn-off of the gate drive circuit, thereby realizing the turn-off of the IGBT circuit 230 for a second duration in the event of an overcurrent fault.

[0039] In one possible implementation, please refer to Figure 3 , Figure 3 This is a second schematic diagram of an overcurrent shutdown circuit provided in an embodiment of this application. Figure 3 As shown, the desaturation trigger circuit 270 includes a first NMOS transistor Q1, a first resistor R1, a first voltage source U1, and an optocoupler OPT.

[0040] In this circuit, the gate of the first NMOS transistor Q1 is connected to the second terminal of the desaturation trigger circuit 270, the drain of the first NMOS transistor Q1 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the first voltage source U1, and the source of the first NMOS transistor Q1 is connected to the first input terminal of the optocoupler OPT. The second input terminal of the optocoupler OPT is grounded, the first output terminal of the optocoupler OPT is connected to the first terminal of the desaturation trigger circuit 270, and the second output terminal of the optocoupler OPT is connected to the third terminal of the desaturation trigger circuit 270.

[0041] In this embodiment, when the circuit is working normally, the voltage comparison circuit 250 outputs a high-level signal to the gate of the first NMOS transistor Q1, so that the source and drain of the first NMOS transistor Q1 are turned on. The first voltage source U1 supplies power to the first input terminal of the optocoupler OPT through the first resistor R1, so that the light-emitting element at the input terminal of the optocoupler OPT works, thereby turning on the photosensitive element between the first output terminal and the second output terminal of the optocoupler OPT. The second input terminal of the gate drive circuit 220 is connected to the source of the IGBT circuit 230.

[0042] When an overcurrent fault occurs in the circuit, the voltage comparator circuit 250 outputs a low-level signal to the gate of the first NMOS transistor Q1, which cuts off the source and drain of the first NMOS transistor Q1. The voltage source U1 stops supplying power to the first input terminal of the optocoupler OPT, thereby turning off the photosensitive element between the first and second output terminals of the optocoupler OPT. The second input terminal of the gate drive circuit 220 is disconnected from the source of the IGBT circuit 230, triggering the desaturation turn-off of the gate drive circuit 220.

[0043] The optocoupler (OPT) is also used to ensure isolation between the high voltage on the circuit line and the low voltage at the logic terminal, preventing electric shock and circuit malfunction. Specifically, the first NMOS transistor Q1 can be a 2N7002 NMOS transistor; the first voltage source U1 can be a 5V voltage source; and the first resistor R1 can be a 0603 type resistor with a resistance of 1KR.

[0044] Optionally, the optocoupler OPT is an optocoupler of model PC817.

[0045] In one possible implementation, please refer to Figure 4 , Figure 4 This is a third schematic diagram of an overcurrent shutdown circuit provided in an embodiment of this application. Figure 4 As shown, the desaturation trigger circuit 270 includes a capacitor isolator ISO, a second voltage source U2, a third voltage source U3, a first capacitor C1, a second resistor R2, and a second NMOS transistor Q2.

[0046] The input terminal of the capacitor isolator ISO is connected to the second terminal of the desaturation trigger circuit 270. The input power supply terminal of the capacitor isolator ISO is connected to the second voltage source U2. The output terminal of the capacitor isolator ISO is connected to the first terminal of the first capacitor C1 and the first terminal of the second resistor R2. The output power supply terminal of the capacitor isolator ISO is connected to the third voltage source U3. The second terminal of the first capacitor C1 is grounded. The second terminal of the second resistor R2 is connected to the gate of the second NMOS transistor Q2. The drain of the second NMOS transistor Q2 is connected to the third terminal of the desaturation trigger circuit 270, and the source of the second NMOS transistor Q2 is connected to the first terminal of the desaturation trigger circuit 270.

[0047] In this embodiment, the capacitor isolator ISO is used to isolate the high voltage on the circuit line from the low voltage at the logic terminal, and to ensure accurate data transmission across the isolation circuit. Specifically, the second voltage source is a 5V voltage source, and the third voltage source is a 15V voltage source. The first capacitor C1 is used to protect the capacitor isolator ISO. When the circuit is working normally, the voltage comparator circuit 250 outputs a high-level signal to the input terminal of the capacitor isolator ISO, and after being isolated and amplified by the capacitor isolator ISO, it is output to the gate of the second NMOS transistor Q2 through the second resistor R2, making the source and drain of the second NMOS transistor conduct. The second input terminal of the gate drive circuit 220 is connected to the source of the IGBT circuit 230.

[0048] When an overcurrent fault occurs in the circuit, the voltage comparator circuit 250 outputs a low-level signal to the input terminal of the capacitor isolator ISO. After being isolated and transmitted through the capacitor isolator ISO, the signal is output to the gate of the second NMOS transistor Q2 through the second resistor R2, which cuts off the source and drain of the second NMOS transistor Q2. The second input terminal of the gate drive circuit 220 is disconnected from the source of the IGBT circuit 230, triggering the desaturation turn-off of the gate drive circuit 220.

[0049] Optionally, the capacitor isolator ISO is a capacitor isolator with model number NSI822X-Q1.

[0050] Furthermore, such as Figure 3 As shown, the delay circuit 260 includes a third resistor R3 and a second capacitor C2. The first end of the third resistor R3 is connected to the input terminal of the delay circuit 260, and the second end of the third resistor R3 is connected to both the first end of the second capacitor C2 and the output terminal of the delay circuit 260; the second end of the second capacitor C2 is grounded.

[0051] In this embodiment, when the circuit is operating normally, the high-level signal output by the voltage comparator circuit 250 charges the second capacitor C2 through the third resistor R3. When an overcurrent fault occurs, the voltage comparator circuit 250 outputs a low-level signal to the first terminal of the third resistor R3. At this time, the first terminal of the third resistor R3 can maintain a high-level signal for a period of time due to the discharge of the second capacitor C2. Only after the second capacitor C2 has discharged to a certain extent will the second terminal of the third resistor R3 switch from high level to low level and be output to the control circuit 210. The delay time of the circuit can be determined according to the resistance value of the third resistor R3 and the capacitance value of the second capacitor C2. Specifically, the third resistor R3 can be a 0603 type resistor with a resistance value of 2KR, and the second capacitor C2 can be a capacitor with parameters of 1nF and 50V.

[0052] Furthermore, such as Figure 3As shown, the gate drive circuit 220 includes a gate drive chip GD, a third capacitor C3, and a fourth resistor R4.

[0053] The gate driver chip GD can be an NCV57101DWR2G model. The IN pin of the gate driver chip GD is connected to the first input terminal of the gate driver circuit 220. The DESAT pin of the gate driver chip GD is connected to the first terminal of the third capacitor C3 and the second input terminal of the gate driver circuit 220, respectively. The G pin of the gate driver chip GD is connected to the first terminal of the fourth resistor R4. The GND pin of the gate driver chip GD is grounded. The second terminal of the third capacitor C3 is grounded. The second terminal of the fourth resistor R4 is connected to the output terminal of the gate driver circuit 220.

[0054] In this embodiment, the third capacitor C3 is used to filter out noise in the circuit and protect the DESAT pin of the gate driver chip GD. Specifically, the third capacitor C3 can be a 100pF 50V capacitor.

[0055] In this embodiment, the fourth resistor R4 is used to adjust the first duration and the second duration. Specifically, the fourth resistor R4 can be a 0603 type resistor with a resistance of 3R.

[0056] Furthermore, such as Figure 3 As shown, the overcurrent shutdown circuit 200 also includes a fifth resistor R5, a first diode D1, and a fourth capacitor C4.

[0057] Specifically, the first end of the fifth resistor R5 is connected to the first end of the desaturation trigger circuit 270, and the second end of the fifth resistor R5 is connected to the input end of the first diode D1; the output end of the first diode D1 is connected to the drain of the IGBT circuit 230; the first end of the fourth capacitor C4 is connected to the drain of the IGBT circuit 230; and the second end of the fourth capacitor C4 is connected to the source of the IGBT circuit 230.

[0058] In this embodiment, the fifth resistor R5 and the first diode D1 are used to protect the second input terminal of the gate drive circuit 220. Specifically, the fifth resistor can be a 0603 type resistor with a resistance of 1KR, and the first diode D1 can be a diode of type NRVUS160VT3G.

[0059] In this embodiment, the fourth capacitor C4 is a support capacitor for the IGBT circuit 230, used to ensure stable operation of the electronic control circuit and filter out stray inductance on the voltage bus.

[0060] The overcurrent shutdown circuit provided in this application includes a control circuit, a gate drive circuit, an IGBT circuit, a voltage detection circuit, a voltage comparator circuit, a delay circuit, and a desaturation trigger circuit. The first input terminal of the control circuit is connected to a pulse width modulation signal, and the output terminal of the control circuit is connected to the first input terminal of the gate drive circuit. The output terminal of the gate drive circuit is connected to the gate of the IGBT circuit. The drain of the IGBT circuit is connected to the positive terminal of the high-voltage bus and the first terminal of the desaturation trigger circuit, respectively. The source of the IGBT circuit is connected to the negative terminal of the high-voltage bus and the input terminal of the voltage detection circuit, respectively. The output terminal of the voltage detection circuit is connected to the input terminal of the voltage comparator circuit. The output terminal of the voltage comparator circuit is connected to the input terminal of the delay circuit and the second terminal of the desaturation trigger circuit, respectively. The output terminal of the delay circuit is connected to the second input terminal of the control circuit. The third terminal of the desaturation trigger circuit is connected to the second input terminal of the gate drive circuit. The overcurrent shutdown circuit provided in this application can extend the shutdown time by triggering the desaturation shutdown of the gate drive circuit through the desaturation trigger circuit when the IGBT circuit experiences overcurrent, thereby improving the overcurrent protection effect on the IGBT circuit.

[0061] Based on the same technical concept, this application also provides a motor controller, which includes the overcurrent shutdown circuit described above, and will not be repeated here.

[0062] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An overcurrent shutdown circuit, characterized in that, The overcurrent shutdown circuit includes: a control circuit, a gate drive circuit, an IGBT circuit, a voltage detection circuit, a voltage comparison circuit, a delay circuit, and a desaturation trigger circuit. The first input terminal of the control circuit is connected to the pulse width modulation signal, and the output terminal of the control circuit is connected to the first input terminal of the gate drive circuit. The output terminal of the gate drive circuit is connected to the gate of the IGBT circuit; The drain of the IGBT circuit is connected to the positive terminal of the high-voltage bus and the first terminal of the desaturation trigger circuit, respectively; the source of the IGBT circuit is connected to the negative terminal of the high-voltage bus and the input terminal of the voltage detection circuit, respectively. The output terminal of the voltage detection circuit is connected to the input terminal of the voltage comparison circuit; The output terminal of the voltage comparator circuit is connected to the input terminal of the delay circuit and the second terminal of the desaturation trigger circuit, respectively. The output terminal of the delay circuit is connected to the second input terminal of the control circuit; The third terminal of the desaturation trigger circuit is connected to the second input terminal of the gate drive circuit.

2. The overcurrent shutdown circuit according to claim 1, characterized in that, The desaturation trigger circuit includes a first NMOS transistor, a first resistor, a first voltage source, and an optocoupler; Wherein, the gate of the first NMOS transistor is connected to the second terminal of the desaturation trigger circuit, the drain of the first NMOS transistor is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the first voltage source, and the source of the first NMOS transistor is connected to the first input terminal of the optocoupler. The second input terminal of the optocoupler is grounded, the first output terminal of the optocoupler is connected to the first terminal of the desaturation trigger circuit, and the second output terminal of the optocoupler is connected to the third terminal of the desaturation trigger circuit.

3. The overcurrent shutdown circuit according to claim 2, characterized in that, The optocoupler is a PC817 type optocoupler.

4. The overcurrent shutdown circuit according to claim 1, characterized in that, The desaturation trigger circuit includes a capacitor isolator, a second voltage source, a third voltage source, a first capacitor, a second resistor, and a second NMOS transistor. Wherein, the input terminal of the capacitor isolator is connected to the second terminal of the desaturation trigger circuit, the input power terminal of the capacitor isolator is connected to the second voltage source, the output terminal of the capacitor isolator is connected to the first terminal of the first capacitor and the first terminal of the second resistor respectively, and the output power terminal of the capacitor isolator is connected to the third voltage source; The second terminal of the first capacitor is grounded; The second end of the second resistor is connected to the gate of the second NMOS transistor; The drain of the second NMOS transistor is connected to the third terminal of the desaturation trigger circuit, and the source of the second NMOS transistor is connected to the first terminal of the desaturation trigger circuit.

5. The overcurrent shutdown circuit according to claim 4, characterized in that, The capacitor isolator is a capacitor isolator with model number NSI822X-Q1.

6. The overcurrent shutdown circuit according to claim 1, characterized in that, The delay circuit includes a third resistor and a second capacitor; Wherein, the first end of the third resistor is connected to the input end of the delay circuit, and the second end of the third resistor is connected to the first end of the second capacitor and the output end of the delay circuit respectively; The second terminal of the second capacitor is grounded.

7. The overcurrent shutdown circuit according to claim 1, characterized in that, The gate drive circuit includes a gate drive chip, a third capacitor, and a fourth resistor; The gate driver chip is an NCV57101DWR2G gate driver chip; the IN pin of the gate driver chip is connected to the first input terminal of the gate driver circuit; the DESAT pin of the gate driver chip is connected to the first terminal of the third capacitor and the second input terminal of the gate driver circuit; the G pin of the gate driver chip is connected to the first terminal of the fourth resistor; and the GND pin of the gate driver chip is grounded. The second terminal of the third capacitor is grounded; The second end of the fourth resistor is connected to the output of the gate drive circuit.

8. The overcurrent shutdown circuit according to claim 1, characterized in that, The overcurrent shutdown circuit also includes a fifth resistor, a first diode, and a fourth capacitor; Wherein, the first end of the fifth resistor is connected to the first end of the desaturation trigger circuit, and the second end of the fifth resistor is connected to the input end of the first diode; The output terminal of the first diode is connected to the drain of the IGBT circuit; The first terminal of the fourth capacitor is connected to the drain of the IGBT circuit, and the second terminal of the fourth capacitor is connected to the source of the IGBT circuit.

9. The overcurrent shutdown circuit according to claim 1, characterized in that, The voltage detection circuit is a Hall sensor with model number HC5F900-S.

10. A motor controller, characterized in that, Includes the overcurrent shutdown circuit as described in any one of claims 1-9.

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