Wide-temperature low-current mismatch charge pump circuit

Abstract

The utility model discloses a wide-temperature low-current mismatch charge pump circuit, and relates to the field of charge pump circuits. The wide-temperature low-current mismatch charge pump circuit comprises a biasing circuit and a core circuit, the biasing circuit is connected with the core circuit; the bias circuit is used for providing bias voltage and bias current irrelevant to temperature for the core circuit; the bias circuit comprises a starting circuit, a positive temperature coefficient current source, a negative temperature coefficient current source and a bias voltage generating circuit, the core circuit comprises a push-pull input structure circuit; the starting circuit enables the bias circuit to get rid of a degeneracy point when the bias circuit is started; the positive temperature coefficient current source is connected with the negative temperature coefficient current source; the bias voltage generation circuit is connected with the push-pull input structure circuit; the push-pull input structure circuit is used for matching the charging current and the discharging current. According to the invention, good current matching characteristics can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of charge pump circuit, in particular to a wide temperature low current mismatch charge pump circuit. BACKGROUND

[0002] The essence of charge pump is a switching current source, and the requirements for it are accurate and stable constant current source and ideal switch. In actual circuit design, it is very difficult to achieve these requirements, and the most important problems are two:

[0003] (1) Mismatch of charging and discharging current. The charging and discharging current of the charge pump is controlled by the input switch signals UP signal and DOWN signal. When the switch controlled by the UP signal is closed and the switch controlled by the DOWN signal is opened, the charge pump is in the charging state. When the switch controlled by the UP signal is opened and the switch controlled by the DOWN signal is closed, the charge pump is in the discharging state. When the two switches controlled by the UP signal and the DOWN signal are closed at the same time, in the ideal state, I UP = I DN At this time, the output voltage Vout remains unchanged. If the charge pump is used in a phase-locked loop (PLL), it can keep the PLL in a good locked state in this state. However, in actual circuit design, the charging and discharging current of the charge pump is not matched, which will cause the output voltage Vout to fluctuate slightly, thereby affecting the performance of the subsequent circuit. Therefore, the matching of the charging and discharging current of the charge pump is very important to the overall performance of the charge pump circuit.

[0004] (2) Unstable bias current of charge pump. In the design of the charge pump, the relatively good matching of the charging and discharging current is ensured under the condition of a certain range of bias current. If the bias current fluctuates when the environmental temperature changes, on the one hand, it will cause the power consumption of the circuit to change, and on the other hand, it may cause the response of the charge pump to the input signal to be no longer linear, thereby distorting the output signal. When the fluctuation is large, the charge pump circuit as a whole may not work normally. CONTENT OF THE INVENTION

[0005] The purpose of the present application is to provide a wide temperature low current mismatch charge pump circuit which can realize good current matching characteristics.

[0006] To achieve the above purpose, the present application provides the following solutions:

[0007] The present application provides a wide temperature low current mismatch charge pump circuit, comprising: a bias circuit and a core circuit; the bias circuit is connected with the core circuit;

[0008] The bias circuit is used to provide a bias voltage and a bias current independent of temperature to the core circuit.

[0009] The bias circuit comprises a starting circuit, a positive temperature coefficient current source, a negative temperature coefficient current source and a bias voltage generating circuit; and the core circuit comprises a push-pull input structure circuit.

[0010] The starting circuit is connected with the negative temperature coefficient current source; the negative temperature coefficient current source is connected with the positive temperature coefficient current source; the positive temperature coefficient current source is connected with the bias voltage generating circuit; and the bias voltage generating circuit is further connected with the push-pull input structure circuit.

[0011] The push-pull input structure circuit is used for matching charging current and discharging current.

[0012] Optionally, the positive temperature coefficient current source comprises a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a third resistor.

[0013] The source of the third PMOS transistor is connected with the source of the negative temperature coefficient current source and the source of the fourth PMOS transistor respectively.

[0014] The gate of the third PMOS transistor is connected with the gate of the fourth PMOS transistor.

[0015] The drain of the third PMOS transistor is connected with the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is connected with one end of the third resistor; the gate of the fourth NMOS transistor is connected with the gate of the fifth NMOS transistor, and the connection point is connected with the drain of the third PMOS transistor.

[0016] The drain of the fifth NMOS transistor is connected with the drain of the fourth PMOS transistor.

[0017] The source of the fifth NMOS transistor is connected with the other end of the third resistor.

[0018] Optionally, the negative temperature coefficient current source comprises a first PMOS transistor, a second PMOS transistor, a third NMOS transistor and a second resistor.

[0019] The source of the first PMOS transistor is connected with the source of the positive temperature coefficient current source and the source of the second PMOS transistor respectively.

[0020] The drain of the first PMOS transistor is connected with one end of the second resistor and the gate of the third NMOS transistor respectively.

[0021] The gate of the first PMOS transistor is connected with the gate of the second PMOS transistor, and the connection point is connected with the drain of the first PMOS transistor.

[0022] The drain of the second PMOS transistor is connected with the drain of the third NMOS transistor;

[0023] The source of the third NMOS transistor is connected with the positive temperature coefficient current source and the other end of the second resistance respectively.

[0024] Optionally, the wide-temperature low-current mismatch charge pump circuit further comprises a first power DC voltage end;

[0025] The first power DC voltage end is connected with the bias circuit and the core circuit respectively.

[0026] Optionally, the push-pull input structure circuit comprises a twelfth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a seventeenth NMOS transistor, a CMOS transmission gate, an operational amplifier, a thirteenth NMOS transistor, a sixteenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor and a fourteenth PMOS transistor.

[0027] The source of the twelfth NMOS transistor is connected with the source of the fourteenth NMOS transistor; the drain of the twelfth NMOS transistor is connected with the first power DC voltage end; the source of the twelfth NMOS transistor and the source of the fourteenth NMOS transistor are both connected with the drain of the thirteenth NMOS transistor; the drain of the fourteenth NMOS transistor is connected with the drain of the ninth PMOS transistor.

[0028] The drain of the fifteenth NMOS transistor is connected with the first power DC voltage end; the source of the fifteenth NMOS transistor is connected with the source of the seventeenth NMOS transistor; the source of the fifteenth NMOS transistor and the source of the seventeenth NMOS transistor are both connected with the drain of the sixteenth NMOS transistor; the drain of the seventeenth NMOS transistor is connected with the drain of the tenth PMOS transistor.

[0029] The first end of the CMOS transmission gate is connected with the first power DC voltage end; the second end of the CMOS transmission gate is grounded; the third end of the CMOS transmission gate is connected with the gate of the tenth PMOS transistor; the fourth end of the CMOS transmission gate is connected with the gate of the thirteenth PMOS transistor.

[0030] The output end of the operational amplifier is connected with the gate of the twelfth PMOS transistor and the gate of the fourteenth PMOS transistor respectively.

[0031] The same direction input end of the operational amplifier is connected with the drain of the nineteenth NMOS transistor; and the same direction input end of the operational amplifier is also connected with the drain of the twelfth PMOS transistor;

[0032] The opposite direction input end of the operational amplifier is connected with the drain of the fourteenth PMOS transistor and the drain of the twentieth NMOS transistor respectively;

[0033] The source of the ninth PMOS transistor is connected with the first power DC voltage end; the gate of the ninth PMOS transistor is connected with the gate of the eleventh PMOS transistor; and the source of the eleventh PMOS transistor is connected with the first power DC voltage end;

[0034] The drain of the eleventh PMOS transistor is connected with the drain of the eighteenth NMOS transistor; the gate of the eighteenth NMOS transistor is connected with the gate of the twenty-first NMOS transistor; the drain of the twenty-first NMOS transistor is connected with the source of the twentieth NMOS transistor; the gate of the twentieth NMOS transistor is connected with the gate of the nineteenth NMOS transistor; the drain of the twentieth NMOS transistor is also connected with the drain of the fourteenth PMOS transistor; the drain of the nineteenth NMOS transistor is connected with the drain of the twelfth PMOS transistor;

[0035] The source of the tenth PMOS transistor is connected with the first power DC voltage end;

[0036] The gate of the thirteenth NMOS transistor is connected with the bias circuit; and the gate of the sixteenth NMOS transistor is connected with the bias circuit;

[0037] The source of the twelfth PMOS transistor is connected with the first power DC voltage end; the gate of the twelfth PMOS transistor is connected with the gate of the fourteenth PMOS transistor; the source of the fourteenth PMOS transistor is connected with the drain of the thirteenth PMOS transistor; and the source of the thirteenth PMOS transistor is connected with the first power DC voltage end.

[0038] Optionally, the starting circuit comprises: a first resistance, a first NMOS transistor and a second NMOS transistor;

[0039] One end of the first resistance is connected with the negative temperature coefficient current source; the other end of the first resistance is connected with the drain of the first NMOS transistor, the gate of the first NMOS transistor, the gate of the second NMOS transistor and the drain of the second NMOS transistor respectively; the gate of the first NMOS transistor is connected with the drain of the second NMOS transistor; the source of the second NMOS transistor is connected with the negative temperature coefficient current source; and the source of the first NMOS transistor is connected with the negative temperature coefficient current source.

[0040] Optionally, the bias voltage generating circuit comprises a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor.

[0041] The source of the fifth PMOS transistor is connected with the positive temperature coefficient current source; the gate of the fifth PMOS transistor is connected with the positive temperature coefficient current source; the drain of the fifth PMOS transistor is connected with the drain of the sixth NMOS transistor; the source of the sixth NMOS transistor is connected with the positive temperature coefficient current source; the gate of the sixth NMOS transistor is connected with the gate of the ninth NMOS transistor; the source of the ninth NMOS transistor is connected with the source of the sixth NMOS transistor; the drain of the ninth NMOS transistor is connected with the source of the eighth NMOS transistor; the drain of the eighth NMOS transistor is connected with the source of the seventh NMOS transistor; the gate of the eighth NMOS transistor is connected with the gate of the seventh NMOS transistor; the drain of the seventh NMOS transistor is connected with the drain of the seventh PMOS transistor; the source of the seventh PMOS transistor is connected with the source of the sixth PMOS transistor and the source of the eighth PMOS transistor respectively; the source of the sixth PMOS transistor is also connected with the source of the fifth PMOS transistor; the gate of the sixth PMOS transistor is connected with the positive temperature coefficient current source; the drain of the sixth PMOS transistor is connected with the drain of the fifth PMOS transistor; the gate of the seventh PMOS transistor is connected with the gate of the eighth PMOS transistor; the drain of the eighth PMOS transistor is connected with the drain of the tenth NMOS transistor; the source of the tenth NMOS transistor is connected with the drain of the eleventh NMOS transistor; the gate of the tenth NMOS transistor and the gate of the eleventh NMOS transistor are both connected with the drain of the eighth PMOS transistor; the source of the eleventh NMOS transistor is connected with the source of the ninth NMOS transistor.

[0042] Optionally, the bias voltage generating circuit further comprises a second power supply DC voltage terminal.

[0043] The second power supply DC voltage terminal is connected with the gate of the eighth NMOS transistor and the gate of the seventh NMOS transistor respectively.

[0044] Optionally, the wide-temperature low-current mismatch charge pump circuit further comprises a ground terminal.

[0045] The ground terminal is connected with the bias circuit and the core circuit respectively.

[0046] Optionally, the wide-temperature low-current mismatch charge pump circuit generates a 50 μA current in a temperature range of -40℃-170℃, and the temperature coefficient is 31 ppm / ℃.

[0047] According to the specific embodiments provided in the application, the application has the following technical effects:

[0048] The application provides a wide-temperature low-current mismatch charge pump circuit, which comprises a bias circuit and a core circuit; the bias circuit is used for providing a bias voltage and a temperature-independent bias current to the core circuit; wherein the bias circuit comprises a starting circuit, a positive temperature coefficient current source, a negative temperature coefficient current source and a bias voltage generating circuit; the core circuit comprises a push-pull input structure circuit; the positive temperature coefficient current source is connected with the negative temperature coefficient current source; the bias voltage generating circuit is connected with the push-pull input structure circuit; and the push-pull input structure circuit is used for matching charging current and discharging current. The positive temperature coefficient current source and the negative temperature coefficient current source can compensate the slope of the negative temperature coefficient current with the slope of the positive temperature coefficient current, and the superposition of the two currents can generate the temperature-independent bias current, and the push-pull input structure circuit can make the charging current and the discharging current match as much as possible, so that good current matching characteristics can be realized in the output voltage range; thus, the application can realize good current matching characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the application or the related art, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0050] Figure 1 It is a structure diagram of the existing push-pull input charge pump circuit;

[0051] Figure 2 It is a structure diagram of the wide-temperature low-current mismatch charge pump circuit;

[0052] Figure 3 It is a result diagram of the current source adjusting current;

[0053] Figure 4 It is a schematic diagram before the charging current and the discharging current are matched;

[0054] Figure 5 It is a schematic diagram after the charging current and the discharging current are matched.

[0055] Reference signs:

[0056] The first resistance R1, the second resistance R2, the third resistance R3, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, the tenth NMOS transistor NM10, the eleventh NMOS transistor NM11, the twelfth NMOS transistor NM12, the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, the fifteenth NMOS transistor NM15, the sixteenth NMOS transistor NM16, the seventeenth NMOS transistor NM17, the eighteenth NMOS transistor NM18, the nineteenth NMOS transistor NM19, the twentieth NMOS transistor NM20, the twenty-first NMOS transistor NM21, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, the CMOS transfer gate TG1, the operational amplifier OP1, the first power supply direct current voltage terminal VDD1, the second power supply direct current voltage terminal VDD2, and the ground terminal GND. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0058] The above purposes, features and advantages of the present application will be more obvious and easy to understand. The present application will be described in further detail below with reference to the drawings and specific embodiments.

[0059] In the existing push-pull input charge pump circuit design, as shown in the charge pump circuit structure in FIG. 1, the charge and discharge currents of the charge pump are mismatched, which will cause the output voltage Vout to fluctuate, and further affect the performance of the subsequent circuit. Therefore, the matching of the charge and discharge currents of the charge pump is very important to the overall performance of the charge pump circuit. Figure 1 The matching of the charge and discharge currents of the charge pump is very important to the overall performance of the charge pump circuit.

[0060] The application provides a wide-temperature low-current mismatch charge pump circuit, which comprises a bias circuit and a core circuit.

[0061] The bias circuit is used for providing a bias voltage and a temperature-independent bias current to the core circuit; wherein the bias circuit comprises a start-up circuit, a positive temperature coefficient current source, a negative temperature coefficient current source and a bias voltage generating circuit; and the core circuit comprises a push-pull input structure circuit.

[0062] The start-up circuit is connected with the negative temperature coefficient current source; the negative temperature coefficient current source is connected with the positive temperature coefficient current source; the positive temperature coefficient current source is connected with the bias voltage generating circuit; the bias voltage generating circuit is also connected with the push-pull input structure circuit; and the push-pull input structure circuit is used for matching charging current and discharging current. The start-up circuit makes the bias circuit get rid of degenerate point at the start-up time.

[0063] The structure of the wide-temperature low-current mismatch charge pump circuit mentioned in the application is shown in Figure 2 .

[0064] Specifically, the positive temperature coefficient current source comprises a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5 and a third resistor R3.

[0065] The source of the third PMOS transistor PM3 is connected with the negative temperature coefficient current source and the source of the fourth PMOS transistor PM4 respectively; the gate of the third PMOS transistor PM3 is connected with the gate of the fourth PMOS transistor PM4; the drain of the third PMOS transistor PM3 is connected with the drain of the fourth NMOS transistor NM4; the source of the fourth NMOS transistor NM4 is connected with one end of the third resistor; the gate of the fourth NMOS transistor NM4 is connected with the gate of the fifth NMOS transistor NM5, and the connection point is connected with the drain of the third PMOS transistor PM3.

[0066] The drain of the fifth NMOS transistor NM5 is connected with the drain of the fourth PMOS transistor PM4; and the source of the fifth NMOS transistor NM5 is connected with the other end of the third resistor R3.

[0067] The negative temperature coefficient current source comprises a first PMOS transistor PM1, a second PMOS transistor PM2, a third NMOS transistor NM3 and a second resistor R2.

[0068] The source of the first PMOS transistor PM1 is connected with the positive temperature coefficient current source and the source of the second PMOS transistor PM2 respectively; the drain of the first PMOS transistor PM1 is connected with one end of the second resistor R2 and the gate of the third NMOS transistor NM3 respectively; the gate of the first PMOS transistor PM1 is connected with the gate of the second PMOS transistor PM2, and the connection point is connected with the drain of the first PMOS transistor PM1.

[0069] The drain of the second PMOS transistor PM2 is connected with the drain of the third NMOS transistor NM3; the source of the third NMOS transistor NM3 is connected with the positive temperature coefficient current source and the other end of the second resistor R2 respectively.

[0070] The wide-temperature low-current mismatch charge pump circuit further comprises a first power supply DC voltage end VDD1; the first power supply DC voltage end VDD1 is connected with the bias circuit and the core circuit respectively.

[0071] The push-pull input structure circuit comprises a twelfth NMOS transistor NM12, a fourteenth NMOS transistor NM14, a fifteenth NMOS transistor NM15, a seventeenth NMOS transistor NM17, a CMOS transfer gate TG1, an operational amplifier OP1, a thirteenth NMOS transistor NM13, a sixteenth NMOS transistor NM16, an eighteenth NMOS transistor NM18, a nineteenth NMOS transistor NM19, a twentieth NMOS transistor NM20, a twenty-first NMOS transistor NM21, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, a thirteenth PMOS transistor PM13 and a fourteenth PMOS transistor PM14.

[0072] The source of the twelfth NMOS transistor NM12 is connected with the source of the fourteenth NMOS transistor NM14; the drain of the twelfth NMOS transistor NM12 is connected with the first power supply DC voltage end VDD1; the source of the twelfth NMOS transistor NM12 and the source of the fourteenth NMOS transistor NM14 are both further connected with the drain of the thirteenth NMOS transistor NM13; the drain of the fourteenth NMOS transistor NM14 is connected with the drain of the ninth PMOS transistor PM9.

[0073] The drain of the fifteenth NMOS transistor NM15 is connected with the first power supply DC voltage terminal VDD1; the source of the fifteenth NMOS transistor NM15 is connected with the source of the seventeenth NMOS transistor NM17; the source of the fifteenth NMOS transistor NM15 and the source of the seventeenth NMOS transistor NM17 are both connected with the drain of the sixteenth NMOS transistor NM16; the drain of the seventeenth NMOS transistor NM17 is connected with the drain of the tenth PMOS transistor PM10.

[0074] The first end of the CMOS transmission gate TG1 is connected with the first power supply DC voltage terminal VDD1; the second end of the CMOS transmission gate TG1 is grounded; the third end of the CMOS transmission gate TG1 is connected with the gate of the tenth PMOS transistor PM10; the fourth end of the CMOS transmission gate TG1 is connected with the gate of the thirteenth PMOS transistor PM13.

[0075] The output end of the operational amplifier OP1 is connected with the gate of the twelfth PMOS transistor PM12 and the gate of the fourteenth PMOS transistor PM14 respectively.

[0076] The same direction input end of the operational amplifier OP1 is connected with the drain of the nineteenth NMOS transistor NM19; the same direction input end of the operational amplifier OP1 is also connected with the drain of the twelfth PMOS transistor PM12.

[0077] The opposite direction input end of the operational amplifier OP1 is connected with the drain of the fourteenth PMOS transistor PM14 and the drain of the twentieth NMOS transistor NM20 respectively.

[0078] The source of the ninth PMOS transistor PM9 is connected with the first power supply DC voltage terminal VDD1; the gate of the ninth PMOS transistor PM9 is connected with the gate of the eleventh PMOS transistor PM11; the source of the eleventh PMOS transistor PM11 is connected with the first power supply DC voltage terminal VDD1.

[0079] The drain of the eleventh PMOS transistor PM11 is connected with the drain of the eighteenth NMOS transistor NM18; the gate of the eighteenth NMOS transistor NM18 is connected with the gate of the twenty-first NMOS transistor NM21; the drain of the twenty-first NMOS transistor NM21 is connected with the source of the twentieth NMOS transistor NM20; the gate of the twentieth NMOS transistor NM20 is connected with the gate of the nineteenth NMOS transistor NM19; the drain of the twentieth NMOS transistor NM20 is also connected with the drain of the fourteenth PMOS transistor PM14; the drain of the nineteenth NMOS transistor NM19 is connected with the drain of the twelfth PMOS transistor PM12.

[0080] The source of the tenth PMOS transistor PM10 is connected with the first power supply direct current voltage terminal VDD1.

[0081] The gate of the thirteenth NMOS transistor NM13 is connected with the bias circuit; the gate of the sixteenth NMOS transistor NM16 is connected with the bias circuit.

[0082] The source of the twelfth PMOS transistor PM12 is connected with the first power supply direct current voltage terminal VDD1; the gate of the twelfth PMOS transistor PM12 is connected with the gate of the fourteenth PMOS transistor PM14; the source of the fourteenth PMOS transistor PM14 is connected with the drain of the thirteenth PMOS transistor PM13; the source of the thirteenth PMOS transistor PM13 is connected with the first power supply direct current voltage terminal VDD1.

[0083] The starting circuit comprises a first resistor R1, a first NMOS transistor NM1 and a second NMOS transistor NM2.

[0084] One end of the first resistor R1 is connected with the negative temperature coefficient current source; the other end of the first resistor R1 is connected with the drain of the first NMOS transistor NM1, the gate of the first NMOS transistor NM1, the gate of the second NMOS transistor NM2 and the drain of the second NMOS transistor NM2 respectively; the gate of the first NMOS transistor NM1 is connected with the drain of the second NMOS transistor NM2; the source of the second NMOS transistor NM2 is connected with the negative temperature coefficient current source; the source of the first NMOS transistor NM1 is connected with the negative temperature coefficient current source.

[0085] The bias voltage generating circuit comprises a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10 and an eleventh NMOS transistor NM11.

[0086] The source of the fifth PMOS transistor PM5 is connected with the positive temperature coefficient current source; the gate of the fifth PMOS transistor PM5 is connected with the positive temperature coefficient current source; the drain of the fifth PMOS transistor PM5 is connected with the drain of the sixth NMOS transistor NM6; the source of the sixth NMOS transistor NM6 is connected with the positive temperature coefficient current source; the gate of the sixth NMOS transistor NM6 is connected with the gate of the ninth NMOS transistor NM9; the source of the ninth NMOS transistor NM9 is connected with the source of the sixth NMOS transistor NM6; the drain of the ninth NMOS transistor NM9 is connected with the source of the eighth NMOS transistor NM8; the drain of the eighth NMOS transistor NM8 is connected with the source of the seventh NMOS transistor NM7; the gate of the eighth NMOS transistor NM8 is connected with the gate of the seventh NMOS transistor NM7; the drain of the seventh NMOS transistor NM7 is connected with the drain of the seventh PMOS transistor PM7; the source of the seventh PMOS transistor PM7 is connected with the source of the sixth PMOS transistor PM6 and the source of the eighth PMOS transistor PM8 respectively; the source of the sixth PMOS transistor PM6 is also connected with the source of the fifth PMOS transistor PM5; the gate of the sixth PMOS transistor PM6 is connected with the positive temperature coefficient current source; the drain of the sixth PMOS transistor PM6 is connected with the drain of the fifth PMOS transistor PM5; the gate of the seventh PMOS transistor PM7 is connected with the gate of the eighth PMOS transistor PM8; the drain of the eighth PMOS transistor PM8 is connected with the drain of the tenth NMOS transistor NM10; the source of the tenth NMOS transistor NM10 is connected with the drain of the eleventh NMOS transistor NM11; the gate of the tenth NMOS transistor NM10 and the gate of the eleventh NMOS transistor NM11 are both connected with the drain of the eighth PMOS transistor PM8; the source of the eleventh NMOS transistor NM11 is connected with the source of the ninth NMOS transistor NM9.

[0087] The bias voltage generating circuit further comprises a second power supply DC voltage terminal VDD2; the second power supply DC voltage terminal VDD2 is connected with the gate of the eighth NMOS transistor NM8 and the gate of the seventh NMOS transistor NM7 respectively.

[0088] The wide-temperature low-current mismatch charge pump circuit further comprises a ground terminal GND; the ground terminal GND is connected with the bias circuit and the core circuit respectively. The wide-temperature low-current mismatch charge pump circuit generates a 50 μA current in a temperature range of-40 ℃-170 ℃, and the temperature coefficient is 31 ppm / ℃.

[0089] Specifically, the charge pump circuit provided by the embodiment of the present application is composed of fourteen PMOS transistors, twenty-one NMOS transistors, three resistors, one CMOS transfer gate and one operational amplifier. Among them, the first resistor R1, the second resistor R2, the third resistor R3, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 constitute a bias circuit of the charge pump. The bias circuit provides bias voltages for the thirteenth NMOS transistor NM13, the sixteenth NMOS transistor NM16, the nineteenth NMOS transistor NM19 and the twentieth NMOS transistor NM20 and provides constant current for the core circuit of the charge pump, which is not affected by temperature.

[0090] The one end of the first resistor R1, the source of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 are electrically connected with the first power supply DC voltage terminal VDD1, and the source of the second NMOS transistor NM2, the other end of the second resistor R2, the source of the third NMOS transistor NM3, the source of the fourth NMOS transistor NM4, the other end of the third resistor R3, the source of the sixth NMOS transistor NM6, the source of the ninth NMOS transistor NM9, and the source of the eleventh NMOS transistor NM11 are electrically connected with the ground terminal GND. The gate and the drain of the first NMOS transistor NM1 and the second NMOS transistor NM2 are respectively connected and electrically connected with the other end of the first resistor R1, wherein the source of the first NMOS transistor NM1 is electrically connected with the node C, the gate and the drain of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the one end of the second resistor R2, and the gate of the third NMOS transistor NM3 are electrically connected with the node A, wherein the drain of the second PMOS transistor PM2 and the drain of the third NMOS transistor NM3 are electrically connected, the drain of the third PMOS transistor PM3, the gate and the drain of the fourth NMOS transistor NM4, and the gate of the fifth NMOS transistor NM5 are electrically connected with the node B, wherein the gate and the drain of the fourth PMOS transistor PM4, the gate of the fifth PMOS transistor PM5, and the drain of the fifth NMOS transistor NM5 are electrically connected with the node C, the source of the fifth NMOS transistor NM5 is electrically connected with the one end of the third resistor R3, wherein the drain of the fifth PMOS transistor PM5, the drain of the sixth PMOS transistor PM6, the gate and the drain of the sixth NMOS transistor NM6, and the gate of the ninth NMOS transistor NM9 are electrically connected with the node D, wherein the gate of the sixth PMOS transistor PM6 is electrically connected with the node A, the gate and the drain of the seventh PMOS transistor PM7, the gate of the eighth PMOS transistor PM8, and the drain of the seventh NMOS transistor NM7 are electrically connected with the node E, the source of the seventh NMOS transistor NM7 is electrically connected with the drain of the eighth NMOS transistor NM8, wherein the gate of the seventh NMOS transistor NM7 and the gate of the eighth NMOS transistor NM8 are electrically connected with the second power supply DC voltage terminal VDD2, the source of the eighth NMOS transistor NM8 is electrically connected with the drain of the ninth NMOS transistor NM9, the drain of the eighth PMOS transistor PM8, the gate and the drain of the tenth NMOS transistor NM10, and the gate of the eleventh NMOS transistor NM11 are electrically connected with the node F, wherein the source of the tenth NMOS transistor NM10 is electrically connected with the drain of the eleventh NMOS transistor NM11.

[0091] The twelfth NMOS transistor NM12, the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, the fifteenth NMOS transistor NM15, the sixteenth NMOS transistor NM16, the seventeenth NMOS transistor NM17, the eighteenth NMOS transistor NM18, the nineteenth NMOS transistor NM19, the twentieth NMOS transistor NM20, the twenty-first NMOS transistor NM21, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, the CMOS transfer gate TG1, and the operational amplifier OP1 constitute a charge pump core circuit, which is used for converting a clock phase difference value in a phase-locked loop into electric charges, and then controlling a voltage of a subsequent circuit, so as to realize accurate control of frequency and phase, wherein the drain electrode of the twelfth NMOS transistor NM12, the source electrode of the ninth PMOS transistor PM9, the drain electrode of the fifteenth NMOS transistor NM15, the source electrode of the tenth PMOS transistor PM10, the high-level active end of the CMOS transfer gate TG1, the source electrode of the twelfth PMOS transistor PM12, and the source electrode of the thirteenth PMOS transistor PM13 are electrically connected to a power direct-current voltage terminal VDD, the source electrode of the thirteenth NMOS transistor NM13, the source electrode of the sixteenth NMOS transistor NM16, the source electrode of the eighteenth NMOS transistor NM18, the source electrode of the nineteenth NMOS transistor NM19, and the source electrode of the twenty-first NMOS transistor NM21 are electrically connected to a ground terminal GND, the gate electrode of the twelfth NMOS transistor NM12 inputs an inverted signal DOWNB of a charge pump discharge switch signal, the source electrode of the twelfth NMOS transistor NM12, the source electrode of the fourteenth NMOS transistor NM14, and the drain electrode of the thirteenth NMOS transistor NM13 are electrically connected to a node G, the gate electrode of the thirteenth NMOS transistor NM13 and the gate electrode of the sixteenth NMOS transistor NM16 are electrically connected to the node D, the gate electrode and the drain electrode of the ninth PMOS transistor PM9, the gate electrode of the eleventh PMOS transistor PM11, and the drain electrode of the fourteenth NMOS transistor NM14 are electrically connected to a node H, wherein the gate electrode of the fourteenth NMOS transistor NM14 inputs the charge pump discharge switch signal DOWN, the gate electrode of the fifteenth NMOS transistor NM15 inputs an inverted signal UPB of a charge pump charging switch signal, the source electrode of the fifteenth NMOS transistor NM15, the source electrode of the seventeenth NMOS transistor NM17, and the drain electrode of the sixteenth NMOS transistor NM16 are electrically connected to a node I, the gate electrode and the drain electrode of the tenth PMOS transistor PM10, the input end of the CMOS transfer gate TG1, and the drain electrode of the seventeenth NMOS transistor NM17 are electrically connected to a node J, wherein the gate electrode of the seventeenth NMOS transistor NM17 inputs the charge pump charging switch signal UP,The drain of the eleventh PMOS transistor PM11, the gate and the drain of the eighteenth NMOS transistor NM18, and the gate of the twenty-first NMOS transistor NM21 are electrically connected to a node K, the output of the CMOS transmission gate TG1 is electrically connected to the gate of the thirteenth PMOS transistor PM13, the gate of the twelfth PMOS transistor PM12 and the gate of the fourteenth PMOS transistor PM14 are electrically connected to the output of the operational amplifier OP1, the drain of the twelfth PMOS transistor PM12 and the drain of the nineteenth NMOS transistor NM19 are electrically connected to the same input of the operational amplifier OP1 to a node Vref, the gate of the nineteenth NMOS transistor NM19 and the gate of the twentieth NMOS transistor NM20 are electrically connected to a node G, the drain of the thirteenth PMOS transistor PM13 and the source of the fourteenth PMOS transistor PM14 are electrically connected, the drain of the fourteenth PMOS transistor PM14 and the drain of the twentieth NMOS transistor NM20 are electrically connected to the opposite input of the operational amplifier to a node Vout, and the source of the twentieth NMOS transistor NM20 and the drain of the twenty-first NMOS transistor NM21 are electrically connected.

[0092] The third PMOS transistor PM3, the fourth PMOS transistor PM4, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the third resistor R3 constitute a positive temperature coefficient (PTAT) current source; the first PMOS transistor PM1, the second PMOS transistor PM2, the third NMOS transistor NM3, and the second resistor R2 constitute a negative temperature coefficient (CTAT) current source. By parameter adjustment, the slope of the negative temperature coefficient (CTAT) current can compensate for the slope of the positive temperature coefficient (PTAT) current, and the superposition of the two currents can generate a temperature-independent bias current. By adjusting the size of the two current source transistors, a wide range of current values can be generated, such as Figure 3 As shown, when a 50 μA current is generated in the temperature range of -40°C to 170°C, the temperature coefficient is only 31 ppm / °C.

[0093] The charge pump push-pull input structure is realized by the twelfth NMOS transistor NM12, the fourteenth NMOS transistor NM14, the fifteenth NMOS transistor NM15, and the seventeenth NMOS transistor NM17, and the push-pull input structure circuit is obtained. The transmission gate TG1 compensates for the different transmission delays of the charge pump charging switch signal UP and the discharging switch signal DOWN, and when the operational amplifier OP1 is used as a voltage follower, Vout = Vref, so that the charging current I UP and the discharging current I DNAs much as possible match, such as Figure 4 And Figure 5 As shown in the figure, under the 3.3V power supply voltage, the output voltage of the charge pump is changed from 0V to 3.3V, the 1% current mismatch output voltage range of the existing push-pull input charge pump circuit is 0.59V-1.87V, and the 1% current mismatch output voltage range of the wide-temperature low-current mismatch charge pump circuit mentioned in the application is 0.32V-2.4V, so it can be seen that the current matching characteristic of the wide-temperature low-current mismatch charge pump circuit mentioned in the application is greatly improved.

[0094] The technical features of the above embodiments can be combined in any way. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0095] The principles and implementation modes of the present application are described by applying specific examples herein, and the above embodiments are only used to help understand the circuit of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In conclusion, the content of the present application should not be understood as a limitation.

Claims

1. A wide-temperature low-current mismatched charge pump circuit, comprising: The wide-temperature low-current mismatched charge pump circuit comprises a bias circuit and a core circuit, and the bias circuit is connected with the core circuit; The bias circuit is configured to provide a bias voltage and a temperature-independent bias current to the core circuit; The bias circuit comprises a start-up circuit, a positive temperature coefficient current source, a negative temperature coefficient current source and a bias voltage generation circuit, and the core circuit comprises a push-pull input structure circuit; The start-up circuit is connected with the negative temperature coefficient current source, the negative temperature coefficient current source is connected with the positive temperature coefficient current source, the positive temperature coefficient current source is connected with the bias voltage generation circuit, and the bias voltage generation circuit is further connected with the push-pull input structure circuit; The push-pull input structure circuit is configured to match charging current and discharging current.

2. The wide-temperature low-current mismatched charge pump circuit of claim 1, wherein, The positive temperature coefficient current source comprises a third PMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a third resistor; The source of the third PMOS transistor is connected with the source of the negative temperature coefficient current source and the source of the fourth PMOS transistor respectively; The gate of the third PMOS transistor is connected with the gate of the fourth PMOS transistor; The drain of the third PMOS transistor is connected with the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected with one end of the third resistor, the gate of the fourth NMOS transistor is connected with the gate of the fifth NMOS transistor, and the connection point is connected with the drain of the third PMOS transistor; The drain of the fifth NMOS transistor is connected with the drain of the fourth PMOS transistor; The source of the fifth NMOS transistor is connected with the other end of the third resistor.

3. The wide-temperature low-current mismatched charge pump circuit of claim 1, wherein, The negative temperature coefficient current source comprises a first PMOS transistor, a second PMOS transistor, a third NMOS transistor and a second resistor; The source of the first PMOS transistor is connected with the source of the positive temperature coefficient current source and the source of the second PMOS transistor respectively; The drain of the first PMOS transistor is connected with one end of the second resistor and the gate of the third NMOS transistor respectively; The gate of the first PMOS transistor is connected with the gate of the second PMOS transistor, and the connection point is connected with the drain of the first PMOS transistor; The drain of the second PMOS transistor is connected with the drain of the third NMOS transistor; The source of the third NMOS transistor is connected with the positive temperature coefficient current source and the other end of the second resistor respectively.

4. The wide-temperature low-current mismatched charge pump circuit of claim 1, wherein, The wide-temperature low-current mismatched charge pump circuit further comprises a first power supply DC voltage end; The first power supply DC voltage end is connected with the bias circuit and the core circuit respectively.

5. The wide-temperature low-current mismatched charge pump circuit of claim 4, wherein, The push-pull input structure circuit comprises a twelfth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a seventeenth NMOS transistor, a CMOS transfer gate, an operational amplifier, a thirteenth NMOS transistor, a sixteenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor and a fourteenth PMOS transistor; The source of the twelfth NMOS transistor is connected with the source of the fourteenth NMOS transistor; the drain of the twelfth NMOS transistor is connected with the first power DC voltage terminal; the source of the twelfth NMOS transistor and the source of the fourteenth NMOS transistor are both connected with the drain of the thirteenth NMOS transistor; the drain of the fourteenth NMOS transistor is connected with the drain of the ninth PMOS transistor; The drain of the fifteenth NMOS transistor is connected with the first power DC voltage terminal; the source of the fifteenth NMOS transistor is connected with the source of the seventeenth NMOS transistor; the source of the fifteenth NMOS transistor and the source of the seventeenth NMOS transistor are both connected with the drain of the sixteenth NMOS transistor; the drain of the seventeenth NMOS transistor is connected with the drain of the tenth PMOS transistor; The first end of the CMOS transfer gate is connected with the first power DC voltage terminal; the second end of the CMOS transfer gate is grounded; the third end of the CMOS transfer gate is connected with the gate of the tenth PMOS transistor; the fourth end of the CMOS transfer gate is connected with the gate of the thirteenth PMOS transistor; The output end of the operational amplifier is connected with the gate of the twelfth PMOS transistor and the gate of the fourteenth PMOS transistor respectively; The same direction input end of the operational amplifier is connected with the drain of the nineteenth NMOS transistor; the same direction input end of the operational amplifier is also connected with the drain of the twelfth PMOS transistor; The opposite direction input end of the operational amplifier is connected with the drain of the fourteenth PMOS transistor and the drain of the twentieth NMOS transistor respectively; The source of the ninth PMOS transistor is connected with the first power DC voltage terminal; the gate of the ninth PMOS transistor is connected with the gate of the eleventh PMOS transistor; the source of the eleventh PMOS transistor is connected with the first power DC voltage terminal; The drain of the eleventh PMOS transistor is connected with the drain of the eighteenth NMOS transistor; the gate of the eighteenth NMOS transistor is connected with the gate of the twenty-first NMOS transistor; the drain of the twenty-first NMOS transistor is connected with the source of the twentieth NMOS transistor; the gate of the twentieth NMOS transistor is connected with the gate of the nineteenth NMOS transistor; the drain of the twentieth NMOS transistor is also connected with the drain of the fourteenth PMOS transistor; the drain of the nineteenth NMOS transistor is connected with the drain of the twelfth PMOS transistor; The source of the tenth PMOS transistor is connected with the first power DC voltage terminal; The gate of the thirteenth NMOS transistor is connected with a bias circuit; and the gate of the sixteenth NMOS transistor is connected with the bias circuit. The source of the twelfth PMOS transistor is connected with a first power DC voltage terminal; the gate of the twelfth PMOS transistor is connected with the gate of the fourteenth PMOS transistor; the source of the fourteenth PMOS transistor is connected with the drain of the thirteenth PMOS transistor; and the source of the thirteenth PMOS transistor is connected with the first power DC voltage terminal.

6. The wide-temperature, low-current mismatched charge pump circuit of claim 1, wherein, The starting circuit comprises a first resistor, a first NMOS transistor and a second NMOS transistor. One end of the first resistor is connected with a negative temperature coefficient current source; the other end of the first resistor is connected with the drain of the first NMOS transistor, the gate of the first NMOS transistor, the gate of the second NMOS transistor and the drain of the second NMOS transistor respectively; the gate of the first NMOS transistor is connected with the drain of the second NMOS transistor; the source of the second NMOS transistor is connected with the negative temperature coefficient current source; and the source of the first NMOS transistor is connected with the negative temperature coefficient current source.

7. The wide-temperature, low-current mismatched charge pump circuit of claim 1, wherein, The bias voltage generating circuit comprises a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor and an eleventh NMOS transistor. The source of the fifth PMOS transistor is connected with the positive temperature coefficient current source; the gate of the fifth PMOS transistor is connected with the positive temperature coefficient current source; the drain of the fifth PMOS transistor is connected with the drain of the sixth NMOS transistor; the source of the sixth NMOS transistor is connected with the positive temperature coefficient current source; the gate of the sixth NMOS transistor is connected with the gate of the ninth NMOS transistor; the source of the ninth NMOS transistor is connected with the source of the sixth NMOS transistor; the drain of the ninth NMOS transistor is connected with the source of the eighth NMOS transistor; the drain of the eighth NMOS transistor is connected with the source of the seventh NMOS transistor; the gate of the eighth NMOS transistor is connected with the gate of the seventh NMOS transistor; the drain of the seventh NMOS transistor is connected with the drain of the seventh PMOS transistor; the source of the seventh PMOS transistor is connected with the source of the sixth PMOS transistor and the source of the eighth PMOS transistor respectively; the source of the sixth PMOS transistor is also connected with the source of the fifth PMOS transistor; the gate of the sixth PMOS transistor is connected with the positive temperature coefficient current source; the drain of the sixth PMOS transistor is connected with the drain of the fifth PMOS transistor; the gate of the seventh PMOS transistor is connected with the gate of the eighth PMOS transistor; the drain of the eighth PMOS transistor is connected with the drain of the tenth NMOS transistor; the source of the tenth NMOS transistor is connected with the drain of the eleventh NMOS transistor; the gate of the tenth NMOS transistor and the gate of the eleventh NMOS transistor are both connected with the drain of the eighth PMOS transistor; the source of the eleventh NMOS transistor is connected with the source of the ninth NMOS transistor.

8. The wide-temperature low-current mismatched charge pump circuit of claim 7, wherein, The bias voltage generating circuit further comprises a second power supply DC voltage terminal; The second power supply DC voltage terminal is connected with the gate of the eighth NMOS transistor and the gate of the seventh NMOS transistor respectively.

9. The wide-temperature, low-current mismatched charge pump circuit of claim 1, wherein, The wide-temperature low-current mismatch charge pump circuit further comprises a ground terminal; The ground terminal is connected with the bias circuit and the core circuit respectively.

10. The wide-temperature, low-current mismatched charge pump circuit of claim 1, wherein, The wide-temperature low-current mismatch charge pump circuit generates a 50 μA current in a temperature range of-40 ℃-170 ℃, and the temperature coefficient is 31 ppm / ℃.

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