Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a substrate, a first source drain electrode layer and a second source drain electrode layer, the first source drain electrode layer and the second source drain electrode layer are arranged on one side of the substrate, the first source drain electrode layer comprises a plurality of conductive parts which are arranged at intervals and located in a display area, and the second source drain electrode layer comprises a plurality of compensation parts which are arranged at intervals and located in the display area. Orthographic projections of the plurality of compensation parts on the substrate and orthographic projections of the plurality of conductive parts on the substrate are arranged in a non-overlapping manner; when patterning processing is carried out on the second source and drain electrode layer, the multiple compensation parts arranged at intervals are formed at the same time, and the compensation parts correspond to the areas among the multiple conductive parts in the first source and drain electrode layer so as to compensate the areas, where the conductive parts are not arranged, in the first source and drain electrode layer. The flatness of the flat layer covering the first source-drain electrode layer and the second source-drain electrode layer is improved, and the uniformity of the thickness of the film layer of the light-emitting layer is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Organic Light-Emitting Diode (OLED) is a new type of current semiconductor light-emitting device, which is a kind of display device by controlling the carrier and excited organic material light-emitting.

[0003] For the OLED display panel prepared by the current inkjet printing, due to the setting of the conductive wire and the capacitor plate, the flatness of the flat layer surface covering the conductive wire and the capacitor plate is poor, which leads to different thickness of the printed ink in different areas, that is, the film layer thickness uniformity of the light-emitting layer is poor, and further affects the service life and light-emitting efficiency of the light-emitting material. UTILITY MODEL CONTENT

[0004] The present application provides a display panel and a display device to solve the technical problem of poor film layer uniformity of the existing OLED display panel.

[0005] To solve the above-mentioned scheme, the technical scheme provided by the present application is as follows:

[0006] The present application provides a display panel, characterized in that it comprises a display area and a non-display area arranged on at least one side of the display area; wherein the display panel comprises:

[0007] a substrate substrate;

[0008] a first source-drain layer arranged on one side of the substrate substrate, the first source-drain layer comprising a plurality of conductive parts arranged at intervals and located in the display area;

[0009] a second source-drain layer arranged on the side of the first source-drain layer away from the substrate substrate, the second source-drain layer comprising a plurality of compensation parts arranged at intervals and located in the display area;

[0010] wherein the orthogonal projection of the plurality of compensation parts on the substrate substrate is non-overlapping with the orthogonal projection of the plurality of conductive parts on the substrate substrate.

[0011] Optionally, at least one first transistor is arranged in the display area, the plurality of conductive parts comprises a first source and a first drain of the first transistor, and the plurality of compensation parts comprises a first compensation block and a second compensation block arranged at intervals.

[0012] The first compensation block is located between the first source and the first drain on the first source / drain layer.

[0013] Optionally, the first source / drain layer further comprises a first plate spaced apart from the plurality of conductive portions, and the second source / drain layer further comprises a second plate opposite to the first plate, the first plate and the second plate having an overlapping portion.

[0014] The second plate is connected to the second compensation block, and the second compensation block is located between the first drain and the first plate on the first source / drain layer.

[0015] Optionally, the display panel further comprises:

[0016] a gate layer between the first source / drain layer and the substrate, the gate layer comprising a first gate of the first transistor.

[0017] The first compensation block has an overlapping portion with the first gate on the substrate.

[0018] Optionally, the thickness of the gate layer is less than the thickness of the first source / drain layer.

[0019] Optionally, the display panel further comprises:

[0020] a light shielding layer between the substrate and the gate layer.

[0021] a semiconductor layer between the light shielding layer and the gate layer.

[0022] The light shielding layer comprises a third plate opposite to the first plate, and the semiconductor layer comprises a fourth plate opposite to the third plate, the first plate, the second plate, the third plate and the fourth plate forming a storage capacitor of the display panel.

[0023] Optionally, at least one second transistor is arranged in the non-display area.

[0024] The semiconductor layer comprises a first active portion of the first transistor and a second active portion of the second transistor, the mobility of the first active portion being less than or equal to the mobility of the second active portion.

[0025] Optionally, the display panel further comprises:

[0026] a buffer layer between the semiconductor layer and the light shielding layer.

[0027] The protective layer includes a first portion located in the display area and a second portion located in the non-display area. The first portion is disposed on the surface of the first active portion away from the substrate, and the second portion is disposed between the second active portion and the buffer layer.

[0028] The mobility of the first active part is less than that of the second active part.

[0029] Optionally, the display panel further includes:

[0030] A light-emitting layer is disposed on the side of the second source / drain layer away from the substrate, and the light-emitting layer further includes a plurality of spaced-apart light-emitting portions;

[0031] In this configuration, multiple compensation units are orthogonally projected onto the light-emitting layer and located within their respective light-emitting units.

[0032] This application also proposes a display device, which includes the above-described display panel.

[0033] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0036] Figure 1 A simplified structural diagram of the display panel provided in the embodiments of this application;

[0037] Figure 2 for Figure 1 The first structural diagram of the mid-section MM;

[0038] Figure 3 for Figure 1 The second structural diagram of the mid-section MM. Detailed Implementation

[0039] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0040] With reference to Figures 1 to 3 The present application provides a display panel 100, which comprises a display area AA and a non-display area NA arranged at least one side of the display area AA, and the display panel 100 comprises a substrate 10 and a first source-drain layer SD1 and a second source-drain layer SD2 arranged at one side of the substrate 10.

[0041] In the embodiment, the first source-drain layer SD1 is arranged at one side of the substrate 10, and the first source-drain layer SD1 comprises a plurality of conductive parts CD arranged at intervals and located in the display area AA; the second source-drain layer SD2 is arranged at a side of the first source-drain layer SD1 away from the substrate 10, and the second source-drain layer SD2 comprises a plurality of compensation parts CP arranged at intervals and located in the display area AA.

[0042] In the embodiment, the plurality of compensation parts CP are arranged at a side of the first source-drain layer SD1 away from the substrate 10, and the plurality of compensation parts CP are arranged at a side of the first source-drain layer SD1 away from the substrate 10.

[0043] The present application simultaneously forms a plurality of compensation parts CP arranged at intervals when the second source-drain layer SD2 is subjected to a patterning process, and the area between the compensation parts CP and the plurality of conductive parts CD in the first source-drain layer SD1 corresponds to the area in which no conductive part CD is arranged in the first source-drain layer SD1, so as to compensate for the area in which no conductive part CD is arranged in the first source-drain layer SD1, improve the flatness of the planar layer covering the first source-drain layer SD1 and the second source-drain layer SD2, and improve the uniformity of the film thickness of the light-emitting layer 402.

[0044] The technical solutions of the present application will be described in combination with specific embodiments.

[0045] With reference to Figure 1 The display panel 100 comprises a display area AA and a non-display area NA arranged adjacent to the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for displaying, and a plurality of sub-pixels PX for realizing the display function are arranged in the display area AA. The non-display area NA can be a frame area of the display panel 100, and functional components for assisting the sub-pixels PX in the display area AA to display can be arranged in the non-display area NA.

[0046] With reference toFigure 1 The lower side of the display area AA can be provided with a binding terminal, which can be connected with an external circuit, and the binding terminal transmits a signal input by the external circuit to a data trace, so as to drive the display panel 100 to display a picture. For example, the binding terminal can be connected with a chip or a chip on film, etc., and is used to provide a power supply and a driving signal for the display panel 100.

[0047] Please refer to Figures 2 to 3 The display panel 100 can include a substrate 10, an array layer 20 arranged on the substrate 10, a pixel layer 30 arranged on the array layer 20, a light-emitting functional layer 40, and an encapsulation layer 50.

[0048] In the embodiment, the material of the substrate 10 can be glass, quartz, polyimide, etc. For example, when the display panel 100 is a flexible panel, the material of the substrate 10 can be a flexible material such as polyimide, or is composed of a laminated film layer of a flexible material and an inorganic material. When the display panel 100 is a rigid panel, the material of the substrate 10 can be a rigid material such as glass or quartz.

[0049] Please refer to Figures 2 to 3 The array layer 20 can include a plurality of thin film transistors, which can be etch-stop type, back channel etch type, or can be divided into bottom-gate thin film transistors, top-gate thin film transistors, etc. according to the position of the gate and the semiconductor layer AS, and the specific structure is not limited.

[0050] In the embodiment, at least one first transistor T1 is arranged in the display area AA, and at least one second transistor T2 is arranged in the non-display area NA. Meanwhile, a pixel driving circuit and a storage capacitor Cst are arranged in the display area AA, the pixel driving circuit includes the first transistor T1, a gate driving circuit is arranged in the non-display area NA, and the gate driving circuit includes the second transistor T2.

[0051] It should be noted that, in order to simplify the process, the first transistor T1 and the second transistor T2 in the display area AA and the non-display area NA can be prepared at the same time.

[0052] For example, please refer to Figures 2 to 3The thin film transistor shown in the figure can be a top-gate thin film transistor, the array layer 20 can include a light shielding layer LS disposed on the substrate 10, a buffer layer 201 disposed on the light shielding layer LS, a semiconductor layer AS disposed on the buffer layer 201, a first gate insulating layer 202 disposed on the semiconductor layer AS, a gate electrode layer GE disposed on the first gate insulating layer 202, an interlayer insulating layer 203 disposed on the gate electrode layer GE, a first source-drain layer SD1 disposed on the interlayer insulating layer 203, a passivation layer 204 disposed on the first source-drain layer SD1, a first planarization layer 205 disposed on the passivation layer 204, a second source-drain layer SD2 disposed on the first planarization layer 205, and a second planarization layer 206 disposed on the second source-drain layer SD2.

[0053] It should be noted that the number of source-drain layers can be set according to the wiring space requirement, for example, the source-drain layer of the present application can be two layers; at the same time, the number of gate electrode layers GE is set according to the requirement of wiring space and capacitance, for example, the gate electrode layer GE of the present application is one layer.

[0054] It should be noted that the buffer layer 201, the first gate insulating layer 202, the interlayer insulating layer 203 and the passivation layer 204 can all be inorganic materials composed of elements such as nitrogen, silicon, oxygen, aluminum, etc., for example, a single layer or a plurality of stacked inorganic film layers composed of one of silicon nitride, silicon oxide and aluminum oxide.

[0055] It should be noted that the planarization layer of the present application is set to ensure the flatness of the film layer, and the number of planarization layers is set according to the requirement of the flatness of the film layer, for example, the planarization layer of the present application can be two layers.

[0056] Please refer to Figures 2 to 3 The pixel layer 30 can include a first pixel definition layer 310 and a second pixel definition layer 320, the first pixel definition layer 310 is disposed on the side of the second planarization layer 206 away from the substrate 10, and the second pixel definition layer 320 is disposed on the surface of the first pixel definition layer 310 away from the substrate 10.

[0057] It should be noted that since the light-emitting layer 402 of the present application is prepared by inkjet printing process, in order to reduce the precision of inkjet printing, the first pixel definition layer 310 of the present application can include a plurality of first shielding strips staggered horizontally and vertically, the first shielding strips are enclosed to form a plurality of pixel openings corresponding to the sub-pixels, the second pixel definition layer 320 includes a plurality of second shielding strips horizontally or vertically, and the colors of the plurality of sub-pixels between the adjacent two second shielding strips are the same, so that in the inkjet printing process, the plurality of sub-pixels between the adjacent two second shielding strips can be printed simultaneously along the arrangement direction of the second shielding strips, reducing the precision of inkjet printing and improving the process efficiency.

[0058] It should be noted that the first pixel definition layer 310 and the second pixel definition layer 320 of the present application can be formed in one process, that is, the film layers of the first pixel definition layer 310 and the second pixel definition layer 320 are formed at the same time, and the first pixel definition layer 310 and the second pixel definition layer 320 are patterned in the same mask, so that the first pixel definition layer 310 forms a plurality of first shielding strips, and the second pixel definition layer 320 forms a plurality of second shielding strips, for example, the present application can include a plurality of first shielding strips extending along the second direction and arranged along the first direction, and a plurality of second shielding strips extending along the first direction and arranged along the second direction.

[0059] In the present embodiment, since the second shielding strip mainly plays a role of isolating different color sub-pixels, the thickness of the second shielding strip of the present application can be greater than the thickness of the first shielding strip.

[0060] It should be noted that the display panel 100 further includes a support layer (not shown) integrally arranged with the pixel layer 30, the support layer is arranged on the surface of the second pixel definition layer 320 away from the first pixel definition layer 310, and the support layer and the pixel layer 30 can be formed in the same mask process, and the support layer can be used to carry a mask plate.

[0061] It should be noted that the materials of the pixel layer 30 and the support layer can be organic positive photoresist.

[0062] Please refer to Figures 2 to 3 , the light-emitting functional layer 40 can include an anode layer 401 arranged on the second planar layer, a light-emitting layer 402 arranged on the anode layer 401, and a cathode layer 403 arranged on the light-emitting layer 402. The anode layer 401 includes a plurality of anodes corresponding to the pixel openings one by one, and the light-emitting layer 402 can include a plurality of light-emitting parts EL corresponding to the plurality of anodes one by one.

[0063] Please refer to Figures 2 to 3 , the encapsulation layer 50 covers the pixel layer 30 and continuously covers the plurality of pixel openings and the plurality of light-emitting parts EL; the encapsulation layer 50 can include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.

[0064] In the present embodiment, the display panel can further include a color filter layer (not shown) arranged on the encapsulation layer 50 and a cover layer (not shown) arranged on the color filter layer, the color filter layer includes a plurality of color resist and a light shielding unit arranged on both sides of the color resist, and one color resist corresponds to one light-emitting part EL; the cover layer is arranged on the side of the color filter layer away from the substrate 10, and the cover layer can be a glass cover or directly formed on the color filter layer.

[0065] The structure of the array layer 20 in the present application Figure 2 will be described in detail below.

[0066] Referring to Figure 2 The material of the light shielding layer LS can include Cr, W, Ti, Ta, Mo, Al, Cu or other metals, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the light shielding layer LS can be a laminated structure composed of a MoTi layer and a Cu layer.

[0067] In this embodiment, since the device effect of the transistor drifts under the action of light, the light shielding layer LS can be arranged between the transistor and the substrate 10 to shield the active part in the transistor; and the light shielding structure is arranged in the non-display area NA, and external light cannot enter the area where the gate drive circuit is located, so the light shielding layer LS can be located in the display area AA, and the light shielding layer LS does not need to be arranged in the non-display area NA.

[0068] Referring to Figure 2 When the light shielding layer LS is patterned, the light shielding layer LS can form a light shielding part LS1 corresponding to the first transistor T1 and a third plate C3 of the storage capacitor Cst.

[0069] Referring to Figure 2 The buffer layer 201 covers the light shielding layer LS, and the material of the buffer layer 201 can be silicon nitride or silicon oxide, or a laminated structure of the two.

[0070] Referring to Figure 2 The semiconductor layer AS is arranged on the side of the buffer layer 201 away from the substrate 10, and the material of the semiconductor layer AS can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides; for example The material of the semiconductor layer AS in Figure 2 may be IGZO.

[0071] In this embodiment, the semiconductor layer AS includes a first active part AS1 of the first transistor T1 and a second active part AS2 of the second transistor T2, and the materials of the first active part AS1 and the second active part AS2 can be the same, that is, the mobility of the first active part AS1 can be equal to the mobility of the second active part AS2.

[0072] In this embodiment, the surfaces of the first active part AS1 and the second active part AS2 away from the gate layer GE are both in contact with the buffer layer 201.

[0073] In the embodiment, the semiconductor layer AS can further include a fourth electrode plate C4 corresponding to the third electrode plate C3, the fourth electrode plate C4 being in contact with a surface of the buffer layer 201 away from the light shielding layer LS, and the fourth electrode plate C4 being arranged opposite to the third electrode plate C3, and the second electrode plate C2 being a capacitor plate of the storage capacitor Cst.

[0074] Referring to Figure 2 , the first gate insulating layer 202 includes a first sub-portion 202a and a second sub-portion 202b, the first sub-portion 202a being arranged on a side of the first active portion AS1 away from the substrate 10, and the second sub-portion 202b being arranged on a side of the second active portion AS2 away from the substrate 10, and the first gate insulating layer 202 being used to insulate the semiconductor layer AS from an upper conductive layer.

[0075] Referring to Figure 2 , the gate electrode layer GE includes a first gate electrode GE1 of the first transistor T1 and a second gate electrode GE2 of the second transistor T2, the first gate electrode GE1 being arranged on a side of the first sub-portion 202a away from the substrate 10, and the second gate electrode GE2 being arranged on a side of the second sub-portion 202b away from the substrate 10.

[0076] In the embodiment, the material of the gate electrode layer GE can include Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the material of the first electrode layer 120 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0077] In the embodiment, the thickness of the gate electrode layer GE can range from 100 nm to 200 nm, for example, the thickness of the gate electrode layer GE of the present application can be 150 nm.

[0078] Referring to Figure 2 , the interlayer insulating layer 203 is arranged on a side of the gate electrode layer GE away from the substrate 10, the interlayer insulating layer 203 being entirely laid, and the interlayer insulating layer 203 covering the gate insulating layer and being in contact with the buffer layer 201.

[0079] Referring to Figure 2The plurality of conductive portions CD can include a first source T1S and a first drain T1D of the first transistor T1, and a second source T2S and a second drain T2D of the second transistor T2, the first source T1S is connected through a first via hole HL1 and one end of a first active portion AS1, the first drain T1D is connected through a second via hole HL2 and the other end of the first active portion AS1, the second source T2S is connected through a third via hole HL3 and one end of a second active portion AS2, and the second drain T2D is connected through a fourth via hole HL4 and the other end of the second active portion AS2.

[0080] In the embodiment, the first source T1S is also electrically connected through a fifth via hole HL5 and the light shielding portion LS1, so that the light shielding portion LS1 is multiplexed as a bottom gate of the first transistor T1, and the turn-on rate of the first transistor T1 is improved.

[0081] In the embodiment, the first source-drain layer SD1 further includes a first plate C1 of the storage capacitor Cst, and the first plate C1 is oppositely arranged with the fourth plate C4.

[0082] In the embodiment, the material of the first source-drain layer SD1 can include Cr, W, Ti, Ta, Mo, Al, Cu or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the first source-drain layer SD1 can be a laminated structure composed of a MoTi layer and a Cu layer, the thickness of the MoTi layer can range from 10 nm to 30 nm, and the thickness of the Cu layer can range from 400 nm to 600 nm.

[0083] Referring to Figure 2 The passivation layer 204 is arranged on the side of the first source-drain layer SD1 away from the substrate 10, the passivation layer 204 is integrally laid, and the passivation layer 204 covers the first source-drain layer SD1 and is in contact with the interlayer insulation layer 203.

[0084] Referring to Figure 2 The first planar layer 205 is arranged on the side of the passivation layer 204 away from the substrate 10, and the first planar layer 205 covers part of the passivation layer 204.

[0085] In the embodiment, since the thickness of the first source-drain layer SD1 is relatively thick, there is a large step difference between the region where the first source-drain layer SD1 is arranged and the region where the first source-drain layer SD1 is not arranged, and the passivation layer 204 is an inorganic material with poor leveling property, so the flatness of the surface of the passivation layer 204 on the side away from the substrate 10 is poor; and the material of the first planar layer 205 can be an organic material with good leveling property, such as polyimide, thereby improving the flatness of the surface of the film layer.

[0086] Referring to Figure 2 The second source-drain layer SD2 includes a connection electrode CT located in the display area AA and a bus BS located in the non-display area NA, the connection electrode CT is connected with the first source electrode T1S through the sixth via hole HL6, and the bus BS can be connected with the second gate electrode GE2, the second source electrode T2S or the second drain electrode T2D in the second transistor T2 through the seventh via hole HL7.

[0087] In the embodiment, the bus BS can include a high potential line, a low potential line, a data line, a clock signal line and the like signal lines; by arranging the bus BS on the side of the second transistor T2 away from the substrate 10, the application reduces the frame space occupied by the bus BS on the display panel 100, and realizes a narrow frame design.

[0088] In the embodiment, the second source-drain layer SD2 can further include a second plate C2 of the storage capacitor Cst, and the second plate C2 is arranged opposite to the first plate C1.

[0089] In the embodiment, the material of the second source-drain layer SD2 can include Cr, W, Ti, Ta, Mo, Al, Cu and the like metal or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the first source-drain layer SD1 can be a laminated structure composed of a Ti layer, an Al layer and a Ti layer, the thickness of the Ti layer can be 40-60 nm, and the thickness of the Al layer can be 400-600 nm.

[0090] Referring to Figure 2 The second planar layer 206 is arranged on the side of the second source-drain layer SD2 away from the substrate 10, and the material of the second planar layer 206 can be the same as that of the first planar layer 205, for example, the second planar layer 206 and the first planar layer 205 can both be a material with good flow planarity such as polyimide.

[0091] In the embodiment, the material of the second planar layer 206 can be different from that of the first planar layer 205, for example, the photosensitivity of the second planar layer 206 can be greater than that of the first planar layer 205, that is, the photosensitivity of the second planar layer 206 is stronger, and when the second planar layer 206 is exposed, the time of the exposure process can be reduced and the efficiency of the exposure process can be improved.

[0092] Referring to Figure 2The anode layer 401 is disposed on the side of the second planar layer 206 away from the substrate 10, and is connected to the connecting electrode CT through a via. The material of the anode layer 401 can include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0093] In the structure of the display panel 100, the materials of the light shielding layer LS, the semiconductor layer AS, the first source-drain layer SD1 and the second source-drain layer SD2 are used to prepare four-layer capacitor plates, without the need of an additional conductive layer to prepare the capacitor plates, thus simplifying the structure of the storage capacitor Cst and reducing the manufacturing cost of the display panel 100. Meanwhile, the parallel capacitor formed by the four-layer capacitor plates improves the capacitance of the storage capacitor Cst, effectively compensates the threshold voltage of the driving transistor, and improves the display picture of the display panel 100. Figure 2

[0094] It should be noted that although the first planar layer 205 and the second planar layer 206 are both organic materials with leveling property, which can improve the flatness of the film layer, when the step difference is large, the flatness of the film layer cannot be guaranteed even if the first planar layer 205 and the second planar layer 206 are provided. For example, the thickness of the first source-drain layer SD1 is usually 500-800 nm, while the thickness of the gate electrode layer GE is about 150 nm, i.e., the thickness of the gate electrode layer GE is smaller than that of the first source-drain layer SD1, and the corresponding conductive material is not provided in some areas. Therefore, there is a large step difference between the wiring area and the non-wiring area of the display panel 100. Since the first source-drain layer SD1 is thick, the step difference between the area provided with the first source-drain layer SD1 and the area not provided with the first source-drain layer SD1 is large.

[0095] Please refer to Figure 3 The second source-drain layer SD2 further includes a plurality of compensation portions CP arranged in the display area AA, and the plurality of compensation portions CP include a plurality of first compensation blocks CP1 and a plurality of second compensation blocks CP2 arranged at intervals. The orthogonal projection of the first compensation block CP1 on the first source-drain layer SD1 is located between the first source T1S and the first drain T1D, and the orthogonal projection of the second compensation block CP2 on the first source-drain layer SD1 is located on the side of the first drain T1D away from the first drain T1D.

[0096] In the structure of the display panel 100, the materials of the light shielding layer LS, the semiconductor layer AS, the first source-drain layer SD1 and the second source-drain layer SD2 are used to prepare four-layer capacitor plates, without the need of an additional conductive layer to prepare the capacitor plates, thus simplifying the structure of the storage capacitor Cst and reducing the manufacturing cost of the display panel 100. Meanwhile, the parallel capacitor formed by the four-layer capacitor plates improves the capacitance of the storage capacitor Cst, effectively compensates the threshold voltage of the driving transistor, and improves the display picture of the display panel 100. Figure 3 ​In the structure, this application can provide a compensation part CP in a low-touch area, such as a first compensation block CP1 in the area between the first source T1S and the first drain T1D. The orthographic projection of the first compensation block CP1 on the substrate 10 overlaps with the orthographic projection of the first gate on the substrate 10, that is, the first compensation block CP1 can correspond to the first gate GE1 to compensate for the step difference between the first source T1S and the first drain T1D. At the same time, a second compensation block CP2 is provided on the side of the first drain T1D away from the first source T1S. The provision of the first compensation block CP1 and the second compensation block CP2 compensates for the area in the display area AA where no conductive part CD is provided, thereby improving the flatness of the surface of the second planarization layer 206.

[0097] In this embodiment, since the second compensation block CP2 does not cover the corresponding wire, the second electrode plate C2 of this application is connected to the second compensation block CP2, and the orthographic projection of the second compensation block CP2 on the first source-drain layer SD1 is located between the first drain T1D and the first electrode plate C1.

[0098] In this embodiment, since this application is mainly used to ensure the thickness uniformity of the light-emitting part EL, the compensation part CP of this application is mainly used to compensate for the step difference of the film layer in the region corresponding to the light-emitting part EL. Therefore, the orthographic projection of the multiple compensation parts CP of this application on the light-emitting layer 402 can be located in the corresponding light-emitting part EL, so as to improve the flatness of the surface of the second flattening layer 206 corresponding to the light-emitting part EL away from the substrate 10, improve the uniformity of the film layer thickness of the light-emitting layer 402, and improve the lifetime and luminous efficiency of the light-emitting material.

[0099] Please see Figure 1 , Figure 3 For this application Figure 2 The second structural diagram of the mid-section MM. Figure 3 medium structure and Figure 3 The structures in the two are the same or similar, but the differences are:

[0100] Please see Figure 3 The material of the first active part AS1 is different from the material of the second active part AS2, and the mobility of the first active part AS1 is less than the mobility of the second active part AS2.

[0101] In the embodiment, the trend of the narrow frame design of the display panel 100, the reduction of the frame size of the display panel 100, the improvement of the driving current capability of the gate driving circuit to reduce the size of the driving circuit, and the increase of the mobility of the second active part AS2 in the second transistor T2 to improve the driving current capability of the transistor in the gate driving circuit, reduce the frame size of the non-display area NA, and realize the narrow frame design while ensuring the driving stability of the non-display area NA.

[0102] In the embodiment, the material of the first active part AS1 can be IGZO, and the material of the second active part AS2 can be IGZTO, IZO (InZnO), or InIZO.

[0103] In the embodiment, in order to differentiate the mobility of the first active part AS1 and the second active part AS2, the first active part AS1 and the second active part AS2 need to be prepared in two mask processes, and in order to affect the active part in the previous process by the subsequent process, the application can set a protective layer 207 between the two processes.

[0104] Referring to Figure 3 , the protective layer 207 can include a first part 207a located in the display area AA and a second part 207b located in the non-display area NA, the first part 207a is arranged on the surface of the first active part AS1 away from the light shielding layer LS, and the second part 207b is arranged between the second active part AS2 and the buffer layer 201.

[0105] In the embodiment, the protective layer 207 can be laid in an integral layer, or only the second part 207b can be arranged in the non-display area NA. ​ The structure is shown; at the same time, the material of the protective layer 207 can be the same as that of the first gate insulating layer 202.

[0106] The application improves the driving current capability of the transistor in the gate driving circuit by making the mobility of the second active part AS2 greater than that of the first active part AS1, reduces the frame size of the non-display area NA, and realizes the narrow frame design; at the same time, the protective layer 207 can protect the first active part AS1 and avoid the influence of the process of the second active part AS2 on the first active part AS1.

[0107] The application also provides a display device including the display panel. It should be noted that the display device of the application can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0108] The application provides a display panel and a display device; the display panel comprises a substrate, a first source-drain layer and a second source-drain layer arranged on one side of the substrate, the first source-drain layer comprises a plurality of conductive parts arranged at intervals and located in a display area, the second source-drain layer comprises a plurality of compensation parts arranged at intervals and located in the display area, and the orthographic projection of the plurality of compensation parts on the first source-drain layer is arranged non-overlappingly with the plurality of conductive parts; the application forms the plurality of compensation parts arranged at intervals simultaneously when the second source-drain layer is subjected to a patterning process, and the area corresponding to the compensation parts and the plurality of conductive parts in the first source-drain layer is compensated, so that the area of the first source-drain layer without the conductive parts is compensated, the flatness of the planar layer covering the first source-drain layer and the second source-drain layer is improved, and the uniformity of the film layer thickness of the light-emitting layer is improved.

[0109] In the description of the application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0110] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0111] The embodiments, implementation manners and related technical features of the application can be combined or replaced with each other without conflict.

[0112] The above is only a preferred embodiment of the application, and does not limit the application in any form, but any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the application still belongs to the scope of the technical solution of the application.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a non-display area arranged on at least one side of the display area; wherein the display panel comprises: a substrate substrate; a first source-drain layer arranged on one side of the substrate substrate, the first source-drain layer comprising a plurality of conductive parts arranged at intervals and located in the display area; a second source-drain layer arranged on the side of the first source-drain layer away from the substrate substrate, the second source-drain layer comprising a plurality of compensation parts arranged at intervals and located in the display area; wherein the orthographic projection of the plurality of compensation parts on the substrate substrate is non-overlapping with the orthographic projection of the plurality of conductive parts on the substrate substrate.

2. The display panel of claim 1, wherein, At least one first transistor is arranged in the display area, the plurality of conductive parts comprises a first source and a first drain of the first transistor, and the plurality of compensation parts comprises a first compensation block and a second compensation block arranged at intervals; wherein the orthographic projection of the first compensation block on the first source-drain layer is located between the first source and the first drain, and the orthographic projection of the second compensation block on the first source-drain layer is located on the side of the first drain away from the first drain.

3. The display panel of claim 2, wherein, The first source-drain layer further comprises a first plate arranged at intervals with the plurality of conductive parts, the second source-drain layer further comprises a second plate arranged opposite to the first plate, and the first plate and the second plate have an overlapping part; wherein the second plate is connected with the second compensation block, and the orthographic projection of the second compensation block on the first source-drain layer is located between the first drain and the first plate.

4. The display panel of claim 3, wherein, The display panel further comprises: a gate layer arranged between the first source-drain layer and the substrate substrate, the gate layer comprising a first gate of the first transistor; wherein the orthographic projection of the first compensation block on the substrate substrate has an overlapping part with the orthographic projection of the first gate on the substrate substrate.

5. The display panel of claim 4, wherein, The thickness of the gate layer is less than the thickness of the first source-drain layer.

6. The display panel of claim 4, wherein, The display panel further comprises: a light shielding layer arranged between the substrate substrate and the gate layer; a semiconductor layer arranged between the light shielding layer and the gate layer; wherein the light shielding layer comprises a third plate arranged opposite to the first plate, the semiconductor layer comprises a fourth plate arranged opposite to the third plate, and the first plate, the second plate, the third plate and the fourth plate constitute a storage capacitor of the display panel.

7. The display panel of claim 6, wherein, At least one second transistor is arranged in the non-display area; wherein the semiconductor layer comprises a first active part of the first transistor and a second active part of the second transistor, and the mobility of the first active part is less than or equal to the mobility of the second active part.

8. The display panel of claim 7, wherein, The display panel further comprises: a buffer layer arranged between the semiconductor layer and the light shielding layer; a protective layer comprising a first part located in the display area and a second part located in the non-display area, the first part being arranged on the surface of the first active part away from the substrate substrate, and the second part being arranged between the second active part and the buffer layer; wherein the mobility of the first active part is less than the mobility of the second active part.

9. The display panel of any one of claims 1 to 8, wherein, The display panel further comprises: A light-emitting layer is arranged on a side of the second source-drain layer away from the substrate, and the light-emitting layer further comprises a plurality of spaced light-emitting portions. The plurality of compensation portions are orthographically projected on the light-emitting layer within the corresponding light-emitting portions.

10. A display device, characterized by comprising: The display device comprises the display panel according to any one of claims 1 to 9.

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