Semiconductor package

Abstract

A semiconductor package includes a package substrate, an integrated interconnect structure, an optical machine module, and an integrated circuit package. The integrated interconnect structure is bonded over the package substrate and includes an insulator and a plurality of vias extending through the insulator. The optical-mechanical module includes an electronic die, a photonic die, and a waveguide, wherein a portion of the optical-mechanical module is embedded in the integrated interconnect structure. An integrated circuit package is bonded over the integrated interconnect structure and electrically coupled to the opto-mechanical module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor package. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to the continual improvement in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this improvement in integration density has resulted from iterative reductions in the minimum feature size, which allows more components to be integrated into a given area. As the demand for smaller, more creative semiconductor package technologies continues to grow, so does the need for smaller, more creative semiconductor die packaging techniques. One example of such a packaging system is the Package-on-Package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide high-order integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and small footprints on printed circuit boards (PCBs). SUMMARY

[0003] According to some embodiments of the present disclosure, a semiconductor package includes a package substrate, an integrated interconnect structure, an optomechanical module, and an integrated circuit package. The integrated interconnect structure is joined over the package substrate and includes an insulator and a plurality of vias extending through the insulator. The optomechanical module includes an electronic die, a photonic die, and a waveguide, wherein a portion of the optomechanical module is embedded in the integrated interconnect structure. The integrated circuit is joined over the integrated interconnect structure and electrically coupled to the optomechanical module.

[0004] According to some embodiments of the present disclosure, a semiconductor package includes a package substrate, an integrated interconnect structure, an interconnect device, an optomechanical module, and an integrated circuit package. The integrated interconnect structure includes an insulator and a plurality of vias extending through the insulator. The interconnect device is embedded in the integrated interconnect structure. The optomechanical module is joined to the integrated interconnect structure and includes an electronic die, a photonic die, and a waveguide. The integrated circuit package is joined over the integrated interconnect structure and electrically coupled to the optomechanical module via the interconnect device.

[0005] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor package includes the following steps. An embedded device and a plurality of vias are provided over a carrier. An insulator is provided over the carrier to form an integrated interconnect structure, wherein the insulator at least laterally encapsulates the embedded device and the plurality of vias. The carrier is removed. The integrated interconnect structure is joined over a package substrate. A photonic die is joined over the integrated interconnect structure, wherein the photonic die is coupled with the embedded device. An integrated circuit package is joined over the integrated interconnect structure, wherein the integrated circuit package is coupled to the photonic die via the integrated interconnect structure.

[0006] In order to make the above features and advantages of the present disclosure more concrete, embodiments are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is to be noted, however, that the various features illustrated in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity. It should be noted that for ease of understanding, the drawings are sometimes shown with exaggerated or reduced sizes.

[0008] Figures 1 to 10 Cross-sectional views of intermediate stages in the manufacture of a semiconductor package are shown, in accordance with some example embodiments of the present disclosure.

[0009] Figures 11 to 15 Cross-sectional views of intermediate stages in the manufacture of a semiconductor package are shown, in accordance with some example embodiments of the present disclosure.

[0010] Figure 16 A cross-sectional view of a semiconductor package is shown, in accordance with some example embodiments of the present disclosure.

[0011] Figure 17 A top view of a semiconductor package is shown, in accordance with some example embodiments of the present disclosure.

[0012] Figures 18 to 23 Cross-sectional views of intermediate stages in the manufacture of a semiconductor package are shown, in accordance with some example embodiments of the present disclosure.

[0013] Figures 24 to 31 A cross-sectional view of intermediate stages in the manufacture of a semiconductor package is shown, in accordance with some example embodiments of the present disclosure.

[0014] REFERENCE NUMERALS

[0015] 100, 100a: semiconductor package

[0016] 101: first carrier

[0017] 102: second carrier

[0018] 104, 1111, 1162, 1611: dielectric layer

[0019] 105: sawing tool

[0020] 110, 110a, 110b, 110’: integrated interconnect structure

[0021] 111: first redistribution structure

[0022] 112: via

[0023] 113: Interconnect devices

[0024] 114: Fake core

[0025] 115: Insulator

[0026] 116: Second Redistribution Structure

[0027] 120, 120a, 120b: Optomechanical modules

[0028] 122: Electron tube chip

[0029] 124: Photonic Chip

[0030] 125: Heat dissipation components

[0031] 126: Waveguide

[0032] 130: Integrated Circuit Packaging

[0033] 132: Processing the die

[0034] 133: Memory die

[0035] 134: Packaging Material

[0036] 136: Intermediary Layer

[0037] 137: Connector

[0038] 138, 142, 1132, 1241: Conductive connectors

[0039] 140, 400: Packaging substrate

[0040] 141: Undermetal layer of bonding pads and bumps

[0041] 150: Optical devices, optical fibers

[0042] 200: Repair tools

[0043] 1112, 1161: Metallized patterns

[0044] 1131: Through hole

[0045] 1141: Core bonding film

[0046] 1221: Core connector

[0047] 1261: Pin

[0048] 1262: Adhesive film

[0049] OP1: Notch Detailed Implementation

[0050] The following disclosure provides a number of different embodiments or examples for implementing different features of the provided subject matter. Particular examples of elements and arrangements are described below to facilitate the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed directly on each other, and more particularly embodiments in which additional features can be formed between the first and second features such that the first and second features can not be directly in contact. Additionally, the present disclosure can repeat reference numerals and / or letters in various instances. This repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not necessarily indicate a relationship between the various embodiments and / or configurations discussed.

[0051] Moreover, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0052] In the present disclosure, various aspects of semiconductor packages and methods of manufacturing the same are described. According to some embodiments, three-dimensional (3D) packages including optical and electrical devices and methods of forming the same are provided. In particular, waveguide structures can be embedded in an integrated interconnect structure for providing an interface between electrical signals transmitted or received from a processing device and optical signals transmitted or received from a fiber or optical waveguide network. Electronic dies and processing devices (e.g., in an integrated circuit package) are bonded to the integrated interconnect structure, which facilitates electrical signal transmission between the electronic dies and the processing devices. The integrated interconnect structure can be formed from a composite material or a molding compound and can include embedded interconnect devices, where the embedded interconnect devices enable superior high-speed transmission of electrical signals. According to some embodiments, intermediate stages in forming semiconductor packages are shown. Some variations of some embodiments are discussed. In various views and illustrative embodiments, the same reference numbers are used to indicate the same elements.

[0053] Figures 1 to 10 Cross-sectional views of intermediate stages in the manufacture of semiconductor packages according to some example embodiments of the present disclosure are shown. Reference is made to Figure 1In some embodiments, a first carrier 101 is provided and a plurality of vias 112 are provided over the first carrier 101. The first carrier 101 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. In the present embodiment, the first carrier 101 can be in the form of a wafer so that a plurality of packages can be formed simultaneously on the first carrier 101. In some embodiments, a release layer (not shown) can be formed over the first carrier 101. The release layer can be formed of a polymer-based material that can be removed with the first carrier 101 from overlying structures to be formed in subsequent steps. In some embodiments, the release layer is an epoxy-based thermal-release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer can be a UV glue that loses its adhesive properties when exposed to UV light. The release layer can be dispensed as a liquid and cured, can be a laminate film laminated onto the first carrier 101, or the like. The top surface of the release layer can be planar and can have a high degree of planarity.

[0054] According to some embodiments of the present disclosure, a first redistribution structure 111 including a dielectric layer 1111 and a metallization pattern 1112 is formed over the first carrier 101 prior to forming the vias 112. In some embodiments, the dielectric layer 111 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 104 is formed of a nitride, such as silicon nitride, an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 1111 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, or the like, or a combination thereof.

[0055] The metallization pattern 1112 is formed on the dielectric layer 1111. As an example of forming the metallization pattern 1112, a seed layer (not shown) is formed over the dielectric layer 1111. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 1112. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating or the like. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum or the like. The photoresist and the portions of the seed layer on which the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are also removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization pattern 1112.

[0056] As shown, the first redistribution structure 111 includes the dielectric layer 1111 and the metallization pattern 1112. In other embodiments, the first redistribution structure 111 can include any number of dielectric layers, metallization patterns and vias. One or more additional metallization patterns 1112 and dielectric layers can be formed in the first redistribution structure 111 by repeating the processes used to form the metallization pattern 1112 and the dielectric layer 1111. A via can be formed during the formation of the metallization pattern by forming a seed layer and a conductive material of the metallization pattern in an opening of an underlying dielectric layer. Thus, the vias can interconnect and electrically couple various metallization patterns.

[0057] With continued reference to Figure 1A via 112 is formed over the first carrier 101. In embodiments, the via 112 is formed over the first redistribution structure 111. As an example of forming the via 112, a seed layer is formed over the first redistribution structure 111. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed over the seed layer and is patterned. The photoresist can be formed by spin coating, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the via. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, etc. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The photoresist is removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process (e.g., by wet or dry etching). The remaining portions of the seed layer and the conductive material form the via 112.

[0058] In Figure 2 At least one embedded device is provided over the first carrier 101. In some embodiments, the embedded device can be attached to the first redistribution structure 111. In this embodiment, the embedded device includes an interconnect device 113 and a dummy die 114 that is electrically isolated from the interconnect device 113 and the via 112. In other embodiments, the embedded device can include an electronic die, a dummy die, a waveguide, any combination thereof, etc. The embedded device can be placed on the first redistribution structure 111 using, for example, a pick-and-place process. Figure 2 One interconnect device 113 is shown, but in other embodiments, more than one interconnect device 113 can be attached.

[0059] In embodiments where multiple interconnect devices 113 are attached, the interconnect devices 113 can have different sizes (e.g., different heights and / or surface areas) or can have the same size (e.g., the same height and / or surface area). In one embodiment, the interconnect device 113 is an interconnect die that does not have active devices such as transistors and diodes, etc. The interconnect die can or can not have passive devices (e.g., capacitors, transformers, inductors, resistors, etc.). According to alternative embodiments of the present disclosure, the interconnect die includes some active devices and / or passive devices (not shown), and the active devices can be formed at the top surface of a semiconductor substrate. The interconnect device 113 has the function of interconnecting the optomechanical module 120 and the integrated circuit package 130 that are subsequently bonded (as described below).Figure 10 According to some embodiments of the present disclosure, the interconnect device 113 can include a substrate, which can be a semiconductor substrate (e.g., a silicon substrate). The substrate can be further a dielectric substrate formed of a dielectric material such as silicon oxide, silicon nitride, etc. According to some embodiments of the present disclosure, regardless of whether the substrate is formed of a semiconductor or a dielectric material, there is no via hole formed to penetrate the substrate.

[0060] In some embodiments, the interconnect device 113 can include an interconnect structure, which further includes dielectric layers and metal lines and vias 1131 in the dielectric layers. The dielectric layers can include intermetal dielectric (IMD) layers. According to some embodiments of the present disclosure, some of the dielectric layers located at the lower portion are formed of low-k dielectric material. The metal lines and vias 1131 are formed in the dielectric layers. The processes can include single damascene and dual damascene processes. In an exemplary single damascene, a trench is first formed in one of the dielectric layers, and then the trench is filled with a conductive material. A planarization process (e.g., a chemical mechanical polishing (CMP) process) is then performed to remove the excess portion of the conductive material above the top surface of the corresponding dielectric layer, and leave the metal line in the trench. In a dual damascene process, a trench and a via opening are both formed in an IMD layer, with the via opening located below the trench and connected to the trench. The conductive material is then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive material can include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The metal lines and vias 1131 can also include some portions formed in a passivation layer.

[0061] In the present embodiment, as shown in Figure 2 The interconnect device 113 can be oriented with the conductive connections 1132 connecting the metal lines and vias 1131 facing the first carrier 101. Different interconnect devices 113 can be joined above the first carrier 101 in different orientations. In some embodiments, a dummy die 114 can be attached to the first redistribution structure 111 by a die attach film (DAF) 1141, which is an adhesive film. The dummy die 114 can be used to adjust the amount of insulator formed later, thereby reducing the problem of thermal stress and warpage. Throughout the description, the term "dummy die" refers to a die or chip that does not have any electrical functionality, and the dummy die does not contribute to the electrical operation of the resulting package. The dummy die can be formed of a homogeneous material without any electrical circuitry, metal lines, and / or sub-layers.

[0062] In some embodiments, the dummy die 114 can be formed of glass, quartz, blank silicon, etc. The coefficient of thermal expansion (CTE) of the dummy die 114 is lower than the CTE of the insulator 115, which will be formed later on Figure 3molded between the interconnect devices 113 and the dummy die 114. In embodiments of the present disclosure, by placing the dummy die 114 on the first carrier 101 with the interconnect devices 113, the dummy die 114 occupies space that would otherwise be occupied by molding compound (i.e., the insulator 115 shown in FIG. 1C). Since the CTE of the dummy die 114 is less than the CTE of the molding compound, the overall CTE of the layer including the molding compound, the interconnect devices 113, and the dummy die 114 is reduced compared to a layer that does not include the dummy die. Since the CTE of the molding compound is much higher than the CTE of the carrier, the carrier and the molding compound can warp during the manufacturing process, affecting the manufacturing process, sometimes making the process inoperable. Thus, by adding the dummy die 114 to reduce the overall CTE, warpage is reduced. Figure 3

[0063] Thereafter, with reference to Figure 3 , the insulator 115 is provided (formed) over the first carrier 101. After formation, the insulator 115 laterally encapsulates at least the plurality of through vias 112 and the embedded devices (e.g., the interconnect devices 113 and the dummy die 114). The insulator 115 can be a molding compound, an epoxy, etc. The insulator 115 can be applied by compression molding, transfer molding, lamination, etc., and can be formed over the first carrier 101 such that the through vias 112 and / or the embedded devices (e.g., the interconnect devices 113 and the dummy die 114) are buried or covered. The insulator 115 is also formed in interstitial regions between the through vias 112, the interconnect devices 113, and / or the dummy die 114. The insulator 115 can be applied in a liquid or semi-liquid form and then solidified.

[0064] In Figure 4 , a planarization process is performed on the insulator 115 to expose the through vias 112 and the back surfaces of the interconnect devices 113 and the dummy die 114. The through vias 112, the interconnect devices 113, and the dummy die 114 can be coplanar with a ground surface of the insulator 115 after the planarization process. The planarization process can be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, the planarization can be omitted, e.g., if the through vias 112 and / or the back surfaces of the interconnect devices 113 and the dummy die 114 are already exposed. Thus, from a structural perspective, the through vias 112 extend through the insulator 115 after the planarization process.

[0065] In Figure 5 ​In some embodiments, a second redistribution structure 116 is formed. The second redistribution structure 116 includes a metallization pattern 1161 and a dielectric layer 1162. The dielectric layer 1162 can be formed over the insulator 115, the via 112, the interconnect device 113, and the dummy die 114. In some embodiments, the dielectric layer 1162 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 1162 is formed of a nitride, such as silicon nitride, an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or the like. The dielectric layer 1162 can be formed by any acceptable deposition process, such as spin-on, CVD, lamination, or the like, or a combination thereof.

[0066] The metallization pattern 1161 can be formed on / in the dielectric layer 1162. As an example of forming the metallization pattern 1161, a seed layer is formed over the dielectric layer 1162. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed over and patterned on the seed layer. The photoresist can be formed by spin-on or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 1161. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, portions of the photoresist and the seed layer not formed with the conductive material are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization pattern 1161.

[0067] It should be understood that the second redistribution structure 116 can include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes similar to those discussed above can be repeated. The metallization patterns can include wires and conductive vias. The conductive vias can be formed during the formation of the metallization patterns by forming the seed layer and the conductive material of the metallization patterns in openings of the underlying dielectric layer. Thus, the conductive vias can interconnect and electrically couple various wires.

[0068] In some embodiments, the second redistribution structure 116 is formed on the first redistribution structure 115. In some embodiments, the second redistribution structure 116 is formed on the first redistribution structure 115 and the dummy die 114. In some embodiments, the second redistribution structure 116 is formed on the first redistribution structure 115, the dummy die 114, and the interconnect device 113. Figure 5In some embodiments, a plurality of under-bump metallizations (UBMs) 141 and a plurality of conductive connections 142 are formed for external connection to the second redistribution structure 116. The UBM 141 has a bump portion on and extending along a major surface of the dielectric layer 1162, and has a via portion extending through the dielectric layer 1611 to physically and electrically couple the metallization pattern 1161. As such, the UBM 141 is electrically coupled to the via 112 and the interconnect device 113. The UBM 141 can be formed of the same material as the metallization pattern 1161, and can be formed using a similar process (e.g., electroplating). In some embodiments, the UBM 141 has a different size (e.g., width, thickness, etc.) than the metallization pattern 1161.

[0069] According to some embodiments, the conductive connections 142 are then formed on the UBMs 141. The conductive connections 142 can be, for example, ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium immersion gold (ENEPIG) formed bumps, or the like. The conductive connections 142 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive connections 142 are formed via a first formation of a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connections 142 include metal pillars (e.g., copper pillars) formed via sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and can be formed by a plating process.

[0070] Afterwards, the Figure 6 In some embodiments, a de-bonding process is performed to separate (or "de-bond") the first carrier 101 from the overlying structure. According to some embodiments, the de-bonding includes projecting light, such as a laser or UV light, onto the release layer such that the release layer decomposes under the heat of the light and the first carrier 101 can be removed. This structure is then flipped over and attached to the second carrier 102, as shown in FIG. 1C. Figure 6The second carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. An adhesive or release layer (not shown) can be formed on the second carrier 102 to facilitate attachment of the structure. Figure 6

[0071] With continued reference to Figure 6 In some embodiments, the notch OP1 is formed at the outer edge of the insulator 115. In some embodiments, the notch OP1 can be formed via a trimming process by the trimming tool 200. In other embodiments, the notch OP1 can be formed by an etching process, etc. See Figure 7 After that, the waveguide 126 is disposed in the notch OP1. In some embodiments, the waveguide 126 can be attached to the bottom surface of the notch OP1 by an adhesive film 1262 such as a die attach film (DAF). In some embodiments, the waveguide 126 is an optical dielectric waveguide, but is not limited thereto. In some embodiments, the material of the waveguide 126 includes glass (such as spin-on glass (SOG)), silicon, silicon oxide, photoresist, epoxy, optical polymers (such as polymethylmethacrylate, polyurethane, or polyimide), and other suitable optical dielectric materials. In the present embodiment, the waveguide 126 is made of a glass die. In some embodiments, the top surface of the waveguide 126 is coplanar with the top surface of the first redistribution structure 111.

[0072] After that, with reference to Figure 7 and Figure 8 A detachment process is performed to debond the second carrier 102 from the conductive connections 142. According to some embodiments, the debonding includes projecting light such as laser or UV light onto the release layer so that the release layer decomposes under the heat of the light and the second carrier 102 is removable. This structure is then flipped and placed on the tape 104. Then, a singulation process is performed by cutting along the cutting line area using the sawing tool 105. As a result, a plurality of integrated interconnect structures 110 (one is shown here) are formed which are separated from each other.

[0073] Then, with reference to Figure 9 ​According to some embodiments, the integrated interconnect structure 110 is flipped and bonded on top of the package substrate 140. The integrated interconnect structure 110 is mounted to the package substrate 140 using a plurality of conductive connections 142. The package substrate 140 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. can also be used. In addition, the package substrate 400 can be an SOI substrate. In general, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the package substrate 140 is based on an insulating core such as a fiberglass reinforced resin core. An example core material is fiberglass resin such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin or other PCB materials or films. The package substrate 140 can use ABF build up film or other laminated materials.

[0074] The package substrate 140 can include active and passive devices (not shown). Those of ordinary skill in the art will recognize that a variety of devices such as transistors, capacitors, resistors, combinations thereof, etc. can be used to create the structural and functional requirements of a semiconductor package design. The devices can be formed using any suitable method.

[0075] The package substrate 140 can further include metallization layers and vias (not shown) and bond pads 141 above the metallization layers and vias. The metallization layers can be formed above the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layers can be formed of alternating dielectric layers (e.g., low-k dielectric material) and conductive layers (e.g., copper) with vias interconnecting the conductive layers and can be formed by any suitable process such as deposition, damascene, dual damascene, or the like. In some embodiments, the package substrate 140 is substantially free of active and passive devices.

[0076] In some embodiments, the conductive connections 142 can be reflowed to attach the integrated interconnect structure 110 to the bond pads 141. The conductive connections 142 electrically and / or physically couple the package substrate 140 (including the metallization layers in the package substrate 140) to the integrated interconnect structure 110.

[0077] The conductive connections 142 can have epoxy flux (not shown) formed thereon prior to reflow soldering, and at least some of the epoxy flux remains as an epoxy residue after the integrated interconnect structure 110 is attached to the package substrate 140. This remaining epoxy residue can act as an underfill to reduce stress and protect joints created by reflow soldering the conductive connections 142. In some embodiments, an underfill (not shown) can be formed between the integrated interconnect structure 110 and the package substrate 140 and around the conductive connections 142. The underfill can be formed by a capillary flow process after the package substrate 140 is attached, or can be formed by a suitable deposition method prior to the integrated interconnect structure 110 being attached.

[0078] Then, referring to Figure 10 , the electronic die 122 and the photonic die 124 are bonded to the integrated interconnect structure 110 and coupled to the embedded devices (e.g., the interconnect device 113 and the waveguide 126). In one implementation, the electronic die 122 is bonded to the integrated interconnect structure 110, and the photonic die 124 is stacked over the electronic die 122 and the waveguide 126 and bonded to the electronic die 122 and the waveguide 126. The bonding between the electronic die 122 and the photonic die 124 can include, for example, hybrid bonding, fusion bonding, direct bonding, dielectric bonding, metal bonding, solder joints (e.g., micro-bumps), etc. The electronic die 122, the photonic die 124, and the waveguide 126 can be considered as an optomechanical module 120. Further, an integrated circuit package 130 is bonded over the integrated interconnect structure 110 and electrically coupled to the optomechanical module 120. In some embodiments, the optomechanical module 120 is configured to receive optical signals from an optical device (e.g., an optical fiber 150 as shown) through pins 1261 of the waveguide 126. The photonic die 124 is optically coupled to the optical device 150 through the waveguide 126. In some embodiments, a portion of the optomechanical module 120 is embedded in the integrated interconnect structure 110. For example, in the present embodiment, the waveguide 126 is embedded in the integrated interconnect structure 110. In some embodiments, a heat dissipation device 125, such as a heatsink, can be disposed on the photonic die 124 of the optomechanical module 120 to facilitate heat dissipation. In some embodiments, the integrated interconnect structure 110 can be an interposer. That is, the integrated interconnect structure 110 can be an integrated interposer structure. Figure 16

[0079] ​Generally, photodetectors of the photonic die 124 are used to detect optical signals. Electronic dies 122 in the optomechanics module 120 can then generate corresponding electrical signals based on the optical signals. These electrical signals can then be transmitted through the interconnect devices 113 of the integrated interconnect structure 110 to the processing die 132 in the integrated circuit package 130. The processing die 132 can then process the electrical signals or provide other appropriate computing functions. In some embodiments, the processing die 132 generates electrical signals that can be transmitted through the interconnect devices 113 of the integrated interconnect structure 110 to the electronic dies 122 of the optomechanics module 120. The electronic dies 122 can then use modulators to generate optical signals and couple these optical signals through the waveguides 126 to the optical fiber 150. In some embodiments, the processing die 132 controls the electronic dies 122 of the optomechanics module 120. In this way, the optomechanics module 120 can be considered a“light input / output (I / O) module” of the semiconductor package 100.

[0080] In Figure 10 In some embodiments, the electronic dies 122 are bonded to the first redistribution structure 111 of the integrated interconnect structure 110. The electronic dies 122 can be, for example, semiconductor devices, dies, or chips that communicate with the photonic die 124 using electrical signals. Figure 10 One electronic die 122 is shown in FIG. 1, but in other embodiments the optomechanics module 120 can include two or more electronic dies 122. The electronic die 122 includes a die connection 1221, which can be, for example, a conductive pad, a conductive pillar, or the like.

[0081] The electronic die 122 can include integrated circuitry for interfacing with the photonic die 124, such as circuitry for controlling the operation of the photonic die 124. For example, the electronic die 122 can include a controller, a driver, a transimpedance amplifier, or the like, or combinations thereof. In some embodiments, the electronic die 122 can further include a CPU. In some embodiments, the electronic die 122 includes circuitry for processing electrical signals received from the photonic die 124, such as circuitry for processing electrical signals received from photodetectors of the photonic die 124. The electronic die 122 can control the high-frequency signals of the photonic die 124 according to electrical signals (digital or analog) received from another device, such as from the processing die 132 of the integrated circuit package. In some embodiments, the electronic die 122 can be an electronic integrated circuit (EIC) that provides serializer / deserializer (SerDes) functionality, or the like. In this way, the electronic die 122 can act as part of an I / O interface between optical signals and electrical signals within the semiconductor package 100.

[0082] In some embodiments, electronic die 122 can be bonded to first redistribution structure 111 by die connectors 1221. In some embodiments, electronic die 122 can be bonded by dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, or the like). In such embodiments, covalent bonds can be formed between oxide layers, such as the topmost dielectric layer of electronic die 122 and the surface dielectric layer (not shown) of first redistribution structure 111. During bonding, metal bonding can also occur between die connectors 1221 of electronic die 122 and conductive pads of first redistribution structure 111. The use of dielectric-to-dielectric bonding can allow for deposition of materials that are transparent to the relevant wavelengths of light over first redistribution structure 111 and / or around electronic die 122, rather than opaque materials such as encapsulants or mold compounds. For example, the dielectric material can be formed of a suitable transparent material (e.g., silicon oxide) rather than an opaque material (e.g., a mold compound). The use of a suitably transparent material as a dielectric material in this manner allows for the transmission of optical signals through the dielectric material, such as between the optical couplers of waveguides 126 and the optical fibers coupled to waveguides 126. Additionally, bonding electronic die 122 to first redistribution structure 111 in this manner can reduce the thickness of resulting semiconductor package 100, and can improve optical coupling between waveguides 126 and optical fibers (e.g., Figure 16 The semiconductor package 100 shown can be considered a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device in some embodiments. In some embodiments, the semiconductor package 100 can be considered a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device.

[0083] In Figure 10 In some embodiments, semiconductor package 100 can be considered a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device. In some embodiments, semiconductor package 100 can be considered a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device.

[0084] The interconnect device 113 provides electrical connections between multiple devices attached to the integrated interconnect structure 110 in the semiconductor package 100, such as between the optomechanical module 120 and the integrated circuit package 130 including at least one processing die 132 and / or at least one memory die 133. In some embodiments, the interconnect device 113 can include through-substrate vias (TSVs) to make electrical connections between conductive features on opposite sides of the interconnect device 113. The TSVs of the interconnect device 113 are optional, and can not be present in some embodiments. The interconnect device 113 can be formed using applicable manufacturing processes. The interconnect device 113 can not contain active devices and / or can not contain passive devices.

[0085] Figure 10 The integrated circuit package 130 shown in FIG. 1 includes two processing dies 132 and one memory die 133, but in other embodiments, the integrated circuit package 130 can include more or fewer devices of different types and / or combinations of devices. The processing dies 132 can include, for example, central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), high-performance computing (HPC) dies, or the like or combinations thereof. The memory die 133 can include, for example, volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), another type of memory, or the like. In such embodiments, processing and memory functions can be integrated within the same die. The processing dies 132 and memory die 133 shown are example elements, and the integrated circuit package 130 can include one or more semiconductor devices, chips, dies, system-on-chip (SoC) devices, system-on-integrated-circuit (SoIC) devices, or the like or combinations thereof. The processing dies 132 and memory die 133 can have different arrangements than shown in other embodiments. These and other configurations are considered to be within the scope of the present disclosure.

[0086] In some embodiments, the integrated circuit package 130 further includes an interposer 136 and an encapsulation material 134. The processing die 132 and the memory die 133 are bonded on the interposer 136, and the encapsulation material 134 laterally encapsulates the processing die 132 and the memory die 133. An underfill layer (not shown) can be formed under and around the processing die 132 and the memory die 133 to encapsulate conductive connections for bonding the processing die 132 and the memory die 133 to the interposer 136. The underfill layer can be formed of an epoxy-based polymeric material. The encapsulation material 134 can be formed over the interposer 136 to at least laterally encapsulate the processing die 132 and the memory die 133. The encapsulation material 134 can be formed of an epoxy molding compound (EMC).

[0087] The integrated interconnect structure 110 electrically connects the optomechanical module 120 and the integrated circuit package 130 and allows transmission of electrical signals between the optomechanical module 120, the processing die 132, and / or the memory die 133. In some embodiments, the optomechanical module 120 and the integrated circuit package 130 are electrically connected to each other through the integrated interconnect structure 110 via interconnect devices 113. For example, the interconnect devices 113 can conduct electrical signals between the processing die 132 and the optomechanical module 120. Using the interconnect devices 113 in this manner can improve high-speed communication between the optomechanical module 120 and the integrated circuit package 130. For example, the interconnect devices 113 can have a finer pitch of conductive wiring than the conductive wiring of the integrated interconnect structure 110 or the conductive wiring of the package substrate 140, which allows superior high-speed transmission of electrical signals. The interconnect devices 113 can also be closer to the optomechanical module 120 and the integrated circuit package 130 than the package substrate 140, thereby shortening the wiring distance and reducing noise, improving high-speed performance, and reducing power consumption. Multiple interconnect devices 113 can be used in any suitable configuration within the integrated interconnect structure 110 of the semiconductor package 100, thereby allowing flexible design and forming larger-sized semiconductor packages 100.

[0088] Figures 11 to 15 A cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some example embodiments of the disclosure is shown. Figures 1 to 10 The process shown is only one of the possible methods of forming the semiconductor package 100. Figures 11 to 15 Another embodiment of manufacturing a semiconductor package is shown. Notably, Figures 11 to 15 The manufacturing method of the semiconductor package shown includes many features that are the same or similar to the previously Figures 1 to 10 The disclosed semiconductor package includes many features that are the same or similar to the previously

[0089] It is noted that,Figures 11 to 15 The steps shown are performed after Figure 5 The steps shown are performed after Figure 5 and Figure 11 After forming the plurality of UBMs 141 and the plurality of conductive connections 142 over the second redistribution structure 116 as shown, the resulting structure is flipped and placed on a tape 104 as shown. The tape 104 herein can be a dicing tape 104 as shown. Then, a notch OP1 is formed on the outer edge of the insulator 115. In some embodiments, the notch OP1 can be formed via a trimming process using a trimming tool 200. In other embodiments, the notch OP1 can be formed by an etching process or the like. Figure 5 Figure 11 The steps shown are performed after Figure 8 The steps shown are performed after

[0090] Referring to Figure 12 Then, a singulation process is performed by cutting along the dicing line area using a sawing tool 105. Thereby, a plurality of integrated interconnect structures 110’ as shown is formed. The notch OP1 extends towards the outermost edge of the integrated interconnect structure 110’. Figure 12

[0091] Then, referring to Figure 13 According to some embodiments, after the singulation process, the integrated interconnect structure 110’ is flipped and bonded over a packaging substrate 140. The integrated interconnect structure 110’ is mounted to the packaging substrate 140 using the plurality of conductive connections 142. The packaging substrate 140 can be the same as or similar to the packaging substrate 140 as shown and can be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, a compound material such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, a combination of these, or the like can be used. Additionally, the packaging substrate 400 can be an SOI substrate. Generally, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the packaging substrate 400 is based on an insulating core (e.g., a fiberglass reinforced resin core). An example core material is fiberglass resin such as FR4. Alternatives to the core material include bismaleimide triazine (BT) resin or other PCB materials or films. The packaging substrate 140 can use an ABF or other build-up film or other laminated material. Figure 10

[0092] ​​​​The package substrate 140 can include active and passive devices (not shown). Those of ordinary skill in the art will recognize that a variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to create the structural and functional requirements of a semiconductor package design. The devices can be formed using any appropriate method. In some embodiments, the conductive connections 142 can be reflowed to connect the integrated interconnect structure 110 to the bond pads 141. The conductive connections 142 electrically and / or physically couple the package substrate 140 (including the metallization layers in the package substrate 140) to the integrated interconnect structure 110.

[0093] Referring then to Figure 14 , the waveguide 126 is disposed in the notch OP1. In some embodiments, the waveguide 126 can be attached to the bottom surface of the notch OP1 by an adhesive film 1262 such as a die attach film (DAF). In some embodiments, the waveguide 126 includes an optical dielectric waveguide, but is not limited thereto. In some embodiments, the material of the waveguide 126 includes glass such as spin-on glass (SOG), silicon, silicon oxide, photoresist, epoxy, optical polymers such as polymethyl methacrylate, polyurethane, or polyimide, and other suitable optical dielectric materials. In the present embodiment, the waveguide 126 is made of a glass tube. In some embodiments, the top surface of the waveguide 126 is coplanar with the top surface of the first redistribution structure 111.

[0094] Referring then to Figure 15 , the electronic die 122 and the photonic die 124 are bonded over the integrated interconnect structure 110 and coupled to the embedded devices (e.g., the interconnect devices 113 and the waveguide 126) embedded in the integrated interconnect structure 110. In one implementation, the electronic die 122 is bonded to the integrated interconnect structure 110, and the photonic die 124 is stacked over and bonded to the electronic die 122 and the waveguide 126. The electronic die 122, the photonic die 124, and the waveguide 126 can be considered as an optomechanical module 120. In addition, an integrated circuit package 130 is bonded over the integrated interconnect structure 110 and electrically coupled to the optomechanical module 120. In some embodiments, the optomechanical module 120 is configured to receive optical signals from an optical device (e.g., an optical fiber 150 as shown) through a pin 1261 of the waveguide 126. The photonic die 124 is optically coupled to the optical device 150 through the waveguide 126. Figure 16

[0095] ​Generally, photodetectors of the photonic die 124 are used to detect optical signals. Then, the electronic die 122 in the optomechanical module 120 can generate corresponding electrical signals based on the optical signals. These electrical signals can then be transmitted through the interconnection devices 113 of the integrated interconnection structure 110 to the processing die 132 in the integrated circuit package 130. The processing die 132 can then process the electrical signals or provide other appropriate computing functions. In some embodiments, the processing die 132 generates electrical signals that can be transmitted through the interconnection devices 113 of the integrated interconnection structure 110 to the electronic die 122 of the optomechanical module 120. The electronic die 122 can then use the modulator to generate optical signals and couple these optical signals through the waveguide 126 to the optical fiber 150. In some embodiments, the processing die 132 controls the electronic die 122 or the optomechanical module 120. In this way, the optomechanical module 120 can be considered as a "light input / output (I / O) module" of the semiconductor package 100. Optical power can be provided to the waveguide 126 through the optical fiber 150 (see Figure 16 and Figure 17 ) coupled to an external light source, for example, or the optical power can be generated by photonic elements (e.g., laser diodes) within the semiconductor package 100.

[0096] Figure 16 A cross-sectional view of a semiconductor package is shown in accordance with some example embodiments of the present disclosure. Figure 17 A top view of a semiconductor package is shown in accordance with some example embodiments of the present disclosure. Referring to Figure 16 In some embodiments, at least one set of optical fibers 150 can be coupled to the waveguide 126 or the optomechanical module 120 through, for example, optical glue and / or guide pins 1261 of the waveguide 126. For illustrative purposes, a plurality of optical fibers 150 is shown in Figure 16 and Figure 17 In the present embodiment, the optical fibers 150 can be edge mounted optical fibers 150. However, in other embodiments, the optical fibers 150 can also include vertically mounted optical fibers or a combination thereof.

[0097] Referring to Figure 17In some embodiments, multiple optomechanical modules 120 surrounding integrated circuit package 130 are attached to integrated interconnect structure 110. Optomechanical modules 120 can be electrically connected to processing die 132 and / or memory die 133 via interconnect devices 113 embedded within integrated interconnect structure 110. From a top view, interconnect devices 113 can overlap with elements connected by interconnect devices 113. For example, from a top view, interconnect devices 113 can overlap with optomechanical modules 120 and integrated circuit package 130. More specifically, from a top view, interconnect devices 113 can overlap and / or interconnect with any two or more elements, such as optomechanical modules 120, processing die 132, and / or memory die 133. Interconnect devices 113 provide high speed connections between elements of a semiconductor package, which can improve high speed performance of the semiconductor package.

[0098] Figures 18 to 23 A cross-sectional view of an intermediate stage in the manufacture of a semiconductor package is shown, in accordance with some example embodiments of the present disclosure. Notably, Figures 18 to 23 The illustrated method of manufacturing a semiconductor package includes many features that are the same or similar to those previously Figures 1 to 10 described. For the purposes of clarity and simplicity, detailed descriptions of the same or similar features can be omitted, and the same or similar reference numbers indicate the same or similar elements. In Figures 18 to 23 In the illustrated embodiments, optomechanical modules containing electronic dies, photonic dies, and waveguides can be integrated into one module and mounted together on an integrated interconnect structure.

[0099] Reference is made to Figure 18 In some embodiments, a plurality of vias 112 and at least one embedded device are provided over a first carrier 101. The first carrier 101 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. In the present embodiment, the first carrier 101 can be in the form of a wafer, and thus multiple packages can be formed simultaneously on the first carrier 101. In some embodiments, a release layer (not shown) can be formed over the first carrier 101. The release layer can be removed with the first carrier 101 from a cover structure to be formed in a subsequent step. The release layer can be dispensed in a liquid form and cured, can be a lamination film laminated onto the first carrier 101, or the like. A top surface of the release layer can be planar and can have a high degree of planarity.

[0100] According to some embodiments of the disclosure, the first redistribution structure 111 is formed prior to providing the via 112 and the embedded device over the first carrier 101. In some embodiments, the via 112 is formed over the first redistribution structure 111. As an example of forming the via 112, a seed layer is formed over the first redistribution structure 111. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed over the seed layer and is patterned. The photoresist can be formed by spin coating, and can be exposed to light for patterning. The pattern of the photoresist corresponds to a via. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, etc. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The photoresist is removed, and the portions of the seed layer over which the conductive material is not formed, by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process (e.g., by wet or dry etching). The remaining portions of the seed layer and the conductive material form the via 112.

[0101] In some embodiments, the embedded device can be attached to the first redistribution structure 111. In this embodiment, the embedded device includes an interconnect device 113 and at least one dummy die 114 that is electrically isolated from the interconnect device 113 and the via 112. The embedded device can be placed on the first redistribution structure 111 using, for example, a pick-and-place process. Figure 18 One interconnect device 113 and two dummy dies 114 are shown, but in other embodiments, more than one interconnect device 113 can be attached. In one embodiment, the interconnect device 113 is an interconnect die that does not have active devices such as transistors and diodes. The interconnect die can or can not have passive devices (e.g., capacitors, transformers, inductors, resistors, etc.). According to alternative embodiments of the disclosure, the interconnect die includes some active devices and / or passive devices (not shown), and the active devices can be formed at the top surface of a semiconductor substrate. The interconnect device 113 has the function of interconnecting the optomechanical module 120 and the integrated circuit package 130 that are subsequently bonded (as shown). Figure 23

[0102] In this embodiment, the interconnect device 113 can be as described in U.S. Patent Application No. 16 / 209, 1 13, filed December 3, 2018, entitled "INTERCONNECT DEVICE FOR AN OPTOMECHANICAL MODULE," which is incorporated by reference in its entirety. Figure 18 ​The dummy dies 114 can be attached to the first redistribution structure 111 by a die attach film (DAF) 1141, which is an adhesive film. The dummy dies 114 can be disposed at any spacing between the vias 112 and serve to adjust the amount of insulator formed later to reduce thermal stress and warpage issues.

[0103] Then, referring to Figure 19 An insulator 115 is disposed (formed) over the first carrier 101. After formation, the insulator 115 laterally encapsulates at least the plurality of vias 112 and the embedded devices (e.g., the interconnect devices 113 and the dummy dies 114). The insulator 115 can be a molding compound, an epoxy, etc. The insulator 115 can be applied by compression molding, transfer molding, lamination, etc., and can be formed over the first carrier 101 such that the vias 112 and / or the embedded devices (e.g., the interconnect devices 113 and the dummy dies 114) are buried or covered. The insulator 115 can be applied in a liquid or semi-liquid form and then solidified.

[0104] The insulator 115 is then subjected to a planarization process to expose the vias 112 and the back surfaces of the interconnect devices 113 and the dummy dies 114. The vias 112, the interconnect devices 113, and the back surfaces of the dummy dies 114 can be coplanar with a ground surface of the insulator 115 after the planarization process. The planarization process can be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, the planarization can be omitted, e.g., if the vias 112 and / or the back surfaces of the interconnect devices 113 and the dummy dies 114 are already exposed. Thus, from a structural perspective, the vias 112 extend through the insulator 115 after the planarization process.

[0105] Referring to Figure 20 A second redistribution structure 116 is formed. It should be understood that the second redistribution structure 116 can include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes similar to those discussed above can be repeated. The metallization patterns can include wires and conductive vias. The conductive vias can be formed during formation of the metallization patterns by forming a seed layer and conductive material in openings of an underlying dielectric layer. Thus, the conductive vias can interconnect and electrically couple various wires.

[0106] In Figure 20In some embodiments, a plurality of under bump metal (UBM) 141 and a plurality of conductive connections 142 are formed for external connection to the second redistribution structure 116. As a result, the UBM 141 is electrically coupled to the via 112 and the interconnect device 113. According to some embodiments, the conductive connections 142 are then formed on the UBM 141. The conductive connections 142 can be, for example, ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium immersion gold (ENEPIG) formed bumps, or the like. The conductive connections 142 can comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connections 142 are formed by first forming a solder layer via evaporation, plating, printing, solder transfer, ball placement, or the like. Once the solder layer is formed on the structure, reflow soldering can be performed in order to shape the material into the desired bump shape. In another embodiment, the conductive connections 142 comprise metal pillars (e.g., copper pillars) formed via sputtering, printing, plating, electroless plating, CVD, or the like. The metal pillars can be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer can comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and can be formed by a plating process.

[0107] Then, referring to Figure 20 and Figure 21 a singulation process is performed to debond the first carrier 101 from the conductive connections 142. The structure is then flipped and placed on the tape 104. Then, a monolithic process is performed by cutting along the scribe regions using a sawing tool 105. As a result, a plurality of integrated interconnect structures 110a (one is shown here) are formed that are separated from each other.

[0108] Then, referring to Figure 22According to some embodiments, the integrated interconnect structure 110 is flipped and bonded to the packaging substrate 140. The integrated interconnect structure 110 is mounted to the packaging substrate 140 using a plurality of conductive connectors 142. The packaging substrate 140 may be made of semiconductor materials such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof may be used. Additionally, the packaging substrate 400 may be an SOI substrate. Generally, an SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the packaging substrate 400 is based on an insulating core (e.g., a glass fiber reinforced resin core). An exemplary core material is glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide triazine (BT) resin or other PCB materials or films. The packaging substrate 140 may use multilayer films such as ABF or other laminated materials. In some embodiments, the conductive connector 142 may be reflow soldered to connect the integrated interconnect structure 110a to the bonding pad 141.

[0109] Then, refer to Figure 23 An optomechanical module 120a, comprising an electron die 122, a photonic die 124, and a waveguide 126, is disposed and bonded above an integrated interconnect structure 110a and coupled to an interconnect device 113. In one embodiment, the waveguide 126 and the electron die 122 are bonded to the upper surface of the integrated interconnect structure 110a, and the photonic die 124 is stacked above the electron die 122 and the waveguide 126 and coupled to the electron die 122 and the waveguide 126. Additionally, an integrated circuit package 130 is bonded above the integrated interconnect structure 110a and electrically coupled to the optomechanical module 120a. In some embodiments, the optomechanical module 120a is configured to receive signals from an optical device (e.g., an optical component) via pins 1261 of the waveguide 126. Figure 16 The optical fiber 150 shown receives the optical signal. The photonic chip 124 is optically coupled to the optical device 150 via waveguide 126. The dummy chip 114 can be located below the waveguide of the optomechanical module 120a and the integrated circuit package 130. Thus, Figure 23 The manufacturing process of the semiconductor package 100a shown is basically complete.

[0110] Figures 24 to 31 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some exemplary embodiments of the present disclosure. It is worth noting that... Figures 24 to 31 The semiconductor package manufacturing method shown includes many features similar to those previously described. Figures 1 to 10 The disclosed embodiments feature the same or similar characteristics. For clarity and simplicity, detailed descriptions of the same or similar characteristics may be omitted, and the same or similar reference numerals denote the same or similar elements. Figures 24 to 31In the illustrated embodiment, the dummy die, electronic die, and waveguide are embedded in an integrated interposer structure.

[0111] Referring to Figure 24 In some embodiments, a plurality of vias 112 and at least one embedded device are provided over a first carrier 101. The first carrier 101 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. In the present embodiment, the first carrier 101 can be in the form of a wafer so that a plurality of packages can be formed simultaneously on the first carrier 101. In some embodiments, a release layer (not shown) can be formed over the first carrier 101. The release layer can be removed with the first carrier 101 from the overlying structure to be formed in subsequent steps. The release layer can be dispensed as a liquid and cured, can be a lamination film laminated onto the first carrier 101, or the like. The top surface of the release layer can be planar and can have a high degree of planarity.

[0112] According to some embodiments of the present disclosure, a first redistribution structure 111 is formed prior to providing the vias 112 and the embedded devices over the first carrier 101. In some embodiments, the vias 112 are formed over the first redistribution structure 111. The formation of the vias can be the same as or similar to the formation of the vias in the aforementioned embodiments. In some embodiments, a plurality of embedded devices are attached to the first redistribution structure 111. In the present embodiment, the embedded devices include an electronic die 122, an optical engine module, and at least one dummy die 114 for reducing warpage of the package. The embedded devices can be placed on the first redistribution structure 111 using, for example, a pick-and-place process. Figure 24 One electronic die 122 and one dummy die 114 are shown, but in other embodiments, more than one electronic die 122 and more than one dummy die 114 can be attached.

[0113] In the present embodiment, the electronic die 122 can be oriented with the conductive connections 1221 facing the first carrier 101, as shown. In some embodiments, the dummy die 114 can be attached to the first redistribution structure 111 by a die attach film (DAF) 1141, which is an adhesive film. The dummy die 114 can be disposed in any suitable space and configured to adjust the amount of insulator to be formed subsequently to reduce thermal stress and warpage issues. Figure 24

[0114] Referring to Figure 25 ​In some embodiments, an insulator 115 is disposed (formed) over the first carrier 101. After formation, the insulator 115 laterally encapsulates at least the plurality of vias 112, the electronic die 113, and the dummy die 114. The insulator 115 can be a molding compound, an epoxy, etc. The insulator 115 can be applied by compression molding, transfer molding, lamination, etc., and can be formed over the first carrier 101 such that the vias 112 and / or embedded devices (e.g., the interconnect device 113, the electronic die 113, and the dummy die 114) are buried or covered. The insulator 115 can be applied in a liquid or semi-liquid form and then solidified.

[0115] The insulator 115 is then subjected to a planarization process to expose the vias 112 and the back surfaces of the electronic die 113 and the dummy die 114. After the planarization process, the vias 112, the back surfaces of the electronic die 113 and the dummy die 114 can be coplanar with an upper surface of the insulator 115. The planarization process can be, for example, chemical mechanical polishing (CMP), a lapping process, etc. In some embodiments, the planarization can be omitted, e.g., if the vias 112 and / or the back surfaces of the electronic die 113 and the dummy die 114 are already exposed. Thus, from a structural perspective, the vias 112 extend through the insulator 115 after the planarization process.

[0116] Referring to Figure 26 , a second redistribution structure 116 is formed. It should be understood that the second redistribution structure 116 can include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes similar to those discussed above can be repeated. The metallization patterns can include conductive lines and conductive vias. The conductive vias can be formed during formation of the metallization patterns by forming a seed layer and conductive material in openings of an underlying dielectric layer. Thus, the conductive vias can interconnect and electrically couple various conductive lines.

[0117] In Figure 26In some embodiments, a plurality of under bump metal layers (UBMs) 141 and a plurality of conductive connections 142 are formed for external connection to the second redistribution structure 116. As a result, the UBM 141 is electrically coupled to the via 112 and the electronic die 122. According to some embodiments, the conductive connections 142 are then formed on the UBM 141. The conductive connections 142 can be, for example, ball grid array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG) technology, or the like. The conductive connections 142 can comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connections 142 are formed by first forming a layer of solder via evaporation, plating, printing, solder transfer, ball placement, or the like. Once the layer of solder is formed on the structure, reflow soldering can be performed in order to shape the material into the desired bump shape. In another embodiment, the conductive connections 142 comprise metal pillars (e.g., copper pillars) formed via sputtering, printing, plating, electroless plating, CVD, or the like. The metal pillars can be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer can comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and can be formed by a plating process.

[0118] Then, with reference to Figure 26 and Figure 27 a de-bonding process is performed to de-bond the first carrier 101 from the conductive connections 142. The structure is then flipped and placed on the second carrier 102. With reference to Figure 27 In some embodiments, a notch OP1 is formed at the outer edge of the insulator 115. The notch is formed next to the electronic die 122. In some embodiments, the notch OP1 can be formed by a trimming process using a trimming tool 200. In other embodiments, the notch OP1 can be formed by an etching process or the like. With reference to Figure 28 The waveguide 126 is then disposed in the notch OP1. As a result, the waveguide 126 is embedded in the integrated interconnect structure next to the electronic die 122. In some embodiments, the waveguide 126 can be attached to the bottom surface of the notch OP1 by an adhesive film 1262 such as a die attach film (DAF). In some embodiments, the waveguide 126 is an optical dielectric waveguide, but is not limited thereto. In some embodiments, the material of the waveguide 126 comprises glass such as spin-on glass (SOG), silicon, silicon oxide, photoresist, epoxy, optical polymers such as polymethyl methacrylate, polyurethane, or polyimide, and other suitable optical dielectric materials. In the present embodiment, the waveguide 126 is made of a glass tube. In some embodiments, the top surface of the waveguide 126 is coplanar with the top surface of the first redistribution structure 111.

[0119] Then, referring to Figure 28 and Figure 29 , a singulation process is performed to separate (de-bond) the second carrier 102 from the conductive connections 142. According to some embodiments, the de-bonding includes projecting light, such as a laser or UV light, onto the release layer such that the release layer decomposes under the heat of the light and the second carrier 102 can be removed. The structure is then flipped over and placed on a tape 104. Then, a singulation process is performed by cutting along the cut line areas using a sawing tool 105. As a result, a plurality of integrated interconnect structures 110b (one is shown here) are formed that are separated from each other. The integrated interconnect structure 110b in this embodiment is embedded with the optical engine module, the electronic die 122 of the dummy die 114, and the waveguide.

[0120] Then, referring to Figure 30 , according to some embodiments, the integrated interconnect structure 110b is flipped over and bonded on a package substrate 140. The integrated interconnect structure 110b is mounted to the package substrate 140 using a plurality of conductive connections 142. The package substrate 140 can be made of a semiconductor material of silicon, germanium, diamond, etc. Alternatively, a compound material of silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon carbide germanium, phosphide gallium arsenide, gallium indium phosphide, a combination of these, etc. can also be used. In addition, the package substrate 140 can be an SOI substrate. In general, an SOI substrate includes a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the package substrate 400 is based on an insulating core (e.g., a fiberglass reinforced resin core). An example core material is fiberglass resin, such as FR4. Alternatives to the core material include a bismaleimide triazine (BT) resin or other PCB material or film. The package substrate 140 can use an ABF build-up film or other laminated material. The package substrate 140 can include active and passive devices (not shown).

[0121] One of ordinary skill in the art will recognize that a variety of devices, such as transistors, capacitors, resistors, combinations thereof, etc. can be used to produce the structural and functional requirements of the semiconductor package design. The devices can be formed using any suitable method. In some embodiments, the conductive connections 142 can be reflowed to attach the integrated interconnect structure 110b to the package substrate 140. The conductive connections 142 electrically and / or physically couple the package substrate 140 (including the metallization layer in the package substrate 140) to the integrated interconnect structure 110b. In some embodiments, an underfill (not shown) can be formed between the integrated interconnect structure 110b and the package substrate 140 and around the conductive connections 142. The underfill can be formed by a capillary flow process after the package substrate 140 is attached, or can be formed by a suitable deposition method before the integrated interconnect structure 110b is attached.

[0122] Then, refer to Figure 31 A photonic die 124 is bonded over an integrated interconnect structure 110b. Specifically, the photonic die 124 is stacked and coupled over and to an electronic die 122 and a waveguide 126 embedded in the integrated interconnect structure 110b. In one embodiment, the coupling surface (e.g., the bottom surface) of the photonic die 124 includes a first portion electrically coupled to the electronic die 122 and a second portion optically coupled to the waveguide 126. In such an embodiment, the first portion may include a plurality of conductive connectors 1241 for bonding to a first redistribution structure 111, and the second portion may be a substantially flat surface for optical coupling to the waveguide 126. The electronic die 122 and waveguide 126 embedded in the integrated interconnect structure 110b, and the photonic die 124 bonded over the integrated interconnect structure 110b, can be considered as an optomechanical module 120b. Additionally, an integrated circuit package 130 is bonded over the integrated interconnect structure 110b and electrically coupled to the optomechanical module 120b. Electron die 122 is connected to photonic die 124 and integrated circuit package 130. In some embodiments, optomechanical module 120b is configured to connect to an optical device (e.g., via pin 1261 of waveguide 126). Figure 16 The optical fiber 150 shown receives optical signals. The photonic chip 124 is optically coupled to the optical device 150 via a waveguide 126. In some embodiments, a heat dissipation device (not shown), such as a heat sink, may be provided on the photonic chip 124 or the optomechanical module 120 to facilitate heat dissipation.

[0123] In embodiments of this disclosure, the semiconductor package employs an integrated interconnect structure between the packaging substrate and the optomechanical module / integrated circuit package. Accordingly, designing the electrical traces between the optomechanical module and the integrated circuit package within the integrated interconnect structure provides more space and finer-line electrical interconnects to improve bandwidth issues in optical systems with semiconductor packages. Furthermore, with this configuration, the optomechanical module and integrated circuit package can be tested separately before being bonded or embedded in the integrated interconnect structure, thus reducing manufacturing costs.

[0124] Based on the above discussion, it can be seen that this disclosure provides various advantages. However, it should be understood that not all advantages need to be discussed herein, and other embodiments may provide different advantages, and not all embodiments need to have specific advantages.

[0125] Other functions and processes can also be included. For example, test structures can be included to assist in verification testing of 3D packages or 3DIC devices. Test structures can include, for example, test pads formed on redistribution layers or substrates that allow for testing of 3D packages or 3DICs, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0126] According to some embodiments of the present disclosure, a semiconductor package includes a package substrate, an integrated interconnect structure, an optomechanical module, and an integrated circuit package. The integrated interconnect structure is bonded over the package substrate and includes an insulator and a plurality of vias extending through the insulator. The optomechanical module includes an electronic die, a photonic die, and a waveguide, wherein a portion of the optomechanical module is embedded in the integrated interconnect structure. The integrated circuit is bonded over the integrated interconnect structure and electrically coupled to the optomechanical module. In one embodiment, the electronic die and the waveguide are embedded in the integrated interconnect structure, and the photonic die is stacked over the electronic die and the waveguide. In one embodiment, the electronic die is connected to the photonic die and the integrated circuit package. In one embodiment, the waveguide includes an optical dielectric waveguide. In one embodiment, the semiconductor package further includes an interconnect device embedded in the integrated interconnect structure, and the interconnect device is connected to the electronic die and the integrated circuit package. In one embodiment, the waveguide is embedded in the integrated interconnect structure. In one embodiment, the electronic die is bonded over the integrated interconnect structure and electrically coupled to the interconnect device, and the photonic die is stacked over the electronic die and the waveguide. In one embodiment, the semiconductor package further includes a dummy die embedded in the integrated interconnect structure. In one embodiment, the photonic die is optically coupled to the optical device through the waveguide. In one embodiment, the integrated circuit package includes a processing die and a memory die bonded over an interposer, and an encapsulation material laterally encapsulating the processing die and the memory die.

[0127] According to some embodiments of the present disclosure, a semiconductor package includes a package substrate, an integrated interconnect structure, an interconnect device, an optomechanical module, and an integrated circuit package. The integrated interconnect structure includes an insulator and a plurality of vias extending through the insulator. The interconnect device is embedded in the integrated interconnect structure. The optomechanical module is bonded to the integrated interconnect structure and includes an electronic die, a photonic die, and a waveguide. The integrated circuit package is bonded over the integrated interconnect structure and electrically coupled to the optomechanical module via the interconnect device. In one embodiment, the waveguide is embedded in the integrated interconnect structure. In one embodiment, the electronic die is disposed over and connected to the interconnect device, and the photonic die is stacked over the electronic die and the waveguide. In one embodiment, the optomechanical module is disposed over the integrated interconnect structure. In one embodiment, the waveguide and the electronic die are bonded to an upper surface of the integrated interconnect structure, and the photonic die is stacked over and coupled to the electronic die and the waveguide. In one embodiment, the integrated circuit package includes a processing die and a memory die bonded over an interposer and an encapsulation material laterally encapsulating the processing die and the memory die.

[0128] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor package includes the following steps. An embedded device and a plurality of vias are provided over a carrier. An insulator is provided over the carrier to form an integrated interconnect structure, wherein the insulator laterally encapsulates at least the embedded device and the plurality of vias. The carrier is removed. The integrated interconnect structure is bonded over a package substrate. A photonic die is bonded over the integrated interconnect structure, wherein the photonic die is coupled to the embedded device. An integrated circuit package is bonded over the integrated interconnect structure, wherein the integrated circuit package is coupled to the photonic die via the integrated interconnect structure. In one embodiment, the method of manufacturing a semiconductor package further includes forming a recess at an outer edge of the insulator and disposing a waveguide in the recess before bonding the photonic die over the integrated interconnect structure. In one embodiment, the method of manufacturing a semiconductor package further includes bonding an electronic die over the integrated interconnect structure, wherein the photonic die is stacked over the electronic die, and the embedded device includes an interconnect device electrically coupled to the electronic die and the integrated circuit package. In one embodiment, the embedded device includes an electronic die, wherein the photonic die is stacked over and electrically coupled to the electronic die.

[0129] The foregoing summary has outlined several features of the embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the present disclosure. Those skilled in the art should also recognize from the summary above that equivalent constructions can perform similar functions, and that not all constructions described can be necessary for a particular implementation. Accordingly, it will be clear to those skilled in the art that they can make various changes, modifications, and alterations to the embodiments without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, characterized by, including: a package substrate; an integrated interconnect structure bonded over the package substrate and including an insulator and a plurality of vias extending through the insulator; an optomechanical module including an electronic die, a photonic die, and a waveguide, wherein a portion of the optomechanical module is embedded in the integrated interconnect structure; and an integrated circuit package bonded over the integrated interconnect structure and electrically coupled to the optomechanical module. The electronic die and the waveguide are embedded in the integrated interconnect structure, and the photonic die is stacked over the electronic die and the waveguide, and the electronic die is connected to the photonic die and the integrated circuit package.

2. The semiconductor package of claim 1, wherein, 3. The semiconductor package of claim 1, wherein the waveguide comprises an optical dielectric waveguide.

4. The semiconductor package of claim 1, further comprising an interconnect device embedded in the integrated interconnect structure, and the interconnect device is connected to the electronic die and the integrated circuit package, wherein the waveguide is embedded in the integrated interconnect structure, the electronic die is bonded over the integrated interconnect structure and electrically coupled to the interconnect device, and the photonic die is stacked over the electronic die and the waveguide.

5. The semiconductor package of claim 1, further comprising a dummy die embedded in the integrated interconnect structure.

6. The semiconductor package of claim 1, wherein the integrated circuit package comprises a processing die and a memory die bonded over an interposer and an encapsulation material laterally encapsulating the processing die and the memory die.

7. A semiconductor package comprising: a package substrate; an integrated interconnect structure including an insulator and a plurality of vias extending through the insulator; an interconnect device embedded in the integrated interconnect structure; an optomechanical module bonded to the integrated interconnect structure and including an electronic die, a photonic die, and a waveguide; an integrated circuit package bonded over the integrated interconnect structure and electrically coupled to the optomechanical module via the interconnect device.

8. The semiconductor package of claim 7, wherein the waveguide is embedded in the integrated interconnect structure, the electronic die is disposed over the interconnect device and connected to the interconnect device, and the photonic die is stacked over the electronic die and the waveguide.

9. The semiconductor package of claim 7, wherein the optomechanical module is disposed over the integrated interconnect structure, the waveguide and the electronic die are bonded to an upper surface of the integrated interconnect structure, and the photonic die is stacked over the electronic die and the waveguide and coupled to the electronic die and the waveguide.

10. The semiconductor package of claim 7, wherein the integrated circuit package comprises a processing die and a memory die bonded over an interposer and an encapsulation material laterally encapsulating the processing die and the memory die. ​

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