MOSFET packaging structure and power semiconductor device
By setting multiple solder points on the source pad of the MOSFET chip and increasing the contact length, the problem of high on-resistance in the MOSFET chip package structure is solved, thereby reducing power consumption and improving efficiency.
Patent Information
- Application Number
- CN202423249289.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2034-12-27
AI Technical Summary
In existing MOSFET chip packaging structures, the on-resistance is relatively large, the energy consumption is relatively high, and the efficiency is not ideal.
At least three solder joints are set on the source pad of the MOSFET chip and connected to the lead frame through source leads to increase the contact points and contact length between the source leads and the source pad, thereby reducing the equivalent lateral distributed resistance of the source pad.
By increasing the number of contact points and the contact length, the on-resistance of the MOSFET is reduced, thereby improving its operating efficiency.
Smart Images
Figure CN223665454U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of power devices, in particular to a MOSFET packaging structure and a power semiconductor device. BACKGROUND
[0002] In modern electronic devices, power semiconductor devices such as power MOSFETs are an important component, widely used in power electronic circuits for controlling voltage and current. The performance of power MOSFETs directly affects the efficiency and reliability of electronic devices.
[0003] The on-resistance (also known as on-loss or Rds(on)) of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a parameter that characterizes the resistance of the MOSFET in the on state. This parameter is very important for evaluating the energy consumption and efficiency of the MOSFET in a circuit. The smaller the on-resistance, the lower the energy consumption and the higher the efficiency of the MOSFET in the on state.
[0004] The on-resistance of a power device is mainly composed of internal MOSFET chip resistance, metal lead resistance, etc. The process of the metal lead is to connect one end of the metal wire to the metal electrode area of the internal MOSFET chip by welding, and then connect the other end of the metal wire to the metal frame by welding, so as to realize the connection of the electrode of the chip to the pin of the lead frame of the package.
[0005] The lead way of the packaging structure of the MOSFET chip in the prior art is greatly limited by the size of the MOSFET chip, resulting in a large on-resistance and high energy consumption in the packaging structure of the MOSFET chip after the MOSFET is connected to the lead frame by the metal lead, and the efficiency is not ideal.
[0006] Therefore, a solution is needed to solve the problem of large on-resistance, high energy consumption, and low efficiency of the packaging structure of the MOSFET chip in the power device. CONTENT OF THE INVENTION
[0007] Therefore, in order to solve the problem of large on-resistance, high energy consumption, and low efficiency of the packaging structure of the MOSFET chip in the power device, the present application provides a MOSFET packaging structure and a power semiconductor device.
[0008] In one aspect of the present application, the present application provides a MOSFET packaging structure, comprising: a lead frame; the lead frame comprising a discrete lead frame source, a lead frame gate and a lead frame drain; a MOSFET chip comprising a chip packaging substrate and a source pad and a gate pad on the surface of the chip packaging substrate; the gate pad is surrounded by the source pad and located at the edge of the area where the source pad is located; the gate pad is connected to the lead frame gate by a straight diagonal pull of the gate lead; the lead frame surrounds the MOSFET chip, and the lead frame drain is sleeved on the packaging substrate and directly connected to the drain of the MOSFET chip; the lead frame source is connected to the source pad by a plurality of source leads; each source lead is diagonally pulled from the lead frame source to the source pad; a single source lead has at least three solder joints on the source pad and one solder joint on the lead frame source.
[0009] The MOSFET packaging structure provided by the present application increases the contact points and contact length of the source lead and the source pad by arranging at least three solder joints on the source pad of the MOSFET chip, that is, increases the area of the source lead and the source pad, which in turn increases the area of the resistance through which the current flows, reduces the equivalent lateral distribution resistance of the source pad, and further reduces the on-resistance. This is conducive to reducing the power consumption of the MOSFET and improving its working efficiency. The MOSFET packaging structure provided by the present application is suitable for silicon-based, silicon carbide-based and silicon nitride-based high-current low-internal resistance MOSFET power devices.
[0010] Further, in some embodiments, the MOSFET packaging structure provided by the present application comprises a copper wire, an aluminum wire or a gold wire; the direction of the shortest distance from the source pad of the MOSFET chip to the lead frame source is the Y direction, and the direction horizontal to the Y direction is the X direction, and the single source lead is arranged in a straight line in the Y direction.
[0011] Further, in some embodiments, the MOSFET packaging structure provided by the present application comprises an array arrangement of the solder joints of all the source leads on the source pad, the same spacing between the source leads, and the same spacing between the solder joints of a single source lead on the source pad.
[0012] Further, in some embodiments, the MOSFET packaging structure provided by the present application comprises a spacing of 500 μm to 800 μm between the adjacent solder joints of a single source lead on the source pad.
[0013] Further, in some embodiments, the MOSFET packaging structure provided by the present application comprises an angle of 10° to 30° between the part between the solder joint of the source lead on the lead frame source and the solder joint of the source lead on the source pad and the connecting line part between each solder joint of the source lead on the source pad.
[0014] Further, in some embodiments, the MOSFET packaging structure provided by the present application has the solder joint of the source lead on the source pad, and the length of the solder joint in the Y direction and the length of the solder joint in the X direction have a ratio of 1:1-1.2:1.
[0015] Further, in some embodiments, the MOSFET packaging structure provided by the present application has the number of solder joints of a single source lead on the source pad, and the number of solder joints increases by one for each 1400 μm increase in the size of the source pad in the Y direction; and the number of source leads increases by one for each 800 μm increase in the size of the source pad in the X direction.
[0016] Further, in some embodiments, the MOSFET packaging structure provided by the present application has a packaging form of the MOSFET packaging structure, which includes a TO-18 packaging, a TO-220 packaging, and a TO-263 packaging; and when the packaging form is the TO-18 packaging, the lead scheme of the source lead on the source pad includes 3 solder joints by 7 leads, 3 solder joints by 8 leads, 4 solder joints by 7 leads, or 4 solder joints by 8 leads.
[0017] Further, in some embodiments, the MOSFET packaging structure provided by the present application has the source pad including a plurality of sub-pads, and the source lead spans the plurality of sub-pads by a single lead and is connected to each sub-pad by a solder joint.
[0018] In another aspect of the present application, the present application also provides a power semiconductor device including the MOSFET packaging structure provided by the present application. The MOSFET packaging structure provided by the present application has at least three solder joints of the source lead on the source pad of the MOSFET chip, so that the contact points and the contact length of the source lead and the source pad are increased, that is, the area of the source lead and the source pad is increased, which in turn increases the area of the resistance through which the current flows, so that the equivalent lateral distribution resistance of the source pad is reduced, and the on-resistance is reduced. This is beneficial to reduce the power consumption of the MOSFET and improve the working efficiency. The MOSFET packaging structure provided by the present application is suitable for silicon-based, silicon carbide-based, and silicon nitride-based high-current low-resistance MOSFET power devices. BRIEF DESCRIPTION OF DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art of the present application, the drawings needed in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0020] Figure 1Fig. 1 is a schematic diagram of a metal lead scheme of a MOSFET chip packaging structure;
[0021] Figure 2a and Figure 2b Fig. 4 is a schematic diagram of a metal layer transverse distribution resistance near a lead solder joint;
[0022] Figures 3a-3f Fig. 5 is a schematic diagram of each step of a metal lead scheme of a MOSFET chip packaging structure according to an embodiment of the present application;
[0023] Figure 4 Fig. 6 is a schematic diagram of a metal lead scheme of a MOSFET chip packaging structure according to another embodiment of the present application.
[0024] BRIEF DESCRIPTION OF DRAWINGS
[0025] 110 - source pad; 110C - chip pin; 110R - metal layer transverse distribution resistance; 130 - gate pad; 210 - lead frame source; 220 - lead frame drain; 230 - lead frame gate; 300 - source lead; 310 - solder joint; 3101 - first solder joint; 3102 - second solder joint; 3103 - third solder joint; 400 - gate lead; P - lead solder joint; 110R - metal layer equivalent transverse distribution resistance. DETAILED DESCRIPTION
[0026] Reference Figure 1 , Figure 1 Fig. 1 is a schematic diagram of a metal lead scheme of a MOSFET chip packaging structure, wherein the MOSFET packaging structure comprises a lead frame, the lead frame comprises a separate lead frame source 210, a lead frame gate 230 and a lead frame drain 220, a MOSFET chip comprising a chip packaging substrate (not shown in the figure) and a source pad 110 and a gate pad 130 on the surface of the chip packaging substrate, the gate pad 130 is surrounded by the source pad 110 and located at the edge of the area where the source pad 110 is located, the gate pad 130 is connected to the lead frame gate 230 by a gate lead 400, the lead frame surrounds the MOSFET chip, the lead frame drain 220 is sleeved on the packaging substrate and directly connected to the drain of the MOSFET chip, the lead frame source 210 is connected to the source pad 110 by a plurality of source leads 300, wherein each source lead 300 is straightly and obliquely pulled from the lead frame source 210 to the source pad 110, and each source lead 300 has one solder joint on the lead frame source 210 and one solder joint on the source pad 110.
[0027] In the lead layout, the current in the MOSFET chip flows from the chip pin 110C, through the MOSFET chip source pad 110, to the lead solder joint P, and then to the source lead 300 to the lead frame source 210, and finally to the external structure. The equivalent metal layer (i.e. the metal layer of the source pad 110) transverse distribution resistance 110R is shown in Figure 2a and Figure 2b As the source lead 300 has only one solder joint on the source pad 110, when the chip area is large, the chip metal layer area not in contact with the solder joint P is also large, the metal layer transverse distribution resistance is large, the on-resistance of the power MOSFET is large, and the energy consumption of the MOSFET in the on state is high, and the efficiency is low.
[0028] Therefore, the present application provides a MOSFET packaging structure and a power semiconductor device to solve the problem of large on-resistance, high energy consumption and low efficiency of the packaging structure of the MOSFET chip in the power device.
[0029] The present application provides a MOSFET packaging structure, comprising: a lead frame; the lead frame comprises a separate lead frame source, a lead frame gate and a lead frame drain; a MOSFET chip comprising a chip packaging substrate and a source pad and a gate pad on the surface of the chip packaging substrate; the gate pad is surrounded by the source pad and is located at the edge of the area where the source pad is located; the gate pad is connected to the lead frame gate by a straight diagonal pull of the gate lead; the lead frame surrounds the MOSFET chip, and the lead frame drain is sleeved on the packaging substrate and directly connected to the drain of the MOSFET chip; the lead frame source is connected to the source pad by a plurality of source leads; the source leads are all inclined from the lead frame source to the source pad; a single source lead has at least three solder joints on the source pad and one solder joint on the lead frame source.
[0030] The present application also provides a power semiconductor device comprising the MOSFET packaging structure provided by the present application.
[0031] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor are within the scope of protection of the present application.
[0032] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0033] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0034] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0035] Embodiment 1
[0036] Reference Figures 3a-3f The present embodiment provides a MOSFET packaging structure, comprising:
[0037] A lead frame, the lead frame comprising a discrete lead frame source 210, a lead frame gate 230 and a lead frame drain 220;
[0038] A MOSFET chip, comprising a chip packaging substrate and a source pad 110 and a gate pad 130 on the surface of the chip packaging substrate; the gate pad 130 is surrounded by the source pad 110 and located at the edge of the area where the source pad 110 is located; the gate pad 130 is connected to the lead frame gate 230 through a straight diagonal pull of the gate lead;
[0039] The lead frame surrounds the MOSFET chip, and the lead frame drain 220 is sleeved on the packaging substrate and directly connected to the drain of the MOSFET chip;
[0040] The lead frame source 210 is connected to the source pad 110 through a plurality of source leads 300; the source leads 300 are all pulled diagonally from the lead frame source 210 to the source pad 110;
[0041] Each source lead 300 has at least three solder joints 310 on the source pad 110 and one solder joint on the lead frame source 210.
[0042] The MOSFET packaging structure provided by the application increases the contact points and contact length of the source lead 300 and the source pad 110 of the MOSFET chip, that is, increases the area of the source lead 300 and the source pad 110, increases the area of the resistance through which the current flows, reduces the equivalent lateral distribution resistance of the source pad 110, and further reduces the on-resistance. This is conducive to reducing the power consumption of the MOSFET and improving the working efficiency. The MOSFET packaging structure provided by the application is suitable for silicon-based, silicon carbide-based, and silicon nitride-based high-current low-resistance MOSFET power devices.
[0043] Further, in some embodiments, the MOSFET packaging structure provided by the application includes a copper wire, an aluminum wire, or a gold wire; the direction of the shortest distance from the source pad 110 of the MOSFET chip to the lead frame source 210 is the Y direction, and the direction horizontal to the Y direction is the X direction, and the single source lead 300 is arranged in a straight line in the Y direction.
[0044] Further, in some embodiments, the MOSFET packaging structure provided by the application includes a copper wire, an aluminum wire, or a gold wire; the direction of the shortest distance from the source pad 110 of the MOSFET chip to the lead frame source 210 is the Y direction, and the direction horizontal to the Y direction is the X direction, and the single source lead 300 is arranged in a straight line in the Y direction.
[0045] Further, in some embodiments, the MOSFET packaging structure provided by the application includes a copper wire, an aluminum wire, or a gold wire; the direction of the shortest distance from the source pad 110 of the MOSFET chip to the lead frame source 210 is the Y direction, and the direction horizontal to the Y direction is the X direction, and the single source lead 300 is arranged in a straight line in the Y direction.
[0046] Further, in some embodiments, the MOSFET packaging structure provided by the application includes a copper wire, an aluminum wire, or a gold wire; the direction of the shortest distance from the source pad 110 of the MOSFET chip to the lead frame source 210 is the Y direction, and the direction horizontal to the Y direction is the X direction, and the single source lead 300 is arranged in a straight line in the Y direction.
[0047] Further, in some embodiments, the MOSFET packaging structure provided by the present application, the solder joint 310 of the source lead 300 on the source pad 110 has a length in the Y direction and a length in the X direction, and the ratio of the length in the Y direction to the length in the X direction is 1:1-1.2:1. In this way, the solder joint is approximately a cuboid resistance structure with a length in the Y direction and a width in the X direction, so that the resistance of the current in the Y direction is smaller than the resistance in the X direction, thereby making the current more easily flow into the source lead 300 in the Y direction.
[0048] Further, in some embodiments, the MOSFET packaging structure provided by the present application, the number of solder joints of a single source lead 300 on the source pad 110 satisfies: for every 1400 μm increase in the size of the source pad 110 in the Y direction, one solder joint is added; and the number of source leads 300 satisfies: for every 800 μm increase in the size of the source pad 110 in the X direction, one lead is added. Such a spacing arrangement can maximize the size of the source pad 110 and arrange the most solder joints 310 in the Y direction.
[0049] Further, in some embodiments, the MOSFET packaging structure provided by the present application, the packaging form of the MOSFET packaging structure includes: TOLL packaging, TO220 packaging, and TO263 packaging; when the packaging form is TOLL packaging, the lead scheme of the source lead 300 on the source pad 110 includes: 3 solder joints × 7 leads, 3 solder joints × 8 leads, 4 solder joints × 7 leads, or 4 solder joints × 8 leads.
[0050] A specific implementation process includes:
[0051] Reference Figure 3a , forming an initial solder joint: setting the position of the wedge of the solder wire to be consistent with the position of the initial solder joint, setting the force and energy of the solder wire, and pressing to obtain the initial solder joint, i.e., the first solder joint 3101;
[0052] First time retreat wedge: setting the initial angle and height of the first segment of the wire arc, and fine-tuning the position of the wedge of the solder wire, and retreating the wedge to be consistent with the preset position of the second solder joint;
[0053] Reference Figure 3b , forming a second solder joint: setting the force and energy of the solder wire, and pressing to obtain the second solder joint 3102;
[0054] Second time retreat wedge: setting the initial angle and height of the second segment of the wire arc, and fine-tuning the position of the wedge of the solder wire, and retreating the wedge to be consistent with the preset position of the third solder joint;
[0055] Reference Figure 3c , forming a third solder joint: setting the force and energy of the solder wire, and pressing to obtain the third solder joint 3103;
[0056] Third time retreat wedge: set the third segment line arc initial angle, line arc height, set the wedge position, retreat the wedge to make it consistent with the preset position of the metal frame bonding point;
[0057] Reference Figure 3d Metal frame bonding: set the soldering force and energy, and press the soldering to obtain the metal frame bonding point;
[0058] Fourth time retreat wedge: set the retreat wedge initial angle and the wedge termination position, retreat the wedge to cut off the metal wire, and complete the soldering of the first source lead 300 on the source pad 110;
[0059] Reference Figure 3e Repeat the above process to complete the soldering of all source leads 300 on the source pad 110;
[0060] Reference Figure 3f Finally, the soldering between the gate pad 130 and the lead frame gate 230 is performed, and the lead is completed. The MOSFET chip soldering process is stable, the three soldering points are consistent, flat, and have no virtual soldering and heavy.
[0061] Embodiment 2
[0062] This embodiment provides another embodiment related to the MOSFET packaging structure of the above-mentioned embodiment 1.
[0063] In some embodiments, the MOSFET packaging structure provided by the present application includes a plurality of sub-pads in the source pad 110, and the source lead 300 crosses the plurality of sub-pads through a single lead and is connected to each sub-pad through a soldering point.
[0064] Specifically, referring to Figure 4 The source pad 110 includes a plurality of sub-pads 111, 112, and 113, and a single source lead 300 crosses each sub-pad and forms a soldering point 310 connected to the pad.
[0065] In this way, the lead can pass through multiple sub-pads, and on the basis of ensuring a larger contact area between the lead and the pad, multiple sub-pads can be set according to circuit requirements for connection.
[0066] Embodiment 3
[0067] In another aspect of the present application, the present application also provides a power semiconductor device comprising the MOSFET packaging structure provided by the present application. The MOSFET packaging structure provided by the present application increases the contact points and contact length of the source lead with the source pad by arranging at least three soldering points on the source pad of the MOSFET chip, i.e. increases the area of the source lead with the source pad, which in turn increases the area of the resistance through which the current flows, reduces the equivalent lateral distributed resistance of the source pad, and further reduces the on-resistance. This is conducive to reducing the power consumption of the MOSFET and improving its working efficiency. The MOSFET packaging structure provided by the present application is suitable for silicon-based, silicon carbide-based, and silicon nitride-based high-current low-resistance MOSFET power devices.
[0068] Obviously, the above embodiments are only examples for clearly illustrating the present application, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and impossible to enumerate all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A MOSFET package structure, characterized in that, include: A lead frame; the lead frame includes a discrete lead frame source, a lead frame gate, and a lead frame drain; A MOSFET chip, including a chip package substrate and source pads and gate pads located on the surface of the chip package substrate; The gate pad is surrounded by the source pad and is located at the edge of the area where the source pad is located; the gate pad and the lead frame gate are connected by a straight, obliquely drawn gate lead. The lead frame surrounds the MOSFET chip, and the drain of the lead frame is sleeved on the package substrate and directly connected to the drain of the MOSFET chip. The source of the lead frame is connected to the source pad by a number of source leads; The source leads are all diagonally drawn from the source of the lead frame to the source pad; each source lead has at least three solder joints on the source pad and one solder joint on the source of the lead frame.
2. The MOSFET package structure according to claim 1, characterized in that, The source lead includes copper wire, aluminum wire, or gold wire; Taking the direction of the shortest distance from the source pad of the MOSFET chip to the source of the lead frame as the Y direction, and the direction perpendicular to the Y direction as the X direction, the following conditions must be met: The individual source leads are arranged in a straight line in the Y direction.
3. The MOSFET package structure according to claim 2, characterized in that, All the source leads have solder joints arranged in an array on the source pad, and the spacing between each source lead is the same. The spacing between solder joints of a single source lead on the source pad is also the same.
4. The MOSFET package structure according to claim 2, characterized in that, The spacing between adjacent solder joints on the source pad of a single source lead is 500μm to 800μm.
5. The MOSFET package structure according to claim 2, characterized in that, The portion of the source lead between the solder joint on the source of the lead frame and the solder joint on the source pad, and the portion of the line connecting each solder joint on the source pad, have an included angle of 10° to 30°.
6. The MOSFET package structure according to claim 1, characterized in that, The length ratio of the source lead's solder joint on the source pad is 1:1 to 1.2:1 in the Y direction to the length in the X direction.
7. The MOSFET package structure according to claim 1, characterized in that, The number of solder joints on the source pad of a single source lead satisfies the following condition: for every 1400μm increase in the size of the source pad in the Y direction, one solder joint is added; The number of source leads satisfies the following condition: for every 800 μm increase in the size of the source pad in the X direction, one lead is added.
8. The MOSFET package structure according to claim 7, characterized in that, The MOSFET packaging structure includes the following packaging forms: TOLL package, TO220 package, and TO263 package; When the package type is TOLL package, the lead configuration of the source leads on the source pads includes: 3 solder pads × 7 leads, 3 solder pads × 8 leads, 4 solder pads × 7 leads, or 4 solder pads × 8 leads.
9. The MOSFET package structure according to any one of claims 1-8, characterized in that, The source pad includes multiple sub-pads, and the source lead crosses the multiple sub-pads through a single lead and is connected to each sub-pad through a solder joint.
10. A power semiconductor device, characterized in that, Includes the MOSFET package structure as described in any one of claims 1-9.