Bus capacitor voltage-sharing and discharging circuit

Abstract

The utility model relates to a bus capacitor voltage-sharing and discharging circuit, which is used for carrying out voltage-sharing and processing on a positive bus capacitor and a negative bus capacitor between BUS buses, and the positive bus capacitor and the negative bus capacitor are connected in series and then are connected between the BUS buses. The bus capacitor voltage-sharing and discharging circuit comprises a half-bus voltage circuit, a switching circuit, a positive bus voltage-sharing resistor, a negative bus voltage-sharing resistor, a switching circuit and a normally-closed switch, and is connected with a collector of the first transistor at a first end through the normally-closed switch. And the normally closed switch is closed when the equipment is shut down, so that the positive bus voltage-sharing resistor, the negative bus voltage-sharing resistor and the bus capacitor are connected in parallel, and the voltage of the bus capacitor is quickly released. The voltage-sharing circuit and the discharging circuit are integrated, the safety and reliability of equipment work are improved, and the voltage-sharing circuit and the discharging circuit are integrated, so that the voltage-sharing circuit and the discharging circuit have great advantages in equipment size and cost, and are easy to implement and popularize.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of safety circuit, specifically relates to a circuit that equalizes voltage and discharges bus capacitor between BUS bus. BACKGROUND

[0002] With the rapid development of global electronic industry, various electronic devices emerge in endlessly, and among them, electrolytic capacitor is used very frequently. Meanwhile, with the continuous improvement of power and voltage level, electrolytic capacitor is often used in series in circuit to realize required function, but the overvoltage level of electrolytic capacitor is low, and the capacitance value and leakage current thereof are quite different, that is, even if electrolytic capacitors of the same type are connected in series, voltage distribution will be uneven if appropriate voltage equalization measures are not taken. Once overvoltage occurs in some electrolytic capacitor, electrolyte will splash and cause an accident. Meanwhile, because the capacity of electrolytic capacitor is large, the stored energy is also large, and a long time is needed to discharge the voltage on both sides of electrolytic capacitor to a safe voltage level when the device stops working, and before that, improper operation or accidental contact will cause electric shock risk, and also prolong the maintenance time, causing inconvenience in maintenance.

[0003] In view of the above problems, at present, for the working scene of electrolytic capacitors in series, such as in multi-level circuit, half-bridge circuit or high-voltage circuit, bus capacitors of the same specification and capacity are often used in series to divide the bus voltage of BUS bus, and a voltage equalization circuit is generally needed for each bus capacitor. Common voltage equalization circuits include the following:

[0004] Firstly, a voltage equalization resistor is connected in parallel with each series bus capacitor branch. Because the voltage equalization resistor is connected between the bus voltages, in order to equalize the voltage, the resistance of the voltage equalization resistor is generally small, so that additional circuit loss is caused. If the resistance is increased, although the power consumption of the resistor can be reduced, the voltage equalization effect will be affected.

[0005] Secondly, in view of the weak voltage equalization effect of a large resistance value, a group of switching circuits are used to connect a small resistance value voltage equalization resistor in series. When the voltage imbalance value exceeds a certain value, the switching circuit is started to connect the voltage equalization resistor to the bus capacitor; when the voltage is balanced, the switching circuit is turned off to disconnect the voltage equalization resistor from the bus capacitor, so as to avoid large power consumption of the voltage equalization resistor.

[0006] Thirdly, the commonly used balancing bridge circuit in the prior art needs to additionally increase a large power power topology circuit, including a large power semiconductor device and an energy storage element (such as an inductor), and a complex control algorithm is introduced, which is not beneficial to cost and size.

[0007] As for the discharge of bus capacitors, the following methods are commonly used at present:

[0008] One is that a small resistance is connected in parallel with the bus capacitor, and the resistance cooperates with the capacitance to discharge the bus capacitor when the machine is shut down, so that the voltage value of the bus capacitor is quickly reduced to a safe voltage. However, this method requires a large power resistor, and increases the power consumption of the system;

[0009] Two is that a small resistance is connected in parallel with the bus capacitor, and the resistance is connected in series with a power switch. When the device is working normally, the switch is in the closed state; when the device is shut down, the switch is opened to connect the resistance in parallel with the bus capacitor, so that the voltage of the capacitor is discharged at a relatively fast rate. This circuit can discharge the bus voltage to a certain voltage, but cannot be discharged to a lower voltage. The reason is that when the auxiliary power supply of the system is powered off, the bus voltage is generally still relatively high, at which time the power switch is out of control and in the closed state, and the discharge of the bus capacitor still takes a long time.

[0010] Therefore, how to provide a bus capacitor voltage equalization and discharge circuit to at least overcome one of the above-mentioned defects is a technical problem to be solved by the present application. Practical new type content

[0011] One of the main purposes of the present application is to overcome at least one of the above-mentioned defects, and to provide a bus capacitor voltage equalization and discharge circuit, which can integrate and use the voltage equalization circuit and the discharge circuit, improve the voltage equalization and discharge effect, and has great advantages in the size and cost of the final device.

[0012] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is:

[0013] The present application provides a bus capacitor voltage equalization and discharge circuit for equalizing and processing the positive and negative bus capacitors between the BUS bus, wherein the positive bus capacitor and the negative bus capacitor are connected in series and connected between the BUS bus, and the bus capacitor voltage equalization and discharge circuit comprises a half bus voltage circuit, a switch circuit, a positive bus voltage equalization resistor, a negative bus voltage equalization resistor, a switch circuit and a normally closed switch, wherein:

[0014] The half bus voltage circuit is arranged between the BUS bus and used for collecting the half bus voltage;

[0015] The switch circuit comprises a first transistor and a second transistor, the emitter of the first transistor and the second transistor is connected, the first end of the positive bus voltage equalization resistor is connected with the positive bus of the BUS bus, the second end of the positive bus voltage equalization resistor is connected with the collector of the first transistor, the first end of the negative bus voltage equalization resistor is connected with the negative bus of the BUS bus, the second end of the negative bus voltage equalization resistor is connected with the collector of the second transistor, the base of the first transistor and the second transistor is connected with the half bus voltage circuit, and the emitter of the first transistor and the second transistor is also connected with the connection midpoint of the positive and negative bus capacitors.

[0016] The first end of the normally closed switch is connected with the collector of the first transistor, and the second end of the normally closed switch is connected with the collector of the second transistor.

[0017] According to one of the embodiments of the utility model, the bus capacitor voltage sharing and discharging circuit further comprises a voltage sharing threshold circuit, the base of the first transistor and the second transistor is connected with the voltage sharing threshold circuit, and the voltage sharing threshold circuit is further connected with the connection midpoint of the half bus voltage circuit.

[0018] According to one of the embodiments of the utility model, the voltage sharing threshold circuit comprises two voltage stabilizing tubes, the two voltage stabilizing tubes are connected in series and placed reversely, the first end of the series circuit formed by the two voltage stabilizing tubes is connected with the base of the first transistor and the second transistor, and the second end is connected with the connection midpoint of the half bus voltage circuit.

[0019] According to one of the embodiments of the utility model, the voltage sharing threshold circuit comprises a bidirectional voltage stabilizing tube, the first end of the bidirectional voltage stabilizing tube is connected with the base of the first transistor and the second transistor, and the second end is connected with the connection midpoint of the half bus voltage circuit.

[0020] According to one of the embodiments of the utility model, the half bus voltage circuit comprises a first voltage division acquisition module and a second voltage division acquisition module, the first voltage division acquisition module and the second voltage division acquisition module are connected in series to form the half bus voltage circuit, and the connection point between the first voltage division acquisition module and the second voltage division acquisition module is the connection midpoint of the half bus voltage circuit.

[0021] According to one of the embodiments of the utility model, the first voltage division acquisition module and the second voltage division acquisition module are respectively formed by one resistor or two or more resistors connected in series, and the resistance value of the first voltage division acquisition module is equal to that of the second voltage division acquisition module.

[0022] According to one of the embodiments of the utility model, the resistance value of the positive bus voltage sharing resistor and the negative bus voltage sharing resistor is equal, and the resistance value of the first voltage division acquisition module and the second voltage division acquisition module is greater than that of the positive bus voltage sharing resistor and the negative bus voltage sharing resistor.

[0023] According to one of the embodiments of the utility model, the positive bus capacitor and the negative bus capacitor are respectively formed by one capacitor or two or more capacitors connected in parallel, the capacitance value of the positive bus capacitor is equal to that of the negative bus capacitor, and the connection point between the positive bus capacitor and the negative bus capacitor is the connection midpoint of the positive and negative bus capacitors.

[0024] According to one of the embodiments of the utility model, the capacitor in the positive bus capacitor and the negative bus capacitor is an electrolytic capacitor.

[0025] According to one of the embodiments of the utility model, the normally closed switch is powered on and presents an off state when the BUS bus is normally powered on, and the normally closed switch loses power and presents a closed state when the BUS bus is powered off.

[0026] Compared with the prior art, the bus capacitor voltage sharing and discharge circuit has the following advantages and beneficial effects:

[0027] The bus capacitor voltage sharing and discharge circuit can integrate the voltage sharing circuit and the discharge circuit, can automatically and dynamically share the voltage of the bus capacitor, has good voltage sharing effect, can reduce unnecessary functional loss, can quickly discharge the bus capacitor to a safe voltage at the moment of shutdown, has good voltage sharing and discharge effects on the bus capacitor, and improves the safety and reliability of equipment operation.

[0028] In addition, the voltage sharing circuit and the discharge circuit are combined into one circuit, which has great advantages in equipment size and cost, and is easy to implement and promote. BRIEF DESCRIPTION OF DRAWINGS

[0029] Some specific embodiments of the utility model will be described in detail below with reference to the accompanying drawings, which are exemplary but not limiting. The same reference signs in the drawings indicate the same or similar components or parts. Those skilled in the art should understand that the drawings are not necessarily drawn to scale. In the drawings:

[0030] Figure 1 is a frame schematic diagram of the bus capacitor voltage sharing and discharge circuit according to the embodiment 1 of the utility model;

[0031] Figure 2 is a circuit structure schematic diagram of the bus capacitor voltage sharing and discharge circuit according to the embodiment 1 of the utility model;

[0032] Figure 3 is a frame schematic diagram of the bus capacitor voltage sharing and discharge circuit according to the embodiment 2 of the utility model;

[0033] Figure 4 is a circuit structure schematic diagram of the bus capacitor voltage sharing and discharge circuit according to the embodiment 2 of the utility model;

[0034] Figure 5 is an equivalent circuit schematic diagram of the bus capacitor voltage sharing and discharge circuit according to the embodiment 2 of the utility model, in which the normally closed switch is in a closed state after the BUS bus is powered off, and the bus capacitor is discharged. DETAILED DESCRIPTION

[0035] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0036] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0037] Example 1:

[0038] This embodiment describes a bus capacitor equalization and discharge circuit for equalizing and processing the positive and negative bus capacitors between BUS buses. The positive bus capacitor C1 and the negative bus capacitor C2 are connected in series between the BUS buses. As shown... Figure 1 The block diagram shown illustrates a bus capacitor equalization and discharge circuit comprising a half-bus voltage circuit, a switching circuit, a positive bus voltage equalization resistor R1, a negative bus voltage equalization resistor R2, a switching circuit, and a normally closed switch S1. The positive bus capacitor C1 and the negative bus capacitor C2 are electrolytic capacitors connected in series between the BUS buses. The half-bus voltage circuit generates a precise half-voltage of the total bus voltage (the voltage between the positive bus BUS+ and the negative bus BUS-). When the voltage difference across the positive and negative bus capacitors is lower than a certain value, the connection between the equalization resistors and the bus capacitors is disconnected via the switching circuit. When the voltage difference between the positive and negative bus capacitors is higher than a certain value, the connection between the equalization resistors and the bus capacitors is closed.

[0039] The normally closed switch S1 can be a normally closed relay or similar device. The normally closed switch S1 is energized and in the closed state when the BUS bus is normally powered on; the normally closed switch S1 is de-energized and in the closed state when the BUS bus is de-energized. That is, when the equipment is shut down and the BUS bus is de-energized, the normally closed switch S1 switches from the normally open state to the normally closed state. The normally closed switch S1 connects the positive and negative bus voltage equalization resistor R2 to the positive and negative bus capacitors, enabling rapid discharge of the positive and negative bus capacitors through the positive and negative bus voltage equalization resistor R2.

[0040] Specifically, such as Figure 2The half bus voltage circuit is arranged between the BUS buses and used for collecting half bus voltage; the switch circuit comprises a first transistor Q1 and a second transistor Q2, the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are connected, the first end of the positive bus voltage resistance R1 is connected with the positive bus BUS+ of the BUS buses, the second end of the positive bus voltage resistance R1 is connected with the collector of the first transistor Q1, the first end of the negative bus voltage resistance R2 is connected with the negative bus BUS- of the BUS buses, the second end of the negative bus voltage resistance R2 is connected with the collector of the second transistor Q2, the base of the first transistor Q1 and the base of the second transistor Q2 are connected with the half bus voltage circuit, and the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are also connected with the connecting point of the positive and negative bus capacitors; the first end of the normally closed switch S1 is connected with the collector of the first transistor Q1, and the second end of the normally closed switch S1 is connected with the collector of the second transistor Q2.

[0041] In the embodiment, when the voltage drop between the connecting point A of the half bus voltage circuit and the connecting point B of the positive and negative bus capacitors is greater than the threshold voltage, the corresponding first transistor Q1 or second transistor Q2 is turned on, so as to connect and turn on the positive bus voltage resistance R1 and the first transistor Q1 or connect and turn on the negative bus voltage resistance R2 and the second transistor Q2, thereby discharging and voltage regulating the bus capacitor. In the embodiment, the threshold voltage is theoretically 0V, but actually the voltage drop between the collector and the emitter of the transistor, which is usually 0.7V. Because the absolute value is small, it is generally regarded as 0V, and the special description is made.

[0042] The half bus voltage circuit comprises a first voltage division collecting module R3 and a second voltage division collecting module R4. The first voltage division collecting module R3 and the second voltage division collecting module R4 are connected in series to form the half bus voltage circuit, and the connecting point between the first voltage division collecting module R3 and the second voltage division collecting module R4 is the connecting point A of the half bus voltage circuit. The first voltage division collecting module R3 and the second voltage division collecting module R4 can be formed by one resistance or two or more resistances connected in series, as long as the resistance values of the first voltage division collecting module R3 and the second voltage division collecting module R4 are equal, so as to realize accurate extraction of the half bus voltage.

[0043] In addition, the resistance values of the positive bus voltage equalization resistor R1 and the negative bus voltage equalization resistor R2 are generally designed to be equal. However, in order to improve efficiency, the resistance values of the first voltage division acquisition module R3 and the second voltage division acquisition module R4 are generally designed to be relatively large, so that the power consumption is relatively low, and the resistance values of the positive bus voltage equalization resistor R1 and the negative bus voltage equalization resistor R2 are designed to be relatively small, so that the voltage equalization capability is increased, and the discharge voltage equalization of the bus capacitor is relatively fast. That is, the resistance values of the first voltage division acquisition module R3 and the second voltage division acquisition module R4 are greater than the resistance values of the positive bus voltage equalization resistor R1 and the negative bus voltage equalization resistor R2.

[0044] The positive bus capacitor C1 and the negative bus capacitor C2 are respectively formed by one capacitor or two or more capacitors in parallel, and the capacitors in the positive bus capacitor C1 and the negative bus capacitor C2 are electrolytic capacitors. The resistance values of the positive bus capacitor C1 and the negative bus capacitor C2 are equal, and the connection point between the positive bus capacitor C1 and the negative bus capacitor C2 is the connection midpoint B of the positive and negative bus capacitors.

[0045] Embodiment 2

[0046] The bus capacitor voltage equalization and discharge circuit of this embodiment is improved on the basis of the bus capacitor voltage equalization and discharge circuit of Embodiment 1, and the improvement is that, as shown in Figure 3 a voltage equalization threshold circuit is arranged between the base of each transistor and the connection midpoint of the half bus voltage circuit, and the base of the first transistor Q1 and the second transistor Q2 is connected to the voltage equalization threshold circuit, and the voltage equalization threshold circuit is further connected to the connection midpoint A of the half bus voltage circuit.

[0047] Through the design of the voltage equalization threshold circuit, the voltage drop between the connection midpoint A of the half bus voltage circuit and the connection midpoint B of the positive and negative bus capacitors is compared with the breakdown voltage of the voltage stabilizing tube in the voltage equalization threshold circuit through the design of the hardware circuit, the breakdown voltage of the voltage stabilizing tube is taken as the threshold voltage, and the transistor is turned on when the voltage is greater than the threshold voltage, so as to realize voltage equalization by connecting the voltage equalization resistor and the bus capacitor in parallel. That is, the bus capacitor voltage equalization and discharge circuit of this embodiment can turn on the transistor under a certain voltage difference, and then realize discharge by connecting the voltage equalization resistor and the bus capacitor in parallel, so that the bus capacitor and the transistor start voltage equalization only when the voltage difference between them is greater than the threshold voltage, effectively avoiding the influence of high-frequency repeated opening of the transistor on its service life, and enhancing the robustness of the voltage equalization circuit.

[0048] Specifically, as shown in Figure 4 the voltage equalization threshold circuit includes two voltage stabilizing tubes, the two voltage stabilizing tubes are connected in series and placed in reverse, the first end of the series circuit formed by the two voltage stabilizing tubes is connected to the base of the first transistor Q1 and the second transistor Q2, and the second end is connected to the connection midpoint of the half bus voltage circuit.

[0049] When the capacitor voltage across the positive bus capacitor C1 is higher than the half bus voltage, and the voltage difference (the voltage U between points A and B AB ) is greater than the breakdown voltage of the voltage regulator, the first voltage regulator Z1 is broken down and turned on, the second voltage regulator Z2 is forward biased and turned on, and the first transistor Q1 is further turned on. The positive bus capacitor C1 is discharged through the positive bus voltage equalizing resistor R1.

[0050] Similarly, when the capacitor voltage of the negative bus capacitor C2 is higher than the half bus voltage, and the voltage difference (the voltage U between points B and A BA ) is greater than the breakdown voltage of the voltage regulator, the first voltage regulator Z1 is forward biased and turned on, the second voltage regulator Z2 is broken down and turned on, and the second transistor Q2 is further turned on. The negative bus capacitor C2 is discharged through the negative bus voltage equalizing resistor R2.

[0051] The voltage equalizing threshold circuit here can also be implemented by replacing the two voltage regulators described above with a bidirectional voltage regulator. The first end of the bidirectional voltage regulator is connected to the bases of the first transistor Q1 and the second transistor Q2, and the second end is connected to the connection midpoint of the half bus voltage circuit. The working principle is the same as that of the two voltage regulators described above, except that the selection of electrical components is different, so it is not repeated here.

[0052] Specifically, taking the working scenario of the bus voltage of the BUS bus at 800V as an example. The device selection is as follows: R1 is 1MΩ, R2 is 10KΩ, Z1 and Z2 are 30V voltage regulators, and C1 and C2 are both 4700uf.

[0053] According to Figure 4 the parameters marked in the circuit schematic, the voltage of the connection midpoint A of the half bus voltage circuit is 400V (relative to BUS-). If the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2 exceeds 30V from the half bus voltage value, i.e., the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2 exceeds 60V, taking the voltage value of the positive bus capacitor C1 as an example, the voltage of the connection midpoint B of the positive and negative bus capacitors is low, and the first transistor Q1 is turned on while the second transistor Q2 is turned off. The positive bus voltage equalizing resistor R1 connects the positive bus capacitor C1 in parallel, and the positive bus voltage equalizing resistor R1 discharges and equalizes the positive bus capacitor C1 until the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2 is less than 60V. Conversely, if the voltage value of the positive bus capacitor C1 is low, the voltage of the connection midpoint B of the positive and negative bus capacitors is high, the first transistor Q1 is turned off while the second transistor Q2 is turned on, the negative bus voltage equalizing resistor R2 connects the negative bus capacitor C2 in parallel, and the negative bus voltage equalizing resistor R2 discharges and equalizes the negative bus capacitor C2 until the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2 is less than 60V.

[0054] When the BUS bus is in a power-on state, the normally closed switch S1 is controlled by an external controller to be in an off state, or the normally closed switch S1 is directly powered by the BUS bus or an auxiliary power supply, so that the normally closed switch S1 switches its own off or closed state according to the power-on state of the BUS bus. It can be seen that when the BUS bus is in a power-on state, the normally closed switch S1 has no effect on the voltage equalization process. When the device is powered off, the BUS bus is powered off, and after a period of time (for example, the auxiliary power supply extracts the energy of the bus capacitor at a high power), the auxiliary power supply fails, and the BUS bus still maintains a high voltage (for example, 200V). At this time, because the BUS bus is powered off and the auxiliary power supply is lost, the control signal of the normally closed switch S1 is lost, so the normally closed switch S1 is switched from off to closed, and the two voltage equalization resistors (the positive bus voltage equalization resistor R1 and the negative bus voltage equalization resistor R2) are connected in series through the normally closed switch S1 and then connected in parallel to the bus capacitor. The equivalent circuit is shown in Figure 5 The capacitor voltage formula is as follows according to the time constant theory:

[0055]

[0056] In the above formula, 47 is the time constant, and the unit is second; The BUS bus voltage curve with time is shown in FIG. 6. According to the above formula, it can be solved that the bus voltage can be reduced to 60V, a safe voltage value, after 56.6 seconds, and the electrolytic capacitor voltage can be quickly released.

[0057] If there is no discharge circuit in the embodiment, the positive bus capacitor C1 and the negative bus capacitor C2 are discharged through the first voltage division acquisition module R3 and the second voltage division acquisition module R4, and the resistance values of the first voltage division acquisition module R3 and the second voltage division acquisition module R4 are much larger than those of the positive bus voltage equalization resistor R1 and the negative bus voltage equalization resistor R2. At this time, the time constant is as high as 4700 seconds. According to the capacitor voltage formula calculated according to the time constant theory:

[0058]

[0059] According to the above formula, it can be solved that the bus voltage can be reduced to 60V, a safe voltage value, after 5658 seconds, that is, it takes nearly two hours to release the electrolytic capacitor voltage to a safe value, which is much higher than the aforementioned 56.6 seconds of rapid discharge through the voltage equalization resistor.

[0060] The above is only an example for illustration. The resistance value of the voltage equalization resistor, the breakdown voltage of the voltage stabilizing tube of the voltage equalization threshold circuit, and the capacitance value of the bus capacitor can be optimized according to the specific circuit requirements.

[0061] In conclusion, the bus capacitor voltage equalization and discharge circuit can integrate the voltage equalization circuit and the discharge circuit by changing the structure of the hardware circuit, can complete the automatic dynamic voltage equalization of the bus capacitor, has good voltage equalization effect, can reduce unnecessary function loss, can quickly discharge the bus capacitor to a safe voltage at the shutdown moment, has good voltage equalization and discharge effects on the bus capacitor, and improves the safety and reliability of equipment work.

[0062] The above examples are only for illustrating the technical concept and characteristics of the utility model, the purpose is to enable the person skilled in the art to understand the content of the utility model and to implement it, and it cannot limit the protection scope of the utility model, and equivalent changes or modifications made according to the spirit and essence of the utility model should be covered in the protection scope of the utility model.

Claims

1. A bus capacitor equalization and discharge circuit, used for equalizing and processing the positive and negative bus capacitors between BUS buses, wherein the positive and negative bus capacitors are connected in series between the BUS buses, characterized in that... The bus capacitor equalization and discharge circuit includes a half-bus voltage circuit, a switching circuit, a positive bus voltage equalization resistor, a negative bus voltage equalization resistor, a switching circuit, and a normally closed switch, wherein: The half-bus voltage circuit is set between the BUS buses and is used to collect the half-bus voltage. The switching circuit includes a first transistor and a second transistor, with the emitters of the first transistor and the second transistor connected together. The first end of the positive bus voltage equalization resistor is connected to the positive bus of the BUS bus, and the second end of the positive bus voltage equalization resistor is connected to the collector of the first transistor. The first end of the negative bus voltage equalization resistor is connected to the negative bus of the BUS bus, and the second end of the negative bus voltage equalization resistor is connected to the collector of the second transistor. The bases of the first transistor and the second transistor are connected to the half-bus voltage circuit, and the emitters of the first transistor and the second transistor are also connected to the midpoint of the connection between the positive and negative bus capacitors. The first terminal of the normally closed switch is connected to the collector of the first transistor, and the second terminal of the normally closed switch is connected to the collector of the second transistor.

2. The bus capacitor equalization and discharge circuit according to claim 1, characterized in that, The bus capacitor equalization and discharge circuit also includes an equalization threshold circuit. After the bases of the first transistor and the second transistor are connected to the equalization threshold circuit, the equalization threshold circuit is then connected to the connection midpoint of the half bus voltage circuit.

3. The bus capacitor equalization and discharge circuit according to claim 2, characterized in that, The voltage equalization threshold circuit includes two Zener diodes connected in series and placed in opposite directions. The first end of the series circuit formed by the two Zener diodes is connected to the base of the first transistor and the second transistor, and the second end is connected to the connection midpoint of the half bus voltage circuit.

4. The bus capacitor equalization and discharge circuit according to claim 2, characterized in that, The voltage equalization threshold circuit includes a bidirectional Zener diode, the first end of which is connected to the base of the first transistor and the second transistor, and the second end is connected to the connection midpoint of the half bus voltage circuit.

5. The bus capacitor equalization and discharge circuit according to any one of claims 1 to 4, characterized in that, The half-bus voltage circuit includes a first voltage divider acquisition module and a second voltage divider acquisition module. The first voltage divider acquisition module and the second voltage divider acquisition module are connected in series to form the half-bus voltage circuit. The connection point between the first voltage divider acquisition module and the second voltage divider acquisition module is the connection midpoint of the half-bus voltage circuit.

6. The bus capacitor equalization and discharge circuit according to claim 5, characterized in that, The first voltage divider acquisition module and the second voltage divider acquisition module are each composed of one resistor or two or more resistors connected in series, and the resistance values ​​of the first voltage divider acquisition module and the second voltage divider acquisition module are equal.

7. The bus capacitor equalization and discharge circuit according to claim 6, characterized in that, The resistance values ​​of the positive bus voltage equalizing resistor and the negative bus voltage equalizing resistor are equal, and the resistance values ​​of the first voltage divider acquisition module and the second voltage divider acquisition module are greater than the resistance values ​​of the positive bus voltage equalizing resistor and the negative bus voltage equalizing resistor.

8. The bus capacitor equalization and discharge circuit according to any one of claims 1 to 4, characterized in that, The positive bus capacitor and the negative bus capacitor are each composed of one capacitor or two or more capacitors connected in parallel. The capacitance values ​​of the positive bus capacitor and the negative bus capacitor are equal. The connection point between the positive bus capacitor and the negative bus capacitor is the connection midpoint of the positive and negative bus capacitors.

9. The bus capacitor equalization and discharge circuit according to claim 8, characterized in that, Both the positive bus capacitor and the negative bus capacitor are electrolytic capacitors.

10. The bus capacitor equalization and discharge circuit according to claim 1, characterized in that, The normally closed switch is energized and in the closed state when the BUS bus is normally energized; the normally closed switch is de-energized and in the closed state when the BUS bus is de-energized.

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