Wide rated current intelligent switching surge decoupling network

Abstract

The utility model relates to an intelligent switching surge decoupling network with a wide rated current. The intelligent switching surge decoupling network comprises a three-phase power supply, a surge decoupling circuit and a switch control circuit, the surge decoupling circuit is composed of four groups of decoupling inductance circuits, a plurality of relay switches and a current monitoring ring. And each group of decoupling inductance circuit comprises a plurality of inductors with different rated currents and is switched through a relay switch. The current monitoring ring collects current data of a three-phase power supply in real time, converts analog signals into digital signals through the AD conversion chip, and sends the digital signals to the microcontroller. The microcontroller controls the logic editor according to the current data, and drives the relay switch to carry out proper switching. A proper decoupling inductance circuit can be automatically selected according to different requirements of three-phase current, and high efficiency and safety of a surge decoupling effect are ensured. Compared with a traditional manual switching mode, the electromagnetic compatibility testing device has higher automation degree, reliability and safety, and is widely applied to various electromagnetic compatibility testing fields.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the electromagnetic compatibility test and measurement technical field, concretely relates to a wide rated current intelligence switching surge decoupling network. BACKGROUND

[0002] Under the new energy development form in recent years, the rated capacity of the lightning surge test decoupling network needs to improve further, the rated current capacity is from several amperes to 200 amperes, but according to the national standard GB / T17626.5, the decoupling network capacity that does not pass needs to meet different parameters, so the market generally has different decoupling networks for different rated currents, and several different rated current decoupling networks are very cumbersome to switch, especially the manual switching of high-current networks is unsafe, and at least 5 decoupling networks are needed to meet the rated current network below 200A, resulting in high cost. UTILITY MODEL CONTENTS

[0003] The utility model discloses a wide rated current intelligence switching surge decoupling network that overcomes the defects in the prior art.

[0004] The utility model discloses a wide rated current intelligence switching surge decoupling network that overcomes the defects in the prior art.

[0005] The utility model provides a kind of wide rated current intelligence switching surge decoupling network, including three-phase power supply, surge decoupling circuit and switch control circuit;

[0006] The surge decoupling circuit includes four groups of decoupling inductance circuits, first current monitoring ring, second current monitoring ring, third current monitoring ring, first relay switch, ninth relay switch, tenth relay switch, and the four groups of decoupling inductance circuits are respectively first decoupling inductance circuit, second decoupling inductance circuit, third decoupling inductance circuit and fourth decoupling inductance circuit, each decoupling inductance circuit includes five parallel different rated current decoupling inductances, and each decoupling inductance is connected with a relay switch in series;

[0007] The three-phase power supply outputs first hot line, second hot line, third hot line, zero line and ground wire, the first hot line is connected with the first decoupling inductance circuit through the first relay switch and the first current monitoring ring in series, the second hot line is connected with the second decoupling inductance circuit through the ninth relay switch and the second current monitoring ring in series, the third hot line is connected with the third decoupling inductance circuit through the tenth relay switch and the third current monitoring ring in series, and the zero line is connected with the fourth decoupling inductance circuit;

[0008] The switch control circuit includes an AD conversion chip, a microcontroller, a logic editor, a first grating isolation group, a second grating isolation group, a third grating isolation group, a fourth grating isolation group, a first NOT gate chip, a second NOT gate chip, a third NOT gate chip, and a fourth NOT gate chip. The input ends of the switch control circuit are connected with the first current monitoring ring, the second current monitoring ring, and the third current monitoring ring respectively, and the output ends are connected with each relay switch of the surge decoupling circuit respectively.

[0009] Further, the 1 pin, the 2 pin, and the 3 pin of the AD conversion chip are connected with the first current monitoring ring, the second current monitoring ring, and the third current monitoring ring respectively. The 15 pin of the AD conversion chip is connected with the ADCS pin of the microcontroller. The 16 pin of the AD conversion chip is connected with the ADDOU pin of the microcontroller. The 17 pin of the AD conversion chip is connected with the ADDIN pin of the microcontroller. The 18 pin of the AD conversion chip is connected with the ADCLK pin of the microcontroller. The 19 pin of the AD conversion chip is connected with the ADINT pin of the microcontroller.

[0010] Further, the D0 to D7 pins of the microcontroller are connected with the D0 to D7 pins of the logic editor respectively.

[0011] Further, the first grating isolation group, the second grating isolation group, the third grating isolation group, and the fourth grating isolation group each include four groups of grating isolation circuits, and the grating isolation circuit includes an optical coupler and a resistor.

[0012] Further, the first grating isolation group includes a first grating isolation circuit, a second grating isolation circuit, a third grating isolation circuit, a fourth grating isolation circuit, and a fifth grating isolation circuit.

[0013] The first grating isolation circuit includes a first optical coupler. The 3 pin of the first optical coupler is connected with the P1.1 pin of the logic editor. The 5 pin of the first optical coupler is connected with the 1 pin of the first NOT gate chip through the sixteenth resistor.

[0014] The second grating isolation circuit includes a second optical coupler. The 3 pin of the second optical coupler is connected with the P1.2 pin of the logic editor. The 5 pin of the second optical coupler is connected with the 2 pin of the first NOT gate chip through the seventeenth resistor.

[0015] The third grating isolation circuit includes a third optical coupler. The 3 pin of the third optical coupler is connected with the P1.3 pin of the logic editor. The 5 pin of the third optical coupler is connected with the 3 pin of the first NOT gate chip through the eighteenth resistor.

[0016] The fourth grating isolation circuit includes a fourth optical coupler. The 3 pin of the fourth optical coupler is connected with the P1.4 pin of the logic editor. The 5 pin of the fourth optical coupler is connected with the 4 pin of the first NOT gate chip through the nineteenth resistor.

[0017] The fifth grating isolation circuit includes a fifth optical coupler, the 3 pin of the fifth optical coupler is connected with the P1.5 pin of the logic editor, and the 5 pin of the fifth optical coupler is connected with the 5 pin of the first NAND gate chip through the twentieth resistor.

[0018] Further, the internal circuits of the second grating isolation group, the third grating isolation group and the fourth grating isolation group are the same as those of the first grating isolation group.

[0019] The input end of the second grating isolation group is connected with the P2 group pin of the logic editor, and the output end is respectively connected with the 1 pin, the 2 pin, the 3 pin, the 4 pin and the 5 pin of the second NAND gate chip.

[0020] The input end of the third grating isolation group is connected with the P3 group pin of the logic editor, and the output end is respectively connected with the 1 pin, the 2 pin, the 3 pin, the 4 pin and the 5 pin of the third NAND gate chip.

[0021] The input end of the fourth grating isolation group is connected with the P4 group pin of the logic editor, and the output end is respectively connected with the 1 pin, the 2 pin, the 3 pin, the 4 pin and the 5 pin of the fourth NAND gate chip.

[0022] Further, the first decoupling inductor circuit includes a second relay switch, a third relay switch, a fourth relay switch, a fifth relay switch and a sixth relay switch, and the 16 pin, the 15 pin, the 14 pin, the 13 pin and the 12 pin of the first NAND gate chip are respectively connected with the second relay switch, the third relay switch, the fourth relay switch, the fifth relay switch and the sixth relay switch.

[0023] Further, the second decoupling inductor circuit includes a seventh relay switch, an eighth relay switch, an eleventh relay switch, a twelfth relay switch and a thirteenth relay switch, and the 16 pin, the 15 pin, the 14 pin, the 13 pin and the 12 pin of the second NAND gate chip are respectively connected with the seventh relay switch, the eighth relay switch, the eleventh relay switch, the twelfth relay switch and the thirteenth relay switch.

[0024] Further, the third decoupling inductor circuit includes a fourteenth relay switch, a fifteenth relay switch, a sixteenth relay switch, a seventeenth relay switch and an eighteenth relay switch, and the 16 pin, the 15 pin, the 14 pin, the 13 pin, the 12 pin and the 10 pin of the third NAND gate chip are respectively connected with the fourteenth relay switch, the fifteenth relay switch, the sixteenth relay switch, the seventeenth relay switch, the eighteenth relay switch and the tenth relay switch.

[0025] Further, the fourth decoupling inductance circuit comprises a nineteenth relay switch, a twentieth relay switch, a twenty-first relay switch, a twenty-second relay switch, a twenty-third relay switch, and the 16th pin, the 15th pin, the 14th pin, the 13th pin, the 12th pin, the 11th pin and the 10th pin of the fourth NOT gate chip are connected with the nineteenth relay switch, the twentieth relay switch, the twenty-first relay switch, the twenty-second relay switch, the twenty-third relay switch, the first relay switch and the ninth relay switch respectively.

[0026] Compared with the prior art, the utility model has the following advantages:

[0027] (1) The utility model discloses can be used in the experimental test below the rated current 200A, can automatically monitor the load current, and the intelligent switching is decoupled to the network parameter of corresponding current range, thereby reaches the output waveform parameter requirement of satisfying national standard GB / T17626.5.

[0028] (2) Through the intelligent switching different rated current's decoupling inductance circuit, the utility model can be in different current range high -efficiently suppresses the surge, ensures that the system can provide the best surge decoupling effect under various load conditions. In addition, the automatic switching function reduces the interference of manual operation, reduces the security hidden danger that manual switching brings.

[0029] (3) The utility model discloses through three -way independent current monitoring and relay control system, real -time response three -phase current's change, and automatically select proper decoupling inductance circuit. This automatic switching mechanism eliminates the demand of manual operation, greatly simplifies the operation process, improves the reliability and convenience of system.

[0030] (4) Through switching different rated current's inductance circuit, the utility model can satisfy from small current to the surge decoupling demand of large current range, especially applicable to the surge suppression test under high current environment. This design makes even under low current condition, the system can provide sufficient surge suppression capacity.

[0031] (5) The utility model discloses the surge decoupling network strictly follows GB / T 17626.5 standard, can switch the current gear according to standard requirement, and ensures the inductance characteristic of each gear to satisfy the prescribed requirement, improves the normative and accuracy of test.

[0032] (6) The utility model discloses through switch control circuit can automatically adjust decoupling inductance circuit, reduces the need of manual operation and equipment maintenance, thereby reduces the operation cost and maintenance difficulty of equipment. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 It is the surge decoupling network chart of prior art;

[0034] Figure 2 It is the surge decoupling circuit diagram of the utility model;

[0035] Figure 3 It is the switch control circuit diagram of the utility model;

[0036] In the drawing, the reference signs are: U1, AD conversion circuit, U2, first NAND gate chip, U3, second NAND gate chip, U4, third NAND gate chip, U5, fourth NAND gate chip, F1, logic editor, F2, microcontroller, JP1, first optocoupler, JP2, second optocoupler, JP3, third optocoupler, JP4, fourth optocoupler, JP5, fifth optocoupler, R16, sixteenth resistance, R17, seventeenth resistance, R18, eighteenth resistance, R19, nineteenth resistance, R20, twentieth resistance, S1, first relay switch, S2, second relay switch, S3, third relay switch, S4, fourth relay switch, S5, fifth relay switch, S6, sixth relay switch, S7, seventh relay switch, S8, eighth relay switch, S9, ninth relay switch, S10, tenth relay switch, S11, eleventh relay switch, S12, twelfth relay switch, S13, thirteenth relay switch, S14, fourteenth relay switch, S15, fifteenth relay switch, S16, sixteenth relay switch, S17, seventeenth relay switch, S18, eighteenth relay switch, S19, nineteenth relay switch, S20, twentieth relay switch, S21, twenty-first relay switch, S22, twenty-second relay switch, S23, twenty-third relay switch. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model and not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the utility model.

[0038] The existing current rating intelligent switching surge decoupling network is switched in parallel through multiple small-current reactors to form the required rated current decoupling network, as shown in the following formula: Figure 1

[0039] ​The utility model relates to a kind of wide rated current intelligent switching surge decoupling network, to improve the surge decoupling effect in electromagnetic compatibility (EMC) test, and solve the cumbersome and security risk problem caused by manual switching in prior art.The decoupling network can automatically switch different rated current decoupling inductance circuit according to real-time current demand by intelligent control technology, to realize the efficiency and safety of surge decoupling, especially suitable for surge suppression test under high current environment.

[0040] As Figure 2 Indicated, including three-phase power supply, surge decoupling circuit and switch control circuit;

[0041] Surge decoupling circuit includes four groups of decoupling inductance circuit, first current monitoring ring, second current monitoring ring, third current monitoring ring, first relay switch, ninth relay switch, tenth relay switch, four groups of decoupling inductance circuit are respectively first decoupling inductance circuit, second decoupling inductance circuit, third decoupling inductance circuit, fourth decoupling inductance circuit, each decoupling inductance circuit includes 5 parallel different rated current decoupling inductance, each decoupling inductance is in series with a relay switch;

[0042] Three-phase power supply outputs first firewire, second firewire, third firewire, zero line and ground wire, first firewire is connected with first decoupling inductance circuit through the first relay switch, first current monitoring ring in series, second firewire is connected with second decoupling inductance circuit through the ninth relay switch, second current monitoring ring in series, third firewire is connected with third decoupling inductance circuit through the tenth relay switch, third current monitoring ring in series, zero line is connected with fourth decoupling inductance circuit;

[0043] As Figure 3 Indicated, switch control circuit includes AD conversion chip, microcontroller, logic editor, first grating isolation group, second grating isolation group, third grating isolation group, fourth grating isolation group, first NAND gate chip, second NAND gate chip, third NAND gate chip, fourth NAND gate chip, switch control circuit input is respectively connected with first current monitoring ring, second current monitoring ring, third current monitoring ring, and output is respectively connected with each relay switch of surge decoupling circuit.

[0044] Further, the 1 pin, 2 pin, 3 pin of AD conversion chip are respectively connected with first current monitoring ring, second current monitoring ring, third current monitoring ring, the 15 pin of AD conversion chip is connected with the ADCS pin of microcontroller, the 16 pin of AD conversion chip is connected with the ADDOU pin of microcontroller, the 17 pin of AD conversion chip is connected with the ADDIN pin of microcontroller, the 18 pin of AD conversion chip is connected with the ADCLK pin of microcontroller, the 19 pin of AD conversion chip is connected with the ADINT pin of microcontroller.

[0045] Further, the D0 to D7 pins of the microcontroller are connected with the D0 to D7 pins of the logic editor respectively.

[0046] Further, the first, second, third and fourth grating isolation groups each include four groups of grating isolation circuits, and the grating isolation circuit includes an optical coupler and a resistor.

[0047] Further, the first grating isolation group includes the first, second, third, fourth and fifth grating isolation circuits.

[0048] The first grating isolation circuit includes a first optical coupler, the 3 pin of the first optical coupler is connected with the P1.1 pin of the logic editor, and the 5 pin of the first optical coupler is connected with the 1 pin of the first NAND gate chip through the sixteenth resistor.

[0049] The second grating isolation circuit includes a second optical coupler, the 3 pin of the second optical coupler is connected with the P1.2 pin of the logic editor, and the 5 pin of the second optical coupler is connected with the 2 pin of the first NAND gate chip through the seventeenth resistor.

[0050] The third grating isolation circuit includes a third optical coupler, the 3 pin of the third optical coupler is connected with the P1.3 pin of the logic editor, and the 5 pin of the third optical coupler is connected with the 3 pin of the first NAND gate chip through the eighteenth resistor.

[0051] The fourth grating isolation circuit includes a fourth optical coupler, the 3 pin of the fourth optical coupler is connected with the P1.4 pin of the logic editor, and the 5 pin of the fourth optical coupler is connected with the 4 pin of the first NAND gate chip through the nineteenth resistor.

[0052] The fifth grating isolation circuit includes a fifth optical coupler, the 3 pin of the fifth optical coupler is connected with the P1.5 pin of the logic editor, and the 5 pin of the fifth optical coupler is connected with the 5 pin of the first NAND gate chip through the twentieth resistor.

[0053] Further, the internal circuits of the second, third and fourth grating isolation groups are the same as those of the first grating isolation group.

[0054] The input end of the second grating isolation group is connected with the P2 group of pins of the logic editor, and the output end is connected with the 1, 2, 3, 4 and 5 pins of the second NAND gate chip respectively.

[0055] The input end of the third grating isolation group is connected with the P3 group of pins of the logic editor, and the output end is connected with the 1, 2, 3, 4 and 5 pins of the third NAND gate chip respectively.

[0056] The fourth grating isolation group input end is connected with the P4 group pin of the logic editor, and the output end is connected with the 1 pin, 2 pin, 3 pin, 4 pin and 5 pin of the fourth NAND gate chip.

[0057] Further, the first decoupling inductance circuit includes a second relay switch, a third relay switch, a fourth relay switch, a fifth relay switch and a sixth relay switch, and the 16th pin, 15th pin, 14th pin, 13th pin and 12th pin of the first NAND gate chip are connected with the second relay switch, the third relay switch, the fourth relay switch, the fifth relay switch and the sixth relay switch respectively.

[0058] Further, the second decoupling inductance circuit includes a seventh relay switch, an eighth relay switch, an eleventh relay switch, a twelfth relay switch and a thirteenth relay switch, and the 16th pin, 15th pin, 14th pin, 13th pin and 12th pin of the second NAND gate chip are connected with the seventh relay switch, the eighth relay switch, the eleventh relay switch, the twelfth relay switch and the thirteenth relay switch respectively.

[0059] Further, the third decoupling inductance circuit includes a fourteenth relay switch, a fifteenth relay switch, a sixteenth relay switch, a seventeenth relay switch and an eighteenth relay switch, and the 16th pin, 15th pin, 14th pin, 13th pin, 12th pin and 10th pin of the third NAND gate chip are connected with the fourteenth relay switch, the fifteenth relay switch, the sixteenth relay switch, the seventeenth relay switch and the eighteenth relay switch respectively.

[0060] Further, the fourth decoupling inductance circuit includes a nineteenth relay switch, a twentieth relay switch, a twenty-first relay switch, a twenty-second relay switch and a twenty-third relay switch, and the 16th pin, 15th pin, 14th pin, 13th pin, 12th pin, 11th pin and 10th pin of the fourth NAND gate chip are connected with the nineteenth relay switch, the twentieth relay switch, the twenty-first relay switch, the twenty-second relay switch and the twenty-third relay switch respectively.

[0061] The surge decoupling circuit is composed of four groups of decoupling inductance circuits, three groups of current monitoring rings and multiple relay switches. Each group of decoupling inductance circuits contains multiple inductors with different rated currents, which are connected in series through relay switches for switching when needed. The current monitoring ring is connected with each decoupling inductance circuit for real-time monitoring of the current size of the three-phase power supply. The current signal collected by the current monitoring ring is converted into a digital signal through an AD conversion chip and sent to a microcontroller. The microcontroller controls the logic editor to output corresponding control signals according to the collected current data, thereby driving the closing or opening of the relay switches and realizing the switching of the decoupling inductance circuit in different current ranges. The switch control circuit automatically selects the appropriate decoupling inductance circuit according to the current size in this way and ensures that the surge decoupling function is always in the best working state.

[0062] In the specific working process, when the system starts, the three-phase power supply is connected to the decoupling inductance circuit through multiple relay switches. In the initial state, all the relay switches are in the closed state, and the system allows a maximum current of 200A to pass. The current monitoring ring monitors the current size of the three-phase power supply in real time, and the current transformer generates an analog voltage signal proportional to the current according to the current of each phase line. The analog signal is converted into a digital signal through an AD conversion chip and transmitted to a microcontroller. The microcontroller analyzes whether the current value meets the requirements of a certain specific range according to the converted current data. The microcontroller further generates control signals through a logic editor to drive the relay switches to perform corresponding switching operations. The control of each phase current is independent, so each phase line can independently adjust the decoupling inductance circuit according to its specific current value to cope with the different synchronization conditions of the three-phase current.

[0063] For example, assuming that the current monitoring ring detects that the current of the first phase (L1-IN) is 16A or less, the switch control circuit will select only the decoupling inductance circuit suitable for 16A current (such as S2, S7, S14 and S19) to avoid unnecessary inductance waste; when the current is greater than 16A but less than or equal to 32A, the system will automatically select the decoupling inductance circuit suitable for 32A current (such as S2, S3, S7, S8, S14, etc.) and close more relay switches accordingly to ensure that the surge decoupling effect is not affected. When the current gradually increases, the system will gradually close more relay switches in a similar manner until the current reaches the maximum value of 200A, at which point all the relay switches are closed to achieve the surge decoupling effect of the maximum rated current.

[0064] The working principle of the utility model is as follows:

[0065] The initial state, each phase of three-phase input electric relay switch S1, S9, S10 is closed, relay switch S2-S8 and S11-23 are in the closed state, at this time can run the maximum current 200A, each phase by 5 decoupling inductance assembly, here is an example of the first phase line L1-IN, for example, wherein the decoupling inductance L1 rated current 17A, decoupling inductance L2 rated current 17A, decoupling inductance L3 rated current 34A, decoupling inductance L4 rated current 68A, decoupling inductance L5 rated current 68A, when the relay switch S1, S9, S10 is closed, the current monitoring ring P1, P2, P3 will be collected first, second, third fire line current size, current monitoring ring P1 collected L1-IN phase line current corresponding to the analog voltage U1, will be input to the 1 pin of 12 bit AD conversion chip TLC2543, the data after AD conversion chip conversion will be sent to F2 microcontroller (CPU-STM-F107), microcontroller will be according to the AD conversion chip transmission of the collected current level to determine, according to the determination result output to the external logic editor F1 (EPM7128SL84), EPM7128SL84 is a total of 84 IO control port of the editable logic editor, when the need for final closing S2 switch, the logic editor F1 will be through the pin P1.1 output low to the 3 pin of the first optocoupler JP1, so that the first optocoupler JP1 into working state, so that the output point N6 is low, through the sixteenth resistance R16 into the first NAND chip U2 (ULN2003), the first NAND chip U2 output high to the second relay switch S2, so that the second relay switch S2 into the closed state, to achieve the purpose of switch control, other road switch control same reason. The grating isolation group 2, grating isolation group 3, grating isolation group 4 are the second grating isolation group, third grating isolation group, fourth grating isolation group, corresponding to the second fire line L2-IN, third fire line L3-IN, zero line N.

[0066] According to the collected current size, and according to the decoupling network current grading of standard GB / T 17626.5, the switching of the decoupling inductor is carried out, when the collected current is less than or equal to 16A, the switches S2, S7, S14 and S19 are closed simultaneously through the above control principle; when the collected current is greater than 16A and less than or equal to 32A, the switches S2, S3, S7, S8, S14, S15, S19 and S20 are closed simultaneously; when the collected current is greater than 32A and less than or equal to 64A, the switches S2, S3, S4, S7, S8, S11, S14, S15, S16, S19, S20 and S21 are closed simultaneously; when the collected current is greater than 64A and less than or equal to 125A, the switches S2, S3, S4, S5, S7, S8, S11, S12, S14, S15, S16, S17, S19, S20, S21 and S22 are closed simultaneously; when the collected current is greater than 125A and less than or equal to 200A, the switches S2, S3, S4, S5, S6, S7, S8, S11, S12, S14, S15, S16, S17, S18, S19, S20, S21, S22 and S23 are closed simultaneously.

[0067] This network realizes the use of up to 200A rated current scenarios through the combination of multiple small inductors, and small inductors can also be used for switching tests at low current, which meets the rated current grading parameters of the decoupling network in the national standard GB / T17626.5, and the actual use current is collected and monitored for intelligent switching. Because it is three independent collections, each switch is independently switched to the decoupling inductor when the three currents are different, without the need for manual replacement of the network, which is safer and more reliable.

[0068] The decoupling inductor circuit of the utility model has a clever design, and through the series combination of inductors with different rated currents, it can cover different needs from small current to large current. This inductor combination enables the system to provide sufficient surge suppression capability through small inductor circuits even in low current tests, and in the case of large current, the system can automatically switch to high current rated decoupling inductors to ensure the stability and effectiveness of the surge decoupling network.

[0069] In addition, the intelligent switching mechanism of the utility model greatly simplifies the operation process. Through three independent current monitoring and relay control, the system can respond to different changes in three-phase current in real time without manual intervention. When the current of each phase reaches the specified range, the system automatically switches to the appropriate decoupling inductor circuit without the need for manual replacement of the decoupling network, reducing the potential risks brought by human operation and improving the safety and reliability of the system. Intelligent switching not only improves the automation level of the system, but also reduces the maintenance and operation cost of the equipment.

[0070] Another important advantage of the utility model is in line with the requirements of national standard GB / T 17626.5.According to the standard, the surge decoupling network needs to have switching capacity of different current capacity, and the inductance characteristic of each current grade needs to meet certain requirements.Through the intelligent switching system of the utility model, the system can automatically adjust the rated current of decoupling inductance according to the change of current, ensure that the test process can strictly follow the standard to test, meet the requirements of different current grades, thereby improve the accuracy and standardization of test.

[0071] In summary, the utility model provides a kind of automatic, intelligent surge decoupling network solution, through the combination of current monitoring and intelligent control, different decoupling inductance circuit can be automatically switched according to real-time current change, avoid the complexity and potential risk of manual switching.The utility model not only improves test efficiency and system security, but also reduces manual intervention and equipment maintenance cost, meets the requirements of relevant standards, has wide application prospect.

[0072] The above is only a specific embodiment of the utility model, but the protection scope of the utility model is not limited to this, any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the utility model, these modifications or replacements should be covered in the protection scope of the utility model.Therefore, the protection scope of the utility model should be subject to the protection scope of claim.

Claims

1. A wide rated current intelligent switching surge decoupling network, characterized in that, Includes three-phase power supply, surge decoupling circuit and switch control circuit; The surge decoupling circuit includes four sets of decoupling inductor circuits, a first current monitoring loop, a second current monitoring loop, a third current monitoring loop, a first relay switch, a ninth relay switch, and a tenth relay switch. The four sets of decoupling inductor circuits are the first decoupling inductor circuit, the second decoupling inductor circuit, the third decoupling inductor circuit, and the fourth decoupling inductor circuit. Each set of decoupling inductor circuits includes five decoupling inductors with different rated currents connected in parallel, and each decoupling inductor is connected in series with a relay switch. The three-phase power supply outputs a first live wire, a second live wire, a third live wire, a neutral wire, and a ground wire. The first live wire is connected to a first decoupling inductor circuit via a first relay switch and a first current monitoring ring connected in series. The second live wire is connected to a second decoupling inductor circuit via a ninth relay switch and a second current monitoring ring connected in series. The third live wire is connected to a third decoupling inductor circuit via a tenth relay switch and a third current monitoring ring connected in series. The neutral wire is connected to a fourth decoupling inductor circuit. The switch control circuit includes an AD conversion chip, a microcontroller, a logic editor, a first grating isolation group, a second grating isolation group, a third grating isolation group, a fourth grating isolation group, a first NOT gate chip, a second NOT gate chip, a third NOT gate chip, and a fourth NOT gate chip. The input terminals of the switch control circuit are respectively connected to the first current monitoring loop, the second current monitoring loop, and the third current monitoring loop, and the output terminals are respectively connected to the relay switches of the surge decoupling circuit.

2. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, Pins 1, 2, and 3 of the AD conversion chip are connected to the first current monitoring loop, the second current monitoring loop, and the third current monitoring loop, respectively. Pin 15 of the AD conversion chip is connected to the ADCS pin of the microcontroller. Pin 16 of the AD conversion chip is connected to the ADDOU pin of the microcontroller. Pin 17 of the AD conversion chip is connected to the ADDIN pin of the microcontroller. Pin 18 of the AD conversion chip is connected to the ADCLK pin of the microcontroller. Pin 19 of the AD conversion chip is connected to the ADINT pin of the microcontroller.

3. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The D0 to D7 pins of the microcontroller are connected to the D0 to D7 pins of the logic editor, respectively.

4. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The first grating isolation group, the second grating isolation group, the third grating isolation group, and the fourth grating isolation group each include four grating isolation circuits, and the grating isolation circuits include optocouplers and resistors.

5. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The first grating isolation group includes a first grating isolation circuit, a second grating isolation circuit, a third grating isolation circuit, a fourth grating isolation circuit, and a fifth grating isolation circuit; The first grating isolation circuit includes a first optocoupler, pin 3 of which is connected to pin P1.1 of the logic editor, and pin 5 of which is connected to pin 1 of the first NOT gate chip through a sixteenth resistor. The second grating isolation circuit includes a second optocoupler, pin 3 of which is connected to pin P1.2 of the logic editor, and pin 5 of which is connected to pin 2 of the first NOT gate chip through the seventeenth resistor; The third grating isolation circuit includes a third optocoupler, pin 3 of which is connected to pin P1.3 of the logic editor, and pin 5 of which is connected to pin 3 of the first NOT gate chip through the eighteenth resistor. The fourth grating isolation circuit includes a fourth optocoupler, pin 3 of which is connected to pin P1.4 of the logic editor, and pin 5 of which is connected to pin 4 of the first NOT gate chip through the nineteenth resistor. The fifth grating isolation circuit includes a fifth optocoupler. Pin 3 of the fifth optocoupler is connected to pin P1.5 of the logic editor, and pin 5 of the fifth optocoupler is connected to pin 5 of the first NOT gate chip through a twentieth resistor.

6. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The internal circuits of the second, third, and fourth grating isolation groups are the same as those of the first grating isolation group; The input terminal of the second grating isolation group is connected to the P2 group pin of the logic editor, and the output terminal is connected to pins 1, 2, 3, 4 and 5 of the second NOT gate chip respectively; The input terminal of the third grating isolation group is connected to the P3 group pins of the logic editor, and the output terminal is connected to pins 1, 2, 3, 4 and 5 of the third NOT gate chip respectively. The input terminal of the fourth grating isolation group is connected to the P4 group pin of the logic editor, and the output terminal is connected to pins 1, 2, 3, 4 and 5 of the fourth NOT gate chip, respectively.

7. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The first decoupling inductor circuit includes a second relay switch, a third relay switch, a fourth relay switch, a fifth relay switch, and a sixth relay switch. Pins 16, 15, 14, 13, and 12 of the first NOT gate chip are respectively connected to the second relay switch, the third relay switch, the fourth relay switch, the fifth relay switch, and the sixth relay switch.

8. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The second decoupling inductor circuit includes a seventh relay switch, an eighth relay switch, an eleventh relay switch, a twelfth relay switch, and a thirteenth relay switch. Pins 16, 15, 14, 13, and 12 of the second NOT gate chip are respectively connected to the seventh relay switch, the eighth relay switch, the eleventh relay switch, the twelfth relay switch, and the thirteenth relay switch.

9. The wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The third decoupling inductor circuit includes a fourteenth relay switch, a fifteenth relay switch, a sixteenth relay switch, a seventeenth relay switch, and an eighteenth relay switch. Pins 16, 15, 14, 13, 12, and 10 of the third NOT gate chip are respectively connected to the fourteenth relay switch, the fifteenth relay switch, the sixteenth relay switch, the seventeenth relay switch, the eighteenth relay switch, and the tenth relay switch.

10. A wide rated current intelligent switching surge decoupling network according to claim 1, characterized in that, The fourth decoupling inductor circuit includes a nineteenth relay switch, a twentieth relay switch, a twenty-first relay switch, a twenty-second relay switch, and a twenty-third relay switch. Pins 16, 15, 14, 13, 12, 11, and 10 of the fourth NOT gate chip are respectively connected to the nineteenth relay switch, the twentieth relay switch, the twenty-first relay switch, the twenty-second relay switch, the twenty-third relay switch, the first relay switch, and the ninth relay switch.

Images