Semiconductor device

Abstract

The utility model discloses a semiconductor device. A semiconductor device, apparatus, structure, and associated methods. The device includes a substrate, a first base layer, a second base layer, and a third base layer. The substrate is disposed between the first base layer and the second and third base layers. The device includes one or more first doped regions and one or more second doped regions. The first doped region is disposed in the third base layer, and at least a portion of the second doped region is disposed in the substrate. The first doped region and the second doped region form one or more junctions configured to increase current conduction of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of power semiconductor discrete devices, and in particular to unidirectional low voltage SIDACtor devices. BACKGROUND

[0002] A discrete semiconductor is a device designated to perform a basic electronic function and is not separable into individual parts that each perform a function of the device. Power semiconductors are used as switches or rectifiers in power electronics. Diodes, transistors, thyristors, and rectifiers are examples of discrete power semiconductors. Discrete power semiconductors exist in a variety of different environments from very low power systems to very high power systems.

[0003] Examples of semiconductor devices include SIDACtor devices, which can be used for overvoltage transient suppression in, for example, telecommunications and data networking equipment applications. SIDACtor devices present some limitations. In particular, in these devices, the off-state voltage of the SIDACtor device should typically be greater than the maximum operating voltage of the circuit it is protecting. The switching voltage of the SIDACtor device should typically be equal to or less than the transient peak voltage rating of the electronic components it is designed to protect. Further, the inclusion of power supplies along with low voltage digital signals in power over Ethernet (PoE) circuits can require that these circuits be protected from current overload and voltage transients such as lightning, ESD, and other fast transients propagated on AC power lines. These and other requirements associated with SIDACtor devices present design challenges, particularly with respect to circuit performance, size, and cost. Moreover, existing SIDACtor devices typically suffer from high breakdown voltages, further complicating implementation of these devices in electronic circuits. UTILITY

[0004] The following summary is presented in order to provide a brief overview of some of the concepts described in greater detail below in the detailed description. This summary does not purport to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0005] In some implementations, the current subject matter relates to a semiconductor device. The device can include a substrate, a first base layer, a second base layer, and a third base layer. The substrate can be disposed between the first base layer and the second base layer and the third base layer, one or more first doped regions and one or more second doped regions. The one or more first doped regions can be disposed in the third base layer, and at least a portion of the one or more second doped regions can be disposed in the substrate. The one or more first doped regions and the one or more second doped regions form one or more junctions configured to increase current conduction of the semiconductor device.

[0006] In some implementations, the current subject matter can include one or more of the following optional features. The substrate can be an N-type substrate. The first base layer and the third base layer can be p-base layers. The second base layer can be an N+ base layer.

[0007] In some implementations, the device can also include one or more first regions disposed in the third base layer. The one or more first regions can be N+ type regions.

[0008] In some implementations, the one or more first doped regions can be p-type regions, and the one or more second doped regions can be n+ type regions. The one or more junctions can be P-N junctions.

[0009] In some implementations, at least one of the one or more first doped regions and the one or more second doped regions can be doped with one or more dopants. The one or more dopants can include at least one of: phosphorus, boron, arsenic, gallium, and any combination thereof. The one or more first doped regions and the one or more second doped regions can have a respective predetermined concentration of the one or more dopants. Each of the one or more first doped regions and the one or more second doped regions can have a respective predetermined depth. The semiconductor device can be characterized by a breakdown voltage, where the breakdown voltage of the semiconductor device can be determined as a function of at least one of: the predetermined concentration of the one or more dopants, the predetermined depth of the one or more first doped regions, the predetermined depth of the one or more second doped regions, and any combination thereof. Each of the one or more first doped regions and the one or more second doped regions can have the same concentration of the one or more dopants. Each of the one or more first doped regions and the one or more second doped regions can have different concentrations of the one or more dopants.

[0010] In some implementations, the device can include a first terminal layer coupled to the third base layer, and a second terminal layer coupled to the first base layer and the second base layer.

[0011] In some embodiments, the device can include one or more passivation layers disposed at one or more edges of the semiconductor device. The one or more passivation layers are configured to be disposed across at least one of: one or more portions of the substrate, one or more portions of the third base layer, one or more portions of the one or more first doped regions, one or more portions of the one or more second doped regions, and any combination thereof.

[0012] In some embodiments, the semiconductor device is a SIDACTor device.

[0013] In some embodiments, the current subject matter relates to a method for fabricating a semiconductor device. The method can include providing a substrate; providing a first base layer, a second base layer, and a third base layer, wherein the substrate is disposed between the first base layer and the second base layer and the third base layer; forming one or more first doped regions and one or more second doped regions, wherein the one or more first doped regions are formed in the third base layer and at least a portion of the one or more second doped regions are formed in the substrate; forming one or more junctions between the one or more first doped regions and the one or more second doped regions; coupling a first terminal layer to the third base layer and a second terminal layer to the first base layer and the second base layer; and coupling one or more passivation layers at one or more edges of the semiconductor device, wherein the one or more passivation layers are configured to be disposed across at least one of: one or more portions of the substrate, one or more portions of the third base layer, one or more portions of the one or more first doped regions, one or more portions of the one or more second doped regions, and any combination thereof.

[0014] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings illustrate certain aspects of the subject matter disclosed herein, and together with the description, help explain some principles associated with the disclosed embodiments. In the drawings,

[0016] Figure 1 An exemplary semiconductor device is shown;

[0017] Figure 2 An exemplary unidirectional semiconductor device is shown;

[0018] Figure 3a Examples of semiconductor devices (e.g., SIDACTor devices) in accordance with some embodiments of the current subject matter are shown;

[0019] Figure 3b Another example of a semiconductor device (e.g., a SIDACTor device) is shown in accordance with some embodiments of the current subject matter;

[0020] Figure 4 is Figure 3a the device shown in Figure 3b a top view of the device shown in

[0021] Figure 5 An example current-voltage plot is shown; and

[0022] Figure 6 An example process is shown in accordance with some embodiments of the current subject matter.

[0023] The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict only typical embodiments of the current subject matter and therefore should not be considered as limiting its scope. In the drawings, like reference numerals refer to like elements.

[0024] Further, for purposes of illustration, certain elements of some of the figures can be omitted, and / or not drawn to scale. Cross-sectional views can be in the form of “sliced” and / or “close-up” cross-sectional views, such that certain background lines that would otherwise be present in a “true” cross-sectional view are omitted for purposes of illustration. Additionally, some reference numbers can be omitted in certain figures for clarity. DETAILED DESCRIPTION

[0025] Various methods according to the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of systems and methods are shown. The devices, systems, components, etc. described can be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the current subject matter to those skilled in the art.

[0026] To address these and potential other deficiencies, one or more embodiments of the current subject matter relate to methods, systems, articles of manufacture, and the like, which are capable of providing unidirectional low voltage semiconductor devices, such as SIDACTor devices, among potentially other advantages.

[0027] Voltage transients are defined as surges of electrical energy of short duration and are the result of a sudden release of energy previously stored and / or induced by other means such as, for example, a heavy inductive load, lightning, etc. Voltage transients can be classified as predictable or repeatable transients and random transients. In electrical or electronic circuits, such energy can be released in a predictable manner via controlled switching action or randomly induced into the circuit from external sources. Repeatable transients are often caused by the operation of motors, generators, and / or switching of reactive circuit components. Random transients, on the other hand, are typically caused by electrostatic discharge (ESD) and lightning, the occurrence of which is generally unpredictable.

[0028] ESD is characterized by very fast rise times and very high peak voltages and currents, which can be the result of an imbalance of positive and negative charges between objects. ESDs generated by everyday activities can exceed the vulnerability threshold of standard semiconductor technology. In the case of lightning, the voltage transients induced by lightning are not the result of a direct hit, even though a direct hit is destructive. When a lightning strike occurs, the event can generate a magnetic field, which in turn can induce a voltage transient of large magnitude in nearby electrical cables. For example, an intercloud lightning strike can affect not only overhead cables, but also buried cables. Even a lightning strike 1 mile (1.6 km) away can generate a 70-volt voltage in a cable. In a cloud-to-ground lightning strike, the effects of the voltage transient are significantly greater.

[0029] Figure 1 An exemplary semiconductor device 100 is shown. The semiconductor device 100 can include a p-type layer 102, an n-type layer 104, and a p-type layer 106. The layer 102 can be configured to include a first n-type region 103 and a second n-type region 105. Similarly, the layer 106 can be configured to include a third n-type region 107. The device 100 also includes a first main terminal (MT1) or anode 1 (used interchangeably herein) 108, a gate terminal 110, and a second main terminal (MT2) or anode 2 (used interchangeably herein) 112. The first main terminal (MT1) 108 is coupled to a portion of the layer 102 and a portion of the second n-type region 105. The gate terminal 110 is coupled to another portion of the layer 102 and a portion of the first n-type region 103. The second main terminal (MT2) 112 is coupled to a portion of the layer 106 and a portion of the third n-type region 107.

[0030] Device 100 operates using one of four combinations or quadrants of the gate 110 voltage relative to the MT1 108 terminal and the trigger voltage of the MT2 112 terminal. In a first combination, the gate 110 and MT2 112 are positive relative to the MT1 108; in a second combination, the gate 110 is negative and the MT2 112 is positive relative to the MT1 108; in a third combination, the gate 110 and MT2 112 are negative relative to the MT1 108; and in a fourth combination, the gate 110 is positive and the MT2 is negative relative to the MT1 108.

[0031] In the first and second combinations, because the MT2 112 is positive, current flows from the MT2 112 through the p-type layer 106, the n-type layer 104, the p-type layer 102, and the n-type region 105 to the MT1 108. The n-type region 107 in the p-type layer 106 and attached to the MT2 112 is not involved.

[0032] In the third and fourth combinations, because the MT2 112 is negative, current flows from the MT1 108 through the p-type layer 102, the n-type region 103, the n-type layer 104, and the p-type layer 106 to the MT2 112. The n-type region 107 in the p-type layer 106 and attached to the MT2 112 is active. The n-type region 105 in the p-type layer 102 and attached to the MT1 108 is only involved in the initial triggering and not in the main current flow.

[0033] Figure 2 An exemplary unidirectional semiconductor device 200 is shown. The device 200 can be a SIDACTor device (e.g., available from Littelfuse, Inc. of Chicago, IL, USA). The device 200 can be configured to be formed in a semiconductor substrate, such as, for example, silicon. As can be appreciated, other substrate materials can be used.

[0034] The SIDACTor device 200 can be designed for suppressing overvoltage transients in various electronic equipment (e.g., telecommunication, data communication, etc. equipment) and can be capable of diverting up to 5000 A of current to ground within nanoseconds of reaching its breakdown voltage. Further, the SIDACTor device 200 can be used to protect against peak current pulses. The SIDACTor device 200 can be a solid state crowbar device that can be designed for protecting equipment located in harsh environments from overvoltage transient currents within nanoseconds.

[0035] The device 200 can be coupled to a MT1 or anode terminal 201 and a MT2 or cathode terminal 203. The terminals 201 and 203 can be made of an electrically conductive material, such as, for example but not limited to, copper, copper alloys, silver, metal alloys, etc., and / or any combination thereof.

[0036] Device 200 can include a substrate 204, a first base layer 202, a second base layer 206, and a third base layer 208. Substrate 204 can have a first type of polarity, such as N-type. Substrate 204 can be formed between first base layer 202 and second base layer 206 and third base layer 208. First base layer 202 and third base layer 208 can have a second type of polarity, such as P-type. Second base layer 206 can have a third type of polarity, such as N+-type. While shown as being based on an N-type substrate, SIDACTor device 200 can have a P-type substrate, with corresponding first, second, and third base layers disposed on opposite surfaces. First base layer 202 can form a P-N junction 205 with substrate 204. Second base layer 206 can form a P-N junction 207a with substrate 204, and third base layer 208 can form a P-N junction 207b with substrate 204. SIDACTor device 200 can be a unidirectional device, however, as can be appreciated, SIDACTor device 200 can be any other type of device.

[0037] First base layer 202 can include one or more regions 210 (a, b, c). Region(s) 210 can be formed using one or more dopants, such as, for example, phosphorus, boron, arsenic, gallium, and / or any other desired material. Each region 210 can be formed using the same dopant material and / or different dopant materials.

[0038] The combination of the polarity of region(s) 210, first base layer 202, and substrate 204 can result in an NPN configuration, which can facilitate a low clamping voltage for SIDACTor device 200. The polarity and / or depth / dopant concentration of region(s) 210 can be selected based on a desired switching current for device 200. Breakdown voltage can refer to the maximum reverse voltage that can be applied without causing an exponential increase in leakage current in device 200.

[0039] The dopant concentration in region(s) 210 can be uniform. Alternatively or additionally, the concentration can be non-uniform. Region(s) 210 can also have a predetermined thickness. The thickness of region(s) 210 can be less than the thickness of substrate 204. The thickness of region(s) 210 can also be less than the thickness of first base layer 202. As can be appreciated, any other type of doping of region(s) 210 is possible.

[0040] The additional doped region 212 can be configured to span at least a portion of the first base layer 202 and the substrate 204. The doped region 212 can be configured to have a polarity different from that of the first base layer 202 and the substrate 204. The polarity of the doped region 212 can be the same as that of region(s) 210. For example, the polarity of the doped region 212 can be N+ type. The doped region 212 can be configured to form an additional junction with the substrate 204 and the first base layer 202.

[0041] Furthermore, in some cases, equal portions of the doped region 212 may be distributed across the first base layer 202 and the substrate 204. Alternatively or additionally, for example, as Figure 2 As shown, substrate 204 may include a larger portion of doped region 212, and first base layer 202 may include a smaller portion of doped region 212. In an alternative example, substrate 204 may include a smaller portion of doped region 212, and first base layer 202 may include a larger portion of doped region 212.

[0042] The doped region 212 can be configured to define the breakdown voltage of the SIDACTor device 200. The presence of the doped region 212 (and other components of the SIDACTor device 200) allows the SIDACTor device 200 to operate at currents exceeding the switching current I. s When the value is 0, it switches from the OFF state to the ON state.

[0043] like Figure 2 As shown, the second substrate 206 and the third substrate 208 can be positioned adjacent to each other and below the substrate 204. The thickness of the second substrate 206 can be greater than the thickness of the third substrate 208. Alternatively or additionally, the thicknesses of substrates 206 and 208 can be equal, and / or the thickness of the second substrate 206 can be less than the thickness of the third substrate 208. The second substrate 206 and the third substrate 208 can also be coupled to a terminal layer 203, which can be disposed below layers 206 and 208. The first terminal 201 and the second terminal 203 can be made of conductive materials, such as, but not limited to, copper, copper alloys, silver, metal alloys, etc., and / or any combination thereof. Terminals 201 and 203 can be used to couple device 200 to one or more electronic components (e.g., printed circuit boards, etc.).

[0044] In some embodiments, during a first operating state, the SIDACTor device 200 can be configured to allow current to flow in a first direction, for example, current can flow from the first base layer 202 to the second base layer 206. In a second operating state, the SIDACTor device 200 can be configured to allow current to flow in a second direction, for example, current can flow from the third base layer 208 to the first base layer 202 and the doped regions 212 and regions 210 (a, b, c).

[0045] Figure 3a An example of a semiconductor device 300, for example, a SIDACTor device, is shown in accordance with some embodiments of the current subject matter. The device 300 can be configured to allow a breakdown voltage to occur at an edge region of the device, for example, the edge region can be an N+ doped region and a P+ doped region, where the value of the breakdown voltage can depend on the doping concentration of one or both of these regions. The region can also form a P-N junction (e.g., formed during a remaining thermal step of fabricating the SIDACTor device), which can also affect the value of the breakdown voltage. In some example non-limiting embodiments, the breakdown voltage value can be less than about 5V (e.g., uniformly distributed). As can be appreciated, any other desired breakdown voltage value can be used. The breakdown voltage value can be adjusted by adjusting the doping concentration of the N+ and P+. Further, the device 300 can be configured to provide a wide conduction region that can be distributed at the edge or periphery of the semiconductor device. This can allow the conduction current to not be overly concentrated, thereby improving the thermal conduction of the device and improving the current density.

[0046] Reference is made to Figure 3a , the SIDACTor device 300 can include a substrate 302, first base layers 304 (a, b), a second base layer 306, and a third base layer 308. The substrate 302 can be positioned between the base layers 304, 306 on one side (e.g., the MT2 terminal 303 side) and the base layer 308 on the other side (e.g., the MT1 terminal 301 side). The substrate 302 can have a first type of polarity, for example, N-type. The first base layer 304 and the third base layer 308 can have a second type of polarity, for example, P-type. The second base layer 306 can have a third type of polarity, for example, N+ type. The first base layer 304a can form a P-N junction 309a with the substrate 302. The first base layer 304b can form a P-N junction 309b with the substrate 302. The third base layer 308 can form a P-N junction 311 with the substrate 302.

[0047] As shown in Figure 3a , the second base layer 306 can be disposed between the first base layers 304a and 304b. The depth / thickness of the second base layer 306 can be greater than the depth / thickness of one or more of the first base layers 304.

[0048] The first base layer 304 and the second base layer 306 can be coupled to a terminal layer 303, which can be disposed below the layers 304, 306. The terminal layer 303 can be coupled to an MT2 terminal (e.g., cathode or anode). The third base layer 308 can be coupled to a terminal layer 301, which can be disposed above the layer 308. The terminal layer 301 can be coupled to an MT1 terminal (e.g., anode or cathode). The first terminal layer 301 and the second terminal layer 303 can be made of an electrically conductive material, such as, for example and without limitation, copper, copper alloy, silver, metal alloy, etc., and / or any combination thereof. The terminals that can be coupled with the terminal layers 301 and 303, respectively, can be used to couple the device 300 to one or more electronic components (e.g., printed circuit board (PCB) (not shown), etc.). Figure 3a

[0049] Although shown as being based on an N-type substrate, the SIDACTor device 300 can have a P-type substrate, with corresponding first, second, and third base layers disposed on opposite surfaces. In some embodiments, the SIDACTor device 300 can be a unidirectional device. As can be appreciated, the SIDACTor device 300 can be any other type of device.

[0050] The third base layer 308 can include one or more regions 310 (a, b, c, d). The region(s) 310 can be formed using one or more dopants, such as, for example, phosphorus, boron, arsenic, gallium, and / or any other desired material. Each region 310 can be formed using the same dopant material and / or a different dopant material. The region(s) 310 can have a polarity of N+ and can be designated as an emitter region. The polarity of each region 310 can be the same or different than the polarity of another region 310. Further, the doping concentration of each region 310 can be the same and / or different than the doping concentration of another region 310. The dopant concentration of the one or more regions 310 can be uniform. Alternatively or additionally, the concentration can be non-uniform. The region(s) 310 can also have a predetermined thickness. The thickness of the region(s) 310 can be less than the thickness of the third base layer 308. As can be appreciated, any other type of doping of the region(s) 310 (and / or any other component of the device 300) is possible.

[0051] In some embodiments, the combination of the polarity of the region(s) 310, the third base layer 308, and the substrate 302 can result in an NPN configuration. The doping and / or depth of the region(s) 310 can be selected depending on the desired configuration of the device 300. For example, the polarity and / or depth / doping concentration of the region(s) 310 can be selected based on the desired switching current of the device 300. ​

[0052] In some embodiments, one or more additional doped regions 312(a, b) and 314(a, b) can be disposed in the third base layer 308. The doped region(s) 312 can be disposed proximate to the terminal layer 301b and proximate to the region(s) 310. For example, the doped region 312a can be positioned proximate to the region 310a, and the doped region 312b can be positioned proximate to the region 310d. The doped regions 314(a, b) can also be disposed at the edges of the device 300, and can be positioned across at least one or more portions of the substrate 302 and the third base layer 308. Further, the doped regions 314 can also be positioned adjacent to and / or surrounding the terminal layer 301. Further, the doped region 314a can be positioned adjacent to the doped region 312a, and the doped region 314b can be positioned adjacent to the doped region 312b.

[0053] In some embodiments, the device 300 can also include one or more passivation layers 318(a, b). The passivation layers 318 can be configured to be disposed across and / or cover at least a portion of the terminal layer 301, the substrate 302, the third base layer 308, and the doped regions 312, 314. For example, the passivation layer 318a can be disposed and / or cover at least a portion of the terminal layer 301, the substrate 302, the third base layer 308, and the doped regions 312a, 314a at one edge. The passivation layer 318b can be disposed and / or cover at least a portion of the terminal layer 301, the substrate 302, the third base layer 308, and the doped regions 312b, 314b at the other edge.

[0054] The doped regions 312 and 314 can be configured to have different polarities. The doped region(s) 312 can have the same polarity as the third base layer 308, e.g., P-type. The doped regions 314 can have an n+ type polarity. The doped regions 312 and 314 can also be configured to create additional P-N junctions 316(a, b). For example, the regions 312a and 314a can be configured to create the P-N junction 316a, and the regions 312b and 314b can be configured to create the P-N junction 316b.

[0055] Doped regions 312 and 314 can be configured to control the breakdown voltage of the SIDACTor device 300. The presence of doped regions 312 and 314 (and other components of the device 300) and the corresponding PN junction 316 allows the device 300 to control the value of the breakdown voltage. This value can be controlled by changing the doping concentration of one or more regions 312, 314. As can be understood, each region 312 and / or 314 can have the same and / or different corresponding doping concentrations. The configuration of the device 300 can allow it to provide a larger conductive region, which can be distributed at the edge or periphery of the semiconductor device, thereby dispersing the conduction current and improving the thermal conductivity and current density of the device.

[0056] In some implementations, during one operating state, the SIDACTor device 300 can be configured to allow current to flow in a first direction 305(a, b). For example, current can flow from one or more first substrates 304 to a third substrate 308 (e.g., current flows from the first substrate 304a to the third substrate 308 and regions 310a, 310b, 312a, 314a in direction 305a, and current flows from the first substrate 304b to the third substrate 308 and regions 310c, 310d, 312b, 314b in direction 305b). During another operating state, the device 300 can be configured to allow current to flow in another direction 307. In this direction, current can flow from the third substrate 308 to the second substrate 306.

[0057] Figure 3b Another example of a semiconductor device 350 according to some embodiments of the present topic is shown, such as a SIDACTor device. Device 350 can be used with... Figure 3a The device shown is similar to 300. For example... Figure 3b As shown, the SIDACTor device 350 may include a substrate 322, a first substrate 324 (a, b), a second substrate 326, and a third substrate 328. The substrate 322 may be positioned between substrates 324 and 326 on one side (e.g., the MT2 terminal 323 side) and substrate 328 on the other side (e.g., the MT1 terminal 321 side). The substrate 322 may have a first type of polarity, such as N-type. The first substrate 324 and the third substrate 328 may have a second type of polarity, such as P-type. The second substrate 326 may have a third type of polarity, such as N+ type. The first substrate 324a may form a PN junction 329a with the substrate 322. The first substrate 324b may form a PN junction 329b with the substrate 322. The third substrate 328 may form a PN junction 331 with the substrate 322.

[0058] like Figure 3bAs shown, a second base layer 326 can be disposed between first base layers 324a and 324b. The depth / thickness of the second base layer 326 can be greater than the depth / thickness of one or more first base layers 324.

[0059] First base layer 324 and second base layer 326 can be coupled to terminal layer 323, which can be disposed below layers 324 and 326. Terminal layer 323 can be coupled to MT2 terminal (e.g., cathode or anode). Third base layer 328 can be coupled to terminal layer 321, which can be disposed above layer 328. Terminal layer 321 can be coupled to MT1 terminal (e.g., anode or cathode). First terminal layer 321 and second terminal layer 323 can be made of conductive material, such as, but not limited to, copper, copper alloys, silver, metal alloys, etc., and / or any combination thereof. Terminals that can be coupled to terminal layers 321 and 323 respectively can be used to couple device 350 to one or more electronic components (e.g., printed circuit boards). Figure 3b (not shown in the image) etc.

[0060] and Figure 3a Similar to the illustrated device 300, although shown based on an N-type substrate, device 350 may have a P-type substrate, wherein corresponding first, second, and third substrates are disposed on opposing surfaces. In some embodiments, device 350 may be a unidirectional device. As will be understood, device 350 may be any other type of device.

[0061] The third substrate 328 may include one or more regions 330 (a, b, c, d). Regions 330 may be formed using one or more dopants, such as, for example, phosphorus, boron, arsenic, gallium, and / or any other desired material. Each region 330 may be formed using the same dopant material and / or different dopant materials. Regions 330 may have an N+ polarity and may be designated as emitter regions. The polarity of each region 330 may be the same as or different from that of another region 330. Furthermore, the doping concentration of each region 330 may be the same as and / or different from that of another region 330. The doping concentration of the one or more regions 330 may be uniform. Alternatively or additionally, the concentration may be non-uniform. Regions 330 may also have a predetermined thickness. The thickness of the one or more regions 330 may be less than the thickness of the third substrate 328. As will be understood, any other type of doping of the one or more regions 330 (and / or any other component of device 350) is possible.

[0062] In some implementations, the combination of polarities of one or more regions 330, the third base layer 328, and the substrate 322 can produce an NPN configuration. The doping and / or depth of one or more regions 330 can be selected depending on the desired configuration of the device 350. For example, the polarity and / or depth / doping concentration of one or more regions 330 can be selected based on the desired switching current of the device 350.

[0063] In some implementations, with Figure 3a Similarly, one or more additional doped regions 332(a, b) and 334(a, b) can be disposed in the third base layer 328. However, as Figure 3b As shown, one or more doped regions 332 can be positioned close to the corresponding passivation layers 338 (a, b) and region 330. One or more doped regions 332 can be entirely disposed within the third substrate 328, and one or more doped regions 334 can be positioned across the third substrate 328 and the substrate 322. For example, a larger portion of the one or more doped regions 334 can be disposed within the substrate 322, while a smaller portion of the one or more doped regions can be disposed within the third substrate 328. As can be understood, the arrangement of the one or more doped regions 334 and / or 332 can be selected based on the desired configuration of the device 350.

[0064] In some embodiments, doped region 332a may be positioned near region 330a, and doped region 332b may be positioned near region 330d. One or more passivation layers 338(a, b) may be configured to cover doped regions 332 and 334. For example, passivation layer 338a may be configured to cover doped regions 332a and 334a, and passivation layer 338b may be configured to cover doped regions 332b and 334b. Doped regions 332(a, b) and 334(a, b) may also be located at the edge of device 350.

[0065] and Figure 3a Similar to the device 300 shown, one or more doped regions 332 and 334 can be configured to have different polarities. The polarity of one or more doped regions 332 can be the same as the polarity of the third base layer 328, for example, P-type. The polarity of one or more doped regions 334 can be n+ type. Doped regions 332 and 334 can also be configured to create additional PN junctions 336 (a, b). For example, regions 332a and 334a can be configured to create PN junction 336a, and regions 332b and 334b ​​can be configured to create PN junction 336b.

[0066] The operation of device 350 can be with Figure 3aOperation of the device 300 shown is similar, e.g., during one operational state, the SIDACTor device 350 can be configured to allow current to flow in a first direction 325 (a, b). For example, current can flow from the first base layer(s) 324 to the third base layer 328 (e.g., current flows in direction 325a from the first base layer 324a to the third base layer 328 and regions 330a, 330b, 332a, 334a, and current flows in direction 325b from the first base layer 324b to the third base layer 328 and regions 330c, 330d, 332b, 334b). During another operational state, the device 350 can be configured to allow current to flow in another direction 327. In this direction, current can flow from the third base layer 328 to the second base layer 326.

[0067] Figure 4 is Figure 3a The SIDACTor device 300 (and / or Figure 3b The device 350) shown is a top view. The device 300 can include current conduction regions 402 and 404. The current conduction region 402 can correspond to a SIDACTor current conduction region. This corresponds to Figure 5 The current conduction region 404 can correspond to a diode current conduction region. This corresponds to the reverse direction of the I-V curve 500 shown. Figure 5 The forward direction of the I-V curve 500 shown.

[0068] Figure 6 An exemplary process 600 for fabricating a transient voltage suppressor device is shown, in accordance with some embodiments of the current subject matter. The process 600 can be used to fabricate, for example, the SIDACTor device 300 shown and / or Figure 3a The device 350 shown. Figure 3b

[0069] At 602, a substrate (e.g., the substrate 302) can be provided. At 604, a first base layer (e.g., the layer(s) 304), a second base layer (e.g., the layer 306), and a third base layer (e.g., the layer 308) can be provided. The substrate can be disposed between the first base layer and the second base layer and the third base layer.

[0070] ​At 604, one or more first doped regions (e.g., regions 312) and one or more second doped regions (e.g., regions 314) can be formed. The first doped regions can be formed in the third base layer, and at least a portion of the one or more second doped regions can be formed in the substrate. In some embodiments, at least one of the one or more first doped regions and the one or more second doped regions can be doped using one or more dopants. The one or more dopants can include at least one of phosphorus, boron, arsenic, gallium, and any combination thereof. The one or more first doped regions and the one or more second doped regions can have a respective predetermined concentration of the one or more dopants. Each of the one or more first doped regions and the one or more second doped regions can have a respective predetermined depth. The semiconductor device can be characterized by a breakdown voltage, where the breakdown voltage of the semiconductor device can be determined as a function of at least one of the predetermined concentration of the one or more dopants, the predetermined depth of the one or more first doped regions, the predetermined depth of the one or more second doped regions, and any combination thereof. Each of the one or more first doped regions and the one or more second doped regions can have the same concentration of the one or more dopants. Each of the one or more first doped regions and the one or more second doped regions can have different concentrations of the one or more dopants.

[0071] At 606, one or more junctions (e.g., junctions 316) can be formed between the one or more first doped regions and the one or more second doped regions.

[0072] At 608, a first terminal layer (e.g., layer 301) can be coupled to the third base layer, and a second terminal layer (e.g., layer 303) can be coupled to the first base layer and the second base layer.

[0073] At 610, one or more passivation layers (e.g., layers 318) can be coupled at one or more edges of the semiconductor device. The passivation layers can be configured to be disposed across at least one of: one or more portions of the substrate, one or more portions of the third base layer, one or more portions of the one or more first doped regions, one or more portions of the one or more second doped regions, and any combination thereof.

[0074] The components and features of the devices described above can be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs), logic gates and / or single chip architectures. Further, the features of the devices can be implemented using microcontrollers, programmable logic arrays and / or microprocessors or any combination of the foregoing, where appropriate. It will be recognized that the hardware, firmware and / or software elements of the devices can be collectively or individually referred to as "logic" or "circuit."

[0075] It will be recognized that the exemplary devices illustrated in the block diagrams described above can represent a functional description of any number of potential implementations. Thus, the division of functionality between the blocks depicted in the flowcharts, omission of blocks, or addition of blocks is not to be construed as requiring implementation in any particular arrangement. Further, the division of functionality between the blocks depicted in the flowcharts, omission of blocks, or addition of blocks is not to be construed as requiring hardware, circuitry, software and / or elements to be necessarily present in any particular embodiment.

[0076] Some embodiments can be described using the expression "one or more of followed by a list of items. The term "and / or" can be used in the disclosure to describe either explicit instances or the intentional inclusion of multiple alternatives. For example, the expression "one or more of A and B" is intended to mean: "at least one A, or at least one B, or at least one A and at least one B." Likewise, the expression "two or more of A, B and C" is intended to mean: "at least one A, at least one B, at least one C, or at least one A and at least one B, or at least one A and at least one C, or at least one B and at least one C, or at least one A and at least one B and at least one C." The expression "one, two, three, or four of A, B, C and D" is intended to mean: "at least one A, at least one B, at least one C, at least one D, or at least one A and at least one B, or at least one A and at least one C, or at least one A and at least one D, or at least one B and at least one C, or at least one B and at least one D, or at least one C and at least one D, or at least one A and at least one B and at least one C and at least one D."

[0077] It is emphasized that the summary of the disclosure provided herein is intended only as an overview of the technical disclosure and does not limit the scope of the claims or the content thereof in any way. Further, in the preceding detailed description, for purposes of convenience and clarity, directional terms are used, such as top, bottom, forward, rear, front, back, left and right, as well as structural terms, such as on, above, below, up, under, next, over, above, below, etc., to describe the relative placement and orientation of components to each other as presented in the drawings. Such terminology is for purposes of description only. There is no intention to be bound by the terms of expression. In addition, it is to be understood that the use of certain terms, for example, "including", "containing", "comprising", "having" and / or "encompassing" is used herein to permit a broad interpretation such that the description is not limited to the recited elements. Thus, the scope of the disclosure should be determined by the appended claims and their legal equivalents, rather than by the description in the summary of the disclosure or the detailed description.

[0078] For the sake of convenience and clarity, terms such as "top", "bottom", "upper", "lower", "vertical", "horizontal", "lateral", "transverse", "radial", "inner", "outer", "left", and "right" can be used herein to describe relative positions and orientations of features and components, each relative to the geometric shapes and orientations of other features and components appearing in the perspective views, exploded perspective views, and cross-sectional views provided herein. The terms are not intended to be limiting, and include the specifically mentioned words, derivatives thereof, and words of similar import.

[0079] What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and / or methods, but one of ordinary skill in the art can recognize that many further combinations and permutations of the disclosed architecture are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0080] The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application can claim the disclosed subject matter in different ways and generally can include any set of one or more limitations as variously disclosed herein in various ways and as otherwise suggested by the examples herein.

[0081] All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, anterior, posterior, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are only used for identification purposes to aid the reader’s understanding of the present disclosure, and do not create limitations, particularly as to the position, orientation, or use of the disclosure. Connection references (e.g., attached, coupled, connected, and joined) are to be construed broadly and will be

[0082] Further, identification references (e.g., primary, secondary, first, second, third, fourth, and the like) are not intended to denote importance or superiority, but to distinguish one feature from another. The drawings are for purposes of illustration only and the dimensions, positions, order and relative sizes reflected in the drawings attached hereto can vary.

[0083] The scope of the disclosure is not intended to be limited to the particular embodiments described herein. Indeed, a variety of embodiments of the disclosure and modifications thereof will be apparent to the skilled artisan in light of the foregoing description and the accompanying drawings. Such other embodiments and modifications are therefore intended to fall within the scope of the disclosure. Further, the disclosure has been described herein in the context of particular implementations for particular purposes in particular environments. It will be recognized by those of ordinary skill in the art, however, that the utility of the disclosure is not limited to this context and that the disclosure can be advantageously implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below are to be interpreted in the broadest and most liberal manner consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a first base layer, a second base layer, and a third base layer, wherein the substrate is disposed between the first base layer and the second base layer and the third base layer; one or more first doped regions and one or more second doped regions, wherein the one or more first doped regions are disposed in the third base layer and at least a portion of the one or more second doped regions are disposed in the substrate; and wherein the one or more first doped regions and the one or more second doped regions form one or more junctions configured to increase current conduction of the semiconductor device.

2. The semiconductor device according to claim 1, wherein The substrate is an N-type substrate.

3. The semiconductor device of claim 2, wherein: the first base layer and the third base layer are p-base layers; and the second base layer is an N+ base layer.

4. The semiconductor device according to claim 3, wherein The semiconductor device further comprises one or more first regions disposed in the third base layer.

5. The semiconductor device of claim 3, wherein The one or more first regions are N+ type regions.

6. The semiconductor device of claim 1, wherein The one or more first doped regions are p-type regions and the one or more second doped regions are n+ type regions.

7. The semiconductor device of claim 6, wherein, The one or more junctions are P-N junctions.

8. The semiconductor device of claim 1, wherein The semiconductor device further comprises a first terminal layer coupled to the third base layer and a second terminal layer coupled to the first base layer and the second base layer.

9. The semiconductor device of claim 1, wherein The semiconductor device further comprises one or more passivation layers disposed at one or more edges of the semiconductor device.

10. The semiconductor device of claim 9, wherein, The one or more passivation layers are configured to be disposed across at least one of: one or more portions of the substrate, one or more portions of the third base layer, one or more portions of the one or more first doped regions, one or more portions of the one or more second doped regions, and any combination thereof.

11. The semiconductor device of claim 1, wherein The semiconductor device is a SIDA CTor device.

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