Solar cell

Abstract

The utility model relates to the photovoltaic field, and discloses a solar cell, which comprises a silicon substrate; a patterned first doped silicon layer; the first doped silicon layer is located on at least one surface of the silicon substrate, so that a part of the surface is provided with the first doped silicon layer, and a part of the surface is not provided with the first doped silicon layer; the first doped silicon layer comprises a grid line region and a non-grid line region, and at least part of the non-grid line region is different from the grid line region in extension direction so as to intersect with the grid line region; a gate line; the grid lines comprise fine grid lines located in the grid line area. The first doped silicon layer comprises the grid line region and the non-grid line region, carrier transmission paths are increased, the transmission performance of carriers on the first doped silicon layer is better, the carrier transmission paths are optimized, the series resistance is smaller, and the battery conversion efficiency of the battery adopting the Poly Finger technology is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaics, in particular to a solar cell. BACKGROUND

[0002] As a green new energy, solar energy has many advantages such as inexhaustibility, cleanliness and environmental protection. A solar cell is a semiconductor device that can convert solar energy into electrical energy, thereby alleviating the energy crisis.

[0003] For example, a TOPCon (Tunnel Oxide Passivating Contact) cell prepares an ultra-thin silicon oxide layer on the back of a silicon substrate, and then deposits a doped polysilicon layer, thereby forming a passivation contact structure on the back, which can effectively reduce surface recombination and metal contact recombination. In order to reduce the problem of serious parasitic absorption of the polysilicon layer on the back of the TOPCon cell, the Poly Finger technology (i.e., only the metal area is provided with a polysilicon layer, and the non-metal area is not provided with a polysilicon layer) can be used. Carriers can only be transported in the direction (vertical direction) in which the carriers are directed to the fine grid lines, resulting in problems such as low FF and decreased short-circuit current gain of the TOPCon cell, which limits the efficiency improvement effect.

[0004] Therefore, how to further improve the conversion efficiency of the cell using the Poly Finger technology is a problem to be solved by those skilled in the art. CONTENT OF THE INVENTION

[0005] The purpose of the present application is to provide a solar cell to further improve the conversion efficiency of the cell using the Poly Finger technology.

[0006] To solve the above technical problems, the present application provides a solar cell, comprising:

[0007] a silicon substrate;

[0008] a patterned first doped silicon layer; the first doped silicon layer is located on at least one surface of the silicon substrate, so that part of the surface is provided with the first doped silicon layer and part of the surface is not provided with the first doped silicon layer; the first doped silicon layer comprises a grid line area and a non-grid line area, at least part of the non-grid line area is different from the extension direction of the grid line area to intersect with the grid line area;

[0009] a grid line; the grid line comprises a fine grid line located in the grid line area.

[0010] Optionally, the short side size of the non-grid line area ranges from 5 μm to 1000 μm.

[0011] Optionally, a ratio of an area of the first doped silicon layer to an area of the silicon substrate without the first doped silicon layer is not greater than 2.

[0012] Optionally, a doping concentration of the first doped silicon layer away from the silicon substrate is greater than a doping concentration of the first doped silicon layer close to the silicon substrate.

[0013] Optionally, further comprising a passivation layer covering a surface of the first doped silicon layer away from the silicon substrate and a part of the silicon substrate without the first doped silicon layer.

[0014] Optionally, a ratio of a short side dimension of the fine gate line to a short side dimension of the gate line region where the fine gate line is located ranges from 1:1 to 1:15.

[0015] Optionally, the short side dimension of the fine gate line is 5 μm to 50 μm.

[0016] Optionally, the short side dimension of the gate line region where the fine gate line is located is 5 μm to 750 μm.

[0017] Optionally, a part of the silicon substrate with the first doped silicon layer and a part of the silicon substrate without the first doped silicon layer form a step.

[0018] Optionally, a roughness of the part of the silicon substrate with the first doped silicon layer and the part of the silicon substrate without the first doped silicon layer is different.

[0019] Optionally, when both surfaces of the silicon substrate are provided with the first doped silicon layer, doping types of the first doped silicon layers of the two surfaces are different.

[0020] Optionally, when one surface of the silicon substrate is provided with the first doped silicon layer, a doping type of the first doped silicon layer is the same as or different from a doping type of the silicon substrate.

[0021] Optionally, the passivation layer is at least one of an aluminum oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

[0022] Optionally, the passivation layer is a single-layer passivation layer.

[0023] Optionally, the passivation layer is a multi-layer passivation layer.

[0024] Optionally, the passivation layer comprises an aluminum oxide layer and a silicon nitride layer stacked together, wherein the aluminum oxide layer is disposed close to the silicon substrate; a thickness of the aluminum oxide layer is 3 nm to 7 nm; and a thickness of the silicon nitride layer is 70 nm to 90 nm.

[0025] Optionally, the height difference between the part area provided with the first doped silicon layer and the part area not provided with the first doped silicon layer is 1-5 μm.

[0026] Optionally, the gate line further comprises a main gate line located in the gate line area; the main gate line is electrically connected with the fine gate line.

[0027] Optionally, the size of the gate line area where the main gate line is located is not less than the size of the gate line area where the fine gate line is located.

[0028] Optionally, the first doped silicon layer is in a mesh structure, wherein the gate line area where the main gate line is located extends laterally, the gate line area where the fine gate line is located extends longitudinally; the non-gate line area extends laterally and at least one end thereof intersects with the gate line area where the fine gate line is located.

[0029] Optionally, the main gate line comprises a connecting line and a pad area; two or more pad areas are connected by the connecting line.

[0030] Optionally, the non-gate line area is arranged in the area not provided with the gate line area where the main gate line is located.

[0031] Optionally, the non-gate line area is arranged in parallel with the gate line area where the main gate line is located.

[0032] Optionally, the size of the side of the fine gate line close to the main gate line is greater than the size of the side of the fine gate line away from the main gate line.

[0033] Optionally, the size of the gate line area where the pad area is located is greater than the size of the gate line area where the connecting line is located.

[0034] Optionally, the size of the gate line area where the connecting line is located is greater than the size of the gate line area where the fine gate line is located.

[0035] Optionally, when the non-gate line area is arranged in parallel with the gate line area where the main gate line is located, 1-5 sub-non-gate line areas are arranged independently between two adjacent main gate lines, and the non-gate line area comprises the sub-non-gate line area.

[0036] Optionally, the short side size of the connecting line is 200-600 μm.

[0037] Optionally, the short side size of the pad area is 800-1600 μm.

[0038] Optionally, a first tunneling layer is arranged between the first doped silicon layer and the silicon substrate.

[0039] A second tunneling layer, a second doped silicon layer and a third tunneling layer are arranged between the first doped silicon layer and the silicon substrate; the second tunneling layer is arranged close to the silicon substrate, and the third tunneling layer is arranged close to the first doped silicon layer.

[0040] A third doped silicon layer is arranged between the first doped silicon layer and the silicon substrate.

[0041] An intrinsic silicon layer is arranged between the first doped silicon layer and the silicon substrate, and the first doped silicon layer is amorphous silicon.

[0042] Optionally, the thickness of the first tunneling layer is 1nm-2.2nm.

[0043] The thickness of the first doped silicon layer is 90nm-200nm.

[0044] Optionally, the thickness of the second tunneling layer is 1.5nm-2.2nm, the thickness of the second doped silicon layer is 20nm-40nm; the thickness of the third tunneling layer is 0.5nm-1.2nm, and the thickness of the first doped silicon layer is 110nm-130nm.

[0045] The second doped silicon layer is an N-type doped layer or a P-type doped layer.

[0046] The second tunneling layer and the second doped silicon layer cover the entire surface, and the third tunneling layer is arranged flush with the first doped silicon layer or the second tunneling layer, the second doped silicon layer and the third tunneling layer are arranged flush with the first doped silicon layer.

[0047] Optionally, the third doped silicon layer is an N-type doped layer or a P-type doped layer.

[0048] A fourth tunneling layer is arranged between the third doped silicon layer and the silicon substrate.

[0049] A fifth tunneling layer is arranged between the third doped silicon layer and the first doped silicon layer.

[0050] The solar cell provided in the application comprises: a solar cell, characterized by comprising: a silicon substrate; a patterned first doped silicon layer; the first doped silicon layer is arranged on at least one surface of the silicon substrate, so that part of the surface is provided with the first doped silicon layer, and part of the surface is not provided with the first doped silicon layer; the first doped silicon layer comprises a grid line area and a non-grid line area, at least part of the non-grid line area is different from the extension direction of the grid line area to intersect with the grid line area; a grid line; the grid line comprises a fine grid line arranged in the grid line area.

[0051] It can be seen that the solar cell in the application includes a silicon substrate, a patterned first doped silicon layer and a grid line, the first doped silicon layer includes a grid line area and a non-grid line area. At least part of the non-grid line area is different from the extension direction of the grid line area, so as to intersect with the grid line area. The carriers between the grid line areas can be transmitted not only to the fine grid lines, but also to the first doped silicon layer in the non-grid line area and then to the fine grid lines. Therefore, in the application, the first doped silicon layer includes a grid line area and a non-grid line area, the carrier transmission path is increased, the carrier transmission performance on the first doped silicon layer is better, the carrier transmission path is optimized, the series resistance is smaller, and the cell conversion efficiency of the cell using the Poly Finger technology is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0053] Figure 1 It is a top view of a solar cell in the prior art;

[0054] Figure 2 It is a top view of a solar cell provided by an embodiment of the application;

[0055] Figure 3 It is a schematic diagram of the carrier transmission path on the solar cell provided by an embodiment of the application;

[0056] In the figure, 1 is a silicon substrate, 2 is a first doped silicon layer, 3 is a fine grid line, 4 is a main grid line, 5 is a removal area, 21 is a grid line area, 22 is a non-grid line area, 211 is a main grid line area, and 212 is a fine grid line area. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the technical solutions of the application, the application will be further described in detail below with reference to the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0058] In the following description, a lot of specific details are set forth in order to provide a thorough understanding of the present application, however, the present application can be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the present application, therefore, the present application is not limited to the specific embodiments disclosed below.

[0059] As described in the background section, as shown in Figure 1 , the current solar cell using the Poly Finger technology, the carriers can only be transmitted in the direction of the carriers towards the fine grid lines (vertical direction), which brings the problem of low FF and short-circuit current gain caused by the problem of carrier lateral transmission.

[0060] Therefore, the present application provides a solar cell, please refer to Figure 2 , comprising:

[0061] a silicon substrate 1;

[0062] a patterned first doped silicon layer 2; it is located on at least one surface of the silicon substrate 1, so that part of the area of the surface is provided with the first doped silicon layer 2, and part of the area (i.e. the removal area 5 below) is not provided with the first doped silicon layer 2; the first doped silicon layer 2 includes a grid line area 21 and a non-grid line area 22, at least part of the non-grid line area 22 is different from the extension direction of the grid line area 21 to intersect with the grid line area 21;

[0063] a grid line; the grid line includes a fine grid line 3 located in the grid line area 21.

[0064] It is worth noting that the silicon substrate 1 can be an N-type silicon substrate or a P-type silicon substrate. The resistivity of the silicon substrate 1 can range from 0.6Ω·cm to 1.4Ω·cm. For example, the resistivity of the silicon substrate 1 can be 0.6Ω·cm, 0.8Ω·cm, 1.0Ω·cm, 1.2Ω·cm, 1.4Ω·cm, etc.

[0065] In the present application, the first doped silicon layer 2 can be a doped polysilicon layer, a doped microcrystalline silicon layer or a doped amorphous silicon layer. The crystal state of the first doped silicon layer 2 on different surfaces can be the same or different. The present application does not limit the setting of the first doped silicon layer 2 on the silicon substrate 1. And the battery structure of the present application can be a finished battery or an intermediate product of the battery. For the sake of explanation, the front surface of the silicon substrate 1 is the surface facing the sunlight, and the back surface of the silicon substrate 11 is opposite to the front surface, but it is not limited by the present application.

[0066] As an implementation manner, when the two surfaces (i.e. the front surface and the back surface) of the silicon substrate 1 are both provided with the first doped silicon layer 2, the doping types of the first doped silicon layer 2 of the two surfaces are different. Among them, one first doped silicon layer 2 can be an N-type doped layer, and the other first doped silicon layer 2 can be a P-type doped layer. In this embodiment, when the two surfaces of the silicon substrate 1 are both provided with the patterned first doped silicon layer 2, the front surface mainly reduces the shading effect, the back surface mainly reduces the parasitic absorption (at this time, if the battery is a double-sided battery, the shading effect is also reduced) and optimizes the carrier transport path, thereby improving the battery efficiency. Of course, in other embodiments, the back surface of the silicon substrate 1 can be provided with the patterned first doped silicon layer 2 of the present application, and the front surface can be provided with the existing Poly Finger technology (i.e. only the first doped silicon layer 2 is provided in the metal area, and the non-metal area is not provided with the first doped silicon layer 2), which should also be within the protection scope of the present application. Of course, in other embodiments, the front surface of the silicon substrate 1 can be provided with the patterned first doped silicon layer 2 of the present application, and the back surface can be provided with the existing Poly Finger technology (i.e. only the first doped silicon layer 2 is provided in the metal area, and the non-metal area is not provided with the first doped silicon layer 2), which should also be within the protection scope of the present application.

[0067] As another implementation manner, when one surface of the silicon substrate 1 is provided with the first doped silicon layer 2, the doping type of the first doped silicon layer 2 is the same as or different from the doping type of the silicon substrate 1. The first doped silicon layer 2 can be an N-type doped layer or a P-type doped layer.

[0068] It should be noted that when the first doped silicon layer 2 is only provided on the back surface of the silicon substrate 1, the front surface of the silicon substrate 1 can also include a diffusion layer and a gate line. The gate line on the front surface can include a main gate line 4 and a fine gate line 3, or the gate line on the front surface only includes the fine gate line 3. Similarly, when the first doped silicon layer 2 is only provided on the front surface of the silicon substrate 1, the back surface of the silicon substrate 1 can also include a diffusion layer and a gate line. The gate line on the back surface can include a main gate line 4 and a fine gate line 3, or the gate line on the back surface only includes the fine gate line 3. In this embodiment, the diffusion layer can be a doped layer formed on the silicon substrate 1, or a deposited doped layer.

[0069] It should be noted that the first doped silicon layer 2 and the silicon substrate 1 can form a homojunction or a heterojunction, form a PN junction or a high-low junction, and can also form a high-doped area with a high doping concentration in the SE.

[0070] In this embodiment, the solar cell is provided with the first doped silicon layer 2 in the gate line area 21 and the non-gate line area 22, and the gate line area 21 and the non-gate line area 22 intersect. It can be understood that the first doped silicon layer 2 outside the gate line area 21 and the non-gate line area 22 is removed. In order to facilitate the description, the area where the first doped silicon layer 2 is removed can be referred to as a removal area 5.

[0071] The carrier has better transmission performance on the first doped silicon layer 2 of the application, and as shown in Figure 3 for the carrier at the position corresponding to the removal area 5, not only can be transmitted to the fine grid line 3 up and down along Figure 3 , but also can be transmitted to the left and right along Figure 3 , and transmitted to the first doped silicon layer 2 of the non-grid line area 22, and then transmitted to the fine grid line 3, that is, the transmission path of the carrier in this embodiment is increased compared with the existing Poly Finger technology. Experiments show that the series resistance of the battery of the application is smaller, and the conversion efficiency of the solar cell is further improved.

[0072] In practical application, in order to ensure the battery efficiency and take into account the processing technology (collapse during grid line printing or slotting, removing poly process, etc.), the existing Poly Finger technology often retains the relatively wide size of the polysilicon layer corresponding to the grid line, but the carrier can only be transmitted in the direction of the fine grid line, and the transmission path of the carrier is not increased, which limits the efficiency improvement effect, and the too wide polysilicon layer also has parasitic absorption, shading and other adverse factors. The first doped silicon layer 2 of the non-grid line area in this embodiment also has the above-mentioned adverse factors, but it can increase the transmission path of the carrier, thereby reducing the series resistance of the battery, and further realizing the efficiency improvement of the battery conversion efficiency, and the efficiency improvement effect is better than that of increasing the polysilicon width. Experiments show that when the first doped silicon layer 2 with the same area (the first doped silicon layer 2 accounts for 40-60% of the back surface) is set on the back surface of the TOPCon battery, compared with the existing Poly Finger technology (i.e. only the first doped silicon layer 2 is set in the metal area, and the first doped silicon layer 2 is not set in the non-metal area), the FF of the application is improved by 0.10%, and the battery conversion efficiency is improved by 0.058%.

[0073] The size of the non-grid line area 22 in this embodiment is not limited and can be set as needed.

[0074] As an implementable manner, the short side size of the non-grid line area 22 ranges from 5μm to 1000μm. For example, the short side size of the non-grid line area 22 is 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, or any value within the range. Figure 2The short side size (i.e. the size in the horizontal direction) can be 5 microns, 50 microns, 100 microns, 200 microns, 400 microns, 600 microns, 800 microns, 1000 microns, etc. Preferably, it is 20-1000 microns. It should be noted that the short side size in the embodiment can be understood as the size in the direction perpendicular to the extension direction of the non-grid line region 22. Of course, in other embodiments, if the size in the extension direction of the non-grid line region 22 is smaller than the size in the direction perpendicular thereto, the short side size can also be understood as the size in the extension direction of the non-grid line region 22. In actual applications, the outer contour shape of the non-grid line region 22 can be a regular pattern or an irregular pattern, and the specific design is subject to the design of the patterned first doped silicon layer 2, which is not limited in the present application. The non-grid line region 22 can be arranged perpendicularly or at an angle to the grid line region 21, or can extend towards the grid line region 21 after being parallel and then bent. Of course, in order to increase the transmission path, the extension direction of the non-grid line region 22 is preferably not parallel to the grid line region 21, but is arranged obliquely or perpendicularly so as to be in contact with the grid line region 21 as much as possible. Since the fine grid lines 3 are generally arranged in parallel and spaced apart, the non-grid line region 22 is preferably arranged to be in contact with all the grid line regions 211 corresponding to the fine grid lines 3 as much as possible, so as to transmit carriers to the fine grid lines 3 in more ways. For example, in a TOPCon cell, the grid line regions 211 corresponding to the fine grid lines 3 have removal regions 5, and the non-grid line region 22 is arranged to be in contact with the grid line regions 211 corresponding to each fine grid line 3 as much as possible in the extension direction. Preferably, the non-grid line region 22 is in contact with more than 30% of the grid line regions 211 corresponding to the fine grid lines 3. Preferably, the non-grid line region 22 is in contact with more than 80% of the grid line regions 211 corresponding to the fine grid lines 3. The specific contact mode and contact ratio are subject to actual production requirements, which are not limited in the present application.

[0075] It should be noted that when the short side size of the non-grid line region 22 is less than 5 microns, the non-grid line region 22 is easily corroded by chemicals and cannot be completely retained, thereby failing to achieve the effect of improving FF and short-circuit current. When the width of the non-grid line region 22 is greater than 1000 microns, the area of the non-grid line region 22 is too large, which may result in a decrease in short-circuit current.

[0076] It should be noted that the size relationship between the fine grid line 3 and the grid line region 21 where the fine grid line 3 is located is not limited in the present embodiment. However, the size of the grid line region 21 where the fine grid line 3 is located is preferably not less than the size of the fine grid line 3, so as to increase the implementation of the processes such as the formation of the patterned first doped silicon layer 2 and the preparation of the grid line, and to improve the processing error tolerance of the production line.

[0077] As an implementable manner, the ratio of the short side size of the fine grid line 3 to the short side size of the grid line area 21 where the fine grid line 3 is located ranges from 1:1 to 1:15, which can make the battery efficiency optimal and solve the problems of (a) collapse of grid line printing, (b) precision deviation of printing, (c) deformation of printing screen, (d) difference between the poly design width and the actual process control, (e) poor carrier transmission capacity of the first doped silicon layer 2 when it is too narrow, and high parasitic absorption when it is too wide. Preferably, the ratio of the short side size of the fine grid line 3 to the short side size of the grid line area 21 where the fine grid line 3 is located ranges from 1:1 to 1:8.

[0078] As an implementable manner, the short side size of the fine grid line 3 can be 5 μm to 50 μm; and / or, preferably, the short side size of the grid line area 21 where the fine grid line 3 is located is 5 μm to 750 μm.

[0079] Further preferably, in consideration of the above factors, the short side size of the fine grid line 3 can be 6 μm to 30 μm, and the short side size of the grid line area 21 where the fine grid line 3 is located is 10 μm to 300 μm.

[0080] It should be noted that the short side size of the fine grid line 3 can be understood as the width of the fine grid line 3, that is, the size perpendicular to the extension direction of the fine grid line 3. In actual application, the extension length of the fine grid line 3 is generally greater than its width, so the short side size can be understood as the width size. Of course, the same situation also applies to the main grid line 4 (see below). The ratio of the area of the first doped silicon layer 2 to the area of the surface of the silicon substrate 1 where the first doped silicon layer 2 is located is not limited in the present embodiment.

[0081] In an embodiment of the present application, the ratio of the area of the first doped silicon layer 2 to the area of the surface where the first doped silicon layer 2 is not provided is not greater than 2. That is, the patterned first doped silicon layer 2 accounts for ≤2 / 3 of the surface where it is provided. Preferably, the patterned first doped silicon layer 2 accounts for ≤60% of the surface where it is provided. Preferably, the patterned first doped silicon layer 2 accounts for ≤45% of the surface where it is provided. Experiments show that when the patterned first doped silicon layer 2 accounts for ≤2 / 3 of the surface where it is provided, the battery exhibits an FF not lower than the FF of the existing Poly Finger technology (error range ≤20%), and the short-circuit current increases, and the open-circuit voltage also increases weakly (the gain is not as large as the short-circuit current), but the battery efficiency is also improved compared with the existing Poly Finger technology. However, at this time, the improvement of the battery efficiency is not mainly dependent on the improvement of the FF, but comes from the synergistic effect of the improvement of the FF, the short-circuit current and the open-circuit voltage. Therefore, compared with the existing Poly Finger technology, the percentage of the patterned first doped silicon layer 2 of the present application in the surface where it is provided can be lower, and thus more poly can be removed, and the efficiency can be improved more obviously.

[0082] The doping concentration of the first doped silicon layer 2 is not limited in the embodiment and can be set as needed. In an embodiment of the present application, the doping concentration of the first doped silicon layer 2 far from the silicon substrate 1 is greater than the doping concentration of the first doped silicon layer 2 close to the silicon substrate 1, so as to improve the passivation effect, reduce the loss of light absorption of the first doped silicon layer 2, reduce the parasitic absorption, optimize the contact resistance, and thus improve the cell conversion efficiency of the solar cell.

[0083] It should be noted that the type of the solar cell is not limited in the embodiment and can be determined as needed.

[0084] As an implementable manner, the solar cell can be a main grid-free cell, that is, only the fine grid lines 3 exist. As another implementable manner, as shown in FIG. 2, the grid lines can further include main grid lines 4 located in the grid line regions 21; the main grid lines 4 are electrically connected with the fine grid lines 3. The carriers on the fine grid lines 3 can be collected to the main grid lines 4. Figure 2

[0085] In an embodiment of the present application, the size of the grid line region 21 where the main grid lines 4 are located is not less than the size of the grid line region 21 where the fine grid lines 3 are located, which helps to reduce the parasitic absorption, improve the cell efficiency, and reduce the loss of light absorption.

[0086] The solar cell in the embodiment includes the silicon substrate 1, the patterned first doped silicon layer 2, and the grid lines. The first doped silicon layer 2 includes the grid line regions 21 and the non-grid line regions 22. At least part of the non-grid line regions 22 is different from the extension direction of the grid line regions 21, so as to intersect with the grid line regions 21. Therefore, the carriers between the grid line regions 21 can be transmitted not only to the fine grid lines 3 but also to the first doped silicon layer 2 in the non-grid line regions 22 and then to the fine grid lines 3. Therefore, the transmission path of the carriers in the solar cell of the present application is increased, the transmission effect of the carriers on the first doped silicon layer 2 is better, the transmission capacity of the carriers is enhanced, the series resistance is smaller, and the cell conversion efficiency is further improved.

[0087] Based on but not limited to the above-mentioned embodiments, in an embodiment of the present application, the solar cell can further include a passivation layer; the passivation layer covers the surface of the first doped silicon layer 2 far from the silicon substrate 1 and the part of the silicon substrate 1 where the first doped silicon layer 2 is not arranged. That is, the passivation layer covers the first doped silicon layer 2 and the removed region 5.

[0088] The passivation layer can improve the passivation performance of the cell, and thus improve the efficiency of the cell.

[0089] It should be noted that the structure of the passivation layer is not limited in the embodiment and can be determined as needed.

[0090] ​As an implementable manner, the passivation layer is at least one of an aluminum oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. In practical applications, the aluminum oxide layer, the silicon nitride layer, the silicon oxide layer, and the silicon oxynitride layer can be arranged in a single layer or in a stack.

[0091] As an implementable manner, the passivation layer is a single-layer passivation layer. The passivation layer is preferably an aluminum oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Of course, the types of the passivation layers arranged on the front surface and the back surface can be the same or different. For example, when the first doped silicon layer 2 is arranged on the back surface and the doping type of the first doped silicon layer 2 is the same as that of the silicon substrate 1, the passivation layer arranged on the back surface can be only a silicon nitride layer or a silicon oxynitride layer. When the first doped silicon layer 2 is arranged on the front surface and the doping type of the first doped silicon layer 2 is different from that of the silicon substrate 1, the passivation layer arranged on the back surface can be an aluminum oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0092] As an implementable manner, the passivation layer is a multi-layer passivation layer. Preferably, the passivation layer close to the silicon substrate 1 is preferably an aluminum oxide layer, and the aluminum oxide layer is stacked with at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. Of course, when the multi-layer passivation layer includes an aluminum oxide layer, the aluminum oxide layer is arranged close to the silicon substrate 1, and then at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer is stacked. Of course, the same aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon oxide layer can also be sandwiched between two layers of the same or different other passivation layers. For example, the silicon substrate 1 is stacked from the inside to the outside with an aluminum oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer. For another example, the silicon substrate 1 is stacked from the inside to the outside with an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0093] As an implementable manner, the passivation layer includes a stacked aluminum oxide layer and a silicon nitride layer, wherein the aluminum oxide layer is arranged close to the side of the silicon substrate 1; the thickness of the aluminum oxide layer is 3 nm to 7 nm; and the thickness of the silicon nitride layer is 70 nm to 90 nm. Preferably, the thickness of the aluminum oxide layer is 4 nm to 6 nm; and the thickness of the silicon nitride layer is 75 nm to 86 nm. The stacked aluminum oxide layer and silicon nitride layer have better passivation effect and are easy to implement.

[0094] Based on but not limited to any of the above embodiments, in an embodiment of the present application, the part of the region where the first doped silicon layer 2 is arranged and the part of the region where the first doped silicon layer 2 is not arranged can form a step.

[0095] As an implementable manner, the height difference between the partial region provided with the first doped silicon layer 2 and the partial region not provided with the first doped silicon layer 2 of the silicon substrate 1 can be 1 μm ~ 5 μm, which can ensure the removal of the doped ions of the first doped silicon layer 2 and the silicon substrate 1, and also ensure the removal of the front side passivation and the risk of over-etching in the normal region. It is worth noting that the height difference is determined by the actual etching process, and the present application does not limit it. The removal region 5 of the etched silicon substrate 1 can be free of an inner expansion layer, while the region corresponding to the first doped silicon layer 2 is provided with an inner expansion layer. The inner expansion layer is formed when the first doped silicon layer 2 diffuses at high temperature, and the doped elements of the first doped silicon layer 2 enter the silicon substrate 1. Of course, if the first doped silicon layer 2 does not have high-temperature diffusion or the processing temperature in its production process is not enough to diffuse its doped elements to the silicon substrate 1, then the inner expansion layer does not exist. When the silicon layer of the removal region 5 is removed, low-concentration diffusion can be performed on the removal region 5 to form a low-concentration region, and then form SE with the gate line region 21 of the high-concentration region. Of course, it is worth noting that the low-concentration region and the high-concentration region can also be formed by high-temperature diffusion after the silicon layer of the removal region 5 is removed, and then laser irradiation is performed on the gate line region 21.

[0096] Based on but not limited to any of the above embodiments, in an embodiment of the present application, the roughness of the partial region provided with the first doped silicon layer 2 of the silicon substrate 1 is different from that of the partial region not provided with the first doped silicon layer 2. Since the first doped silicon layer 2 of the removal region 5 needs to be cleaned after being removed, it will etch the silicon substrate 1, and then the roughness of the silicon substrate 1 in the removal region 5 is no longer the same as that of the region where the first doped silicon layer 2 is located. Based on the consideration of light trapping effect, passivation effect and electrode bonding strength, the roughness of the removal region 5 can be greater than or less than that of the region where the first doped silicon layer 2 is located.

[0097] As an implementable manner, the partial region provided with the first doped silicon layer 2 of the silicon substrate 1 has a tower base textured surface, and the removal region 5 of the silicon substrate 1 has a tower top textured surface or a combined textured surface of tower base and tower top. If the aluminum oxide layer closest to the silicon substrate 1 and the first doped silicon layer 2 is used for passivation, the removal region 5 of the silicon substrate 1 preferably adopts the combined textured surface of tower base and tower top to further improve the open circuit voltage and thus improve the battery conversion efficiency.

[0098] Based on but not limited to any of the above embodiments, in an embodiment of the present application, when the solar cell includes the main busbar 4, the first doped silicon layer 2 is in a mesh structure, wherein the grid area 21 where the main busbar 4 is located extends horizontally, the grid area 21 where the fine busbar 3 is located extends vertically, and at least part of the non-grid area 22 extends horizontally and at least one end thereof intersects with the grid area 21 where the fine busbar 3 is located. In actual application, the mesh structure can be a square grid arranged horizontally and vertically, and the non-grid area is arranged between the adjacent main busbars 4. Of course, the mesh structure can also be other shapes, such as snowflake, spider web, etc. which are not arranged horizontally and vertically, and the patterning of the electrode and the patterning of the first doped silicon layer are subject to the patterning, which is not limited in the present application.

[0099] The first doped silicon layer 2 is in a mesh structure arranged horizontally and vertically, which can simplify the process of removing the removal area 5 of the first doped silicon layer 2, simplify the process control program, and reduce the complexity thereof.

[0100] As an implementable manner, the main busbar 4 includes a connecting line and a pad area, and two or more pad areas are connected by the connecting line.

[0101] The size of the connecting line and the pad area in the present embodiment is not limited and is subject to the situation. As an implementable manner, the short side size of the connecting line can be 200 μm to 600 μm.

[0102] If the connecting line is too narrow, the series resistance will increase, thereby affecting the performance of the cell, and due to the increase of the resistance, more power loss will be caused. If the connecting line is too wide, more sunlight will be blocked, the effective illumination area of the cell will be reduced, thereby reducing the conversion efficiency, and the manufacturing cost will also be increased.

[0103] As an implementable manner, the short side size of the pad area can be 800 μm to 1600 μm, so as to facilitate the connection of the main busbar 4 and the pad. Preferably, the short side size of the pad area can be 1000 μm to 1200 μm. Preferably, the short side size of the pad area can be 1100 μm, 1200 μm, 800 μm, or 1600 μm.

[0104] As an implementable manner, the size of the grid area 21 where the pad area is located is greater than the size of the grid area 21 where the connecting line is located, so as to improve the welding offset of the solder ribbon, improve the mechanical strength of the solder joint, and improve the durability of the cell.

[0105] As an implementable manner, the size of the grid area 21 where the connecting line is located is greater than the size of the grid area 21 where the fine busbar 3 is located, which can reduce the shading problem caused by additional parasitic absorption, thereby improving the current of the cell.

[0106] Based on but not limited to any of the above embodiments, in an embodiment of the present application, as Figure 2As shown, when the solar cell piece includes the main busbar 4, the non-busbar region 22 is arranged in the region where the busbar region 21 where the main busbar 4 is not arranged.

[0107] That is, the non-busbar region 22 is arranged between the adjacent main busbar 4 regions, intersects with the fine busbar 3 region, and can make the carriers quickly transmit to the fine busbar 3 and the non-busbar region 22, and then gather on the main busbar 4.

[0108] As an implementable manner, the non-busbar region 22 is arranged in parallel with the busbar region 21 where the main busbar 4 is arranged, that is, the non-busbar region 22 and the busbar region 21 where the fine busbar 3 is arranged are perpendicular, which can simplify the manufacturing process of laser removal.

[0109] In an embodiment of the present application, when the non-busbar region 22 is arranged in parallel with the busbar region 21 where the main busbar 4 is arranged, 1-5 sub-non-busbar regions 22 are arranged independently between the two adjacent main busbars 4, and the non-busbar region 22 includes the sub-non-busbar region 22. That is, 1-5 non-busbar regions 22 are arranged between the two adjacent main busbars 4. For example, the number of non-busbar regions 22 between the two adjacent main busbars 4 can be 1, 2, 3, 4, 5, etc. Figure 2 For example, three are shown.

[0110] When the number of non-busbar regions 22 between the adjacent main busbars 4 is too small, the FF or short-circuit current of the solar cell is not obviously improved. Further, when the first doped silicon layer 2 accounts for not more than 2 / 3 of the area of the surface where it is arranged, when the number of non-busbar regions 22 between the adjacent main busbars 4 is too large, the area occupied by the non-busbar region 22 is too large, resulting in that the area of the first doped silicon layer 2 is too large, which is not conducive to the improvement of the short-circuit current.

[0111] As an implementable manner, the size of the fine busbar 3 close to the main busbar 4 side is greater than the size of the fine busbar 3 away from the main busbar 4 side, so as to enhance the connection firmness between the fine busbar 3 and the main busbar 4.

[0112] Based on but not limited to any of the above embodiments, in an embodiment of the present application, a first tunneling layer is arranged between the first doped silicon layer 2 and the silicon substrate 1. The first tunneling layer and the first doped silicon layer 2 can form a single-layer tunneling structure.

[0113] The first tunneling layer can be a silicon oxide layer, an intrinsic silicon layer, or a silicon nitride layer.

[0114] As an implementable manner, the thickness of the first tunneling layer can be 1-2.2 nm.

[0115] As an implementable manner, the thickness of the first doped silicon layer 2 can be 90-200 nm, so that the gain brought by J0metal (open voltage) is greater than the loss of Isc, the comprehensive electrical performance parameters are best, and the efficiency is best (the efficiency is maximized).

[0116] Different from the above embodiment, in the present embodiment, an intrinsic silicon layer is arranged between the first doped silicon layer 2 and the silicon substrate 1, and the first doped silicon layer 2 is doped amorphous silicon.

[0117] Different from the above embodiment, in the present embodiment, a second tunnel layer, a second doped silicon layer and a third tunnel layer are arranged between the first doped silicon layer 2 and the silicon substrate 1 in the solar cell; the second tunnel layer is arranged close to the silicon substrate 1, and the third tunnel layer is arranged close to the first doped silicon layer 2.

[0118] The second tunnel layer and the second doped silicon layer form a first tunnel structure, and the third tunnel layer and the first doped silicon layer 2 form a second tunnel structure, that is, the solar cell has a double-layer tunnel structure, which can effectively reduce the recombination of the metal contact area and improve the FF and open voltage of the cell.

[0119] As an implementable manner, the thickness of the second tunnel layer is 1.5-2.2 nm, the thickness of the second doped silicon layer is 20-40 nm, the thickness of the third tunnel layer is 0.5-1.2 nm, and the thickness of the first doped silicon layer 2 is 110-130 nm.

[0120] Comparative experiments of a 150 nm laminated tunnel solar cell (the thickness of the second tunnel layer is 1.5-2.2 nm, the thickness of the second doped silicon layer is 20-40 nm, the thickness of the third tunnel layer is 0.5-1.2 nm, and the thickness of the first doped silicon layer 2 is 110-130 nm) and a 150 nm single-layer tunnel cell (the thickness of the first tunnel layer is 1-2.2 nm, and the thickness of the first doped silicon layer 2 is 140-170 nm) show that the laminated tunnel structure of the cell using the Poly Finger technology is better than the single-layer tunnel structure. It should be noted that the thickness of the doped silicon layer (the first doped silicon layer 2, the second doped silicon layer and the third doped silicon layer) is difficult to control and measure, so the range value is used for description.

[0121] As an implementable manner, the second doped silicon layer can be an N-type doped layer or a P-type doped layer, and further doped with at least one of C, N, O and H elements. When the second doped silicon layer is doped with at least one of C, N, O and H elements in addition to N-type doped elements or P-type doped elements, the passivation effect of the second doped silicon layer can be improved, thereby further improving the conversion efficiency of the cell.

[0122] As an implementable manner, the doping concentration of the first doped silicon layer 2 is higher than that of the second doped silicon layer, and the higher doping concentration of the first doped silicon layer 2 in contact with the gate line can optimize the contact resistance, thereby improving the battery conversion efficiency.

[0123] As an implementable manner, the second tunneling layer and the second doped silicon layer cover the entire surface, and the third tunneling layer is arranged flush with the first doped silicon layer 2.

[0124] As an implementable manner, the second tunneling layer, the second doped silicon layer and the third tunneling layer are arranged flush with the first doped silicon layer 2.

[0125] As an implementable manner, the second tunneling layer and the second doped silicon layer cover the entire surface, and the thickness of the second doped silicon layer corresponding to the first doped silicon layer is greater than the thickness of the second doped silicon layer corresponding to the removal area 5, that is, when the first doped silicon layer 2 is removed in the removal area 5 or the first doped silicon layer 2 is not doped, only part of the second doped silicon layer located in the removal area 5 is etched during cleaning.

[0126] Unlike the above-mentioned embodiments, in the present embodiment, a third doped silicon layer is provided between the first doped silicon layer 2 and the silicon substrate 1, that is, a third doped silicon layer and a first doped silicon layer 2 are provided on one surface of the silicon substrate 1, which can avoid the risk of misalignment, reduce additional metal recombination and current loss, and improve the efficiency and yield of the battery.

[0127] As an implementable manner, the third doped silicon layer is an N-type doped layer or a P-type doped layer, and is further doped with at least one of C, N, O and H elements. When the third doped silicon layer is doped with at least one of C, N, O and H elements in addition to N-type doping elements or P-type doping elements, the passivation effect of the second doped silicon layer can be improved, thereby further improving the battery conversion efficiency.

[0128] As an implementable manner, the doping concentration of the first doped silicon layer 2 is higher than that of the third doped silicon layer, and the higher doping concentration of the first doped silicon layer 2 in contact with the gate line can optimize the contact resistance, thereby improving the battery conversion efficiency.

[0129] As an implementable manner, a fourth tunneling layer is provided between the third doped silicon layer and the silicon substrate 1, the fourth tunneling layer and the third doped silicon layer form a tunneling structure, and the first doped silicon layer 2 is further provided on the tunneling structure, which can improve the efficiency of the battery.

[0130] As an implementable manner, a fifth tunneling layer is provided between the third doped silicon layer and the first doped silicon layer 2, the fourth tunneling layer and the third doped silicon layer form a tunneling structure, and the fifth tunneling layer and the first doped silicon layer 2 form a tunneling structure, that is, a double-layer tunneling structure is formed, which can improve the FF and open voltage of the battery.

[0131] AsFigure 2 As shown, on the basis of any of the above embodiments, in one embodiment of the present application, in the target range A of the grid line area 21 where the two adjacent main grid lines 4 are located and the grid line area 21 where the two adjacent fine grid lines 3 are located, the ratio of the area of the non-grid line area 22 to the area of the region other than the non-grid line area 22 in the target range A can range from 1:1 to 1:9.

[0132] For example, the ratio of the area of the non-grid line area 22 to the area of the region other than the non-grid line area 22 in the target range A can be 1:1, 1:3, 1:5, 1:7, 1:9, etc., which is not specifically limited in the present embodiment.

[0133] If the ratio of the area of the non-grid line area 22 to the area of the region other than the non-grid line area 22 in the target range A is too large, it indicates that the area of the region other than the non-grid line area 22 in the target range A is larger, and the FF of the solar cell is not obviously improved. If the ratio of the area of the non-grid line area 22 to the area of the region other than the non-grid line area 22 in the target range A is too small, it indicates that the area of the non-grid line area 22 is larger, which will lose the short-circuit current.

[0134] A manufacturing process for preparing the solar cell in the present application is described below.

[0135] Step 1. Select an N-type single crystal silicon wafer, the resistivity of the N-type single crystal silicon wafer is 0.6-1.4 Ω·cm, the thickness is 150±20 μm, the surface of the N-type single crystal silicon wafer is pre-cleaned, and then double-sided texturing is performed;

[0136] Step 2. Perform one-time boron diffusion on the double sides of the textured N-type single crystal silicon wafer, which includes the processes of deposition, promotion and oxidation, to form a boron emitter, i.e., a diffusion layer;

[0137] Step 3. Perform alkali polishing treatment on the back surface of the N-type single crystal silicon wafer using a slot-type NaOH and an additive, wherein the additive functions to protect the BSG layer on the front surface from being removed;

[0138] Step 4. Perform low-pressure deposition of a first tunneling layer and an amorphous silicon layer at 580-620 degrees Celsius using an LPCVD (Low Pressure Chemical Vapor Deposition) device;

[0139] Step 5. Perform phosphorus doping and growth of a 15-35 nm PSG layer and partial winding on the back surface at 800-920 degrees Celsius using a phosphorus diffusion device;

[0140] Step 6. The backside PSG layer is patterned by laser, the PSG layer in the gate line area is reserved, the area outside the gate line area is meshed, and the PSG layer in the middle of the mesh is modified. The size of the mesh depends on the design of the laser spot.

[0141] Step 7. The frontside PSG layer is removed by HF acid using a chain device, and the frontside poly silicon winding and BSG, the backside PSG layer, and the poly in the laser opening area are cleaned and removed using a tank device.

[0142] Step 8. An Al2O3 layer is deposited on the frontside and backside of the cell using TMA (trimethylaluminum) and an oxidizing agent by a plate or tube ALD (atomic layer deposition) or PECVD (plasma enhanced chemical vapor deposition) device.

[0143] Step 9. SiNx / SiONx / SiOx anti-reflective film is deposited on the frontside and SiNx / SiONx / SiOx passivation film is deposited on the backside using SiH4 / NH3 / N2O by a PECVD device. The frontside anti-reflective film is made first, and then the backside passivation film is made.

[0144] Step 10. The main grid and fine grid lines are printed on the backside by screen printing, the main grid and fine grid lines are printed on the frontside by screen printing to coincide with the previous patterned emitter, and then sintering is performed.

[0145] Step 11. H passivation is performed by a light injection furnace.

[0146] Step 12. The frontside of the cell is treated by LECO laser treatment.

[0147] Step 13. The whole cell is tested for IV.

[0148] Step 14. The test is sorted.

[0149] The application also provides a photovoltaic module comprising the solar cell of any of the above embodiments.

[0150] It should be noted that the photovoltaic module can also include a frontside substrate, a frontside adhesive film layer, a backside adhesive film layer, and a backside substrate, and can refer to the photovoltaic module in the related art for details.

[0151] On the basis of the above embodiments, in an embodiment of the application, the frontside substrate is an ultra-white embossed glass substrate.

[0152] The ultra-white embossed glass substrate can increase the amount of light entering the photovoltaic module, thereby increasing the power generation of the photovoltaic module.

[0153] The various embodiments described in this specification are intended to be illustrative only and in no way limit the scope of the application. Those skilled in the art will be able to devise numerous alternative arrangements without departing from the scope of the application.

[0154] The above describes the solar cell provided by the present application in detail. The principles and implementation manners of the present application are described by applying specific examples in this paper.

[0155] It should be noted that, in this specification, the relationship terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0156] The various embodiments in this specification can be freely combined without departing from the principles of the art, and when an element such as a layer, film, region or plate is referred to as "on", "superimposed", "provided with", "provided on" another element, the element can be directly on the other element, and there can also be one or more intermediate elements.

[0157] The above description of the embodiments is only used to help understand the schemes and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A solar cell, characterized in that, include: Silicon substrate; A patterned first doped silicon layer is located on at least one surface of the silicon substrate, such that a portion of the surface is provided with the first doped silicon layer and a portion of the surface is not provided with the first doped silicon layer; the first doped silicon layer includes gate line regions and non-gate line regions, at least a portion of the non-gate line regions having a different extension direction from the gate line regions so as to intersect the gate line regions; The grid line includes fine grid lines located in the grid line region.

2. The solar cell as described in claim 1, characterized in that: The short side dimension of the non-gate region ranges from 5μm to 1000μm.

3. The solar cell as described in claim 1, characterized in that: The ratio of the area of ​​at least one of the surfaces having the first doped silicon layer to the area of ​​the surface not having the first doped silicon layer is not greater than 2.

4. The solar cell as described in claim 1, characterized in that: It also includes a passivation layer; which covers the surface of the first doped silicon layer away from the silicon substrate and a portion of the silicon substrate where the first doped silicon layer is not disposed.

5. The solar cell as described in claim 1, characterized in that: The ratio of the short side dimension of the fine grid line to the short side dimension of the grid line region in which the fine grid line is located is in the range of 1:1 to 1:

15.

6. The solar cell according to claim 1, characterized in that: The short side dimension of the fine grid lines is 5μm~50μm.

7. The solar cell as claimed in claim 1, characterized in that: The short side dimension of the grid line region where the fine grid line is located is 5μm to 750μm.

8. The solar cell as claimed in claim 1, characterized in that: The silicon substrate has a step formed between a portion of the region where the first doped silicon layer is provided and a portion of the region where the first doped silicon layer is not provided.

9. The solar cell as claimed in claim 1, characterized in that: The roughness of the portion of the silicon substrate having the first doped silicon layer differs from that of the portion not having the first doped silicon layer.

10. The solar cell according to claim 1, characterized in that: When the first doped silicon layer is provided on both surfaces of the silicon substrate, the doping types of the first doped silicon layer on the two surfaces are different; when the first doped silicon layer is provided on one surface of the silicon substrate, the doping type of the first doped silicon layer is the same as or different from the doping type of the silicon substrate.

11. The solar cell as claimed in claim 4, characterized in that: The passivation layer is at least one of an aluminum oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

12. The solar cell as claimed in claim 4, characterized in that: The passivation layer is a single-layer passivation layer.

13. The solar cell as claimed in claim 4, characterized in that: The passivation layer is a multi-layer passivation layer.

14. The solar cell according to claim 4, characterized in that: The passivation layer comprises stacked aluminum oxide and silicon nitride, wherein the aluminum oxide is disposed on the side closer to the silicon substrate; the thickness of the aluminum oxide is 3 nm to 7 nm; and the thickness of the silicon nitride is 70 nm to 90 nm.

15. The solar cell as claimed in claim 8, characterized in that: The height difference between the portion of the silicon substrate having the first doped silicon layer and the portion not having the first doped silicon layer is 1 μm to 5 μm.

16. The solar cell according to any one of claims 1-15, characterized in that, The grid line also includes a main grid line located in the grid line region; the main grid line is electrically connected to the fine grid line.

17. The solar cell as claimed in claim 16, characterized in that: The size of the grid line region where the main grid line is located is not less than the size of the grid line region where the fine grid line is located.

18. The solar cell as claimed in claim 16, characterized in that: The first doped silicon layer has a mesh structure, wherein the gate line region where the main gate line is located extends laterally, and the gate line region where the fine gate line is located extends longitudinally; the non-gate line region extends laterally and at least one end of it intersects with the gate line region where the fine gate line is located.

19. The solar cell as claimed in claim 16, characterized in that: The main gate line includes a connecting line and a pad area; two or more of the pad areas are connected by the connecting line.

20. The solar cell as claimed in claim 16, characterized in that: The non-gate line area is set in the area where there is no gate line area where the main gate line is located.

21. The solar cell as claimed in claim 16, characterized in that: The non-gate line area is arranged parallel to the gate line area where the main gate line is located.

22. The solar cell as claimed in claim 16, characterized in that: The dimension of the fine grid line on the side closer to the main grid line is larger than the dimension of the fine grid line on the side farther away from the main grid line.

23. The solar cell as claimed in claim 19, characterized in that: The size of the gate line area where the pad area is located is larger than the size of the gate line area where the connector line is located.

24. The solar cell as claimed in claim 19, characterized in that: The size of the grid line region where the connecting line is located is larger than the size of the grid line region where the fine grid line is located.

25. The solar cell as claimed in claim 21, characterized in that: When the non-gate line area is arranged parallel to the gate line area where the main gate line is located, there are 1 to 5 independently arranged sub-non-gate line areas between two adjacent main gate lines, and the non-gate line area includes the sub-non-gate line area.

26. The solar cell as claimed in claim 19, characterized in that: The short side dimension of the connecting line is 200μm~600μm.

27. The solar cell as claimed in claim 19, characterized in that: The short side dimension of the pad area is 800μm~1600μm.

28. The solar cell according to any one of claims 1-15 or any one of claims 17-27, characterized in that: A first tunneling layer is provided between the first doped silicon layer and the silicon substrate.

29. The solar cell according to any one of claims 1-15 or any one of claims 17-27, characterized in that: A second tunneling layer, a second doped silicon layer, and a third tunneling layer are stacked between the first doped silicon layer and the silicon substrate; wherein the second tunneling layer is disposed close to the silicon substrate, and the third tunneling layer is disposed close to the first doped silicon layer.

30. The solar cell according to any one of claims 1-15 or any one of claims 17-27, characterized in that: A third doped silicon layer is provided between the first doped silicon layer and the silicon substrate.

31. The solar cell according to any one of claims 1-15 or any one of claims 17-27, characterized in that: An intrinsic silicon layer is provided between the first doped silicon layer and the silicon substrate, and the first doped silicon layer is doped amorphous silicon.

32. The solar cell as claimed in claim 28, characterized in that: The thickness of the first tunneling layer is 1 nm to 2.2 nm.

33. The solar cell as claimed in claim 28, characterized in that: The thickness of the first doped silicon layer is 90nm~200nm.

34. The solar cell as claimed in claim 29, characterized in that: The thickness of the second tunneling layer ranges from 1.5 nm to 2.2 nm, and the thickness of the second doped silicon layer ranges from 20 nm to 40 nm; the thickness of the third tunneling layer ranges from 0.5 nm to 1.2 nm, and the thickness of the first doped silicon layer ranges from 110 nm to 130 nm.

35. The solar cell as claimed in claim 29, characterized in that: The second tunneling layer and the second doped silicon layer cover the entire surface and the third tunneling layer is flush with the first doped silicon layer, or the second tunneling layer, the second doped silicon layer and the third tunneling layer are flush with the first doped silicon layer.

36. The solar cell as claimed in claim 30, characterized in that: A fourth tunneling layer is provided between the third doped silicon layer and the silicon substrate.

37. The solar cell according to claim 30, characterized in that: A fifth tunneling layer is provided between the third doped silicon layer and the first doped silicon layer.

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