Solar cell, cell assembly and photovoltaic system

By setting arc-shaped concave surface traces and grid lines on the back surface of the silicon substrate of the solar cell, the problem of light escape is solved, light absorption and conversion efficiency are improved, and current output is enhanced.

CN223666707UActive Publication Date: 2025-12-12TIANJIN AIKO SOLAR ENERGY TECH CO LTD
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Patent Information

Application Number
CN202522365610.8
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-11-07
Publication Date
2025-12-12
Estimated Expiration
2035-11-07

AI Technical Summary

Technical Problem

Traditional solar cells have low light absorption and photoelectric conversion efficiency. Light escapes after being reflected and refracted on the silicon wafer surface, resulting in wasted light energy. The light propagation path is not optimized, making it difficult to improve current output and overall conversion efficiency.

Method used

A concave arc-shaped trace and grid line are set on the back surface of the silicon substrate, with an included angle of 0 to 15°. The surface of the trace can be equipped with a textured structure to increase light reflection and propagation path and improve light absorption efficiency.

Benefits of technology

By changing the angle of light to reflect it back into the silicon wafer, the light absorption path is increased, thereby improving the current output and photoelectric conversion efficiency of the battery and reducing surface recombination losses.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model is suitable for the photovoltaic technology field, and provides a solar cell, a cell assembly and a photovoltaic system, the solar cell comprises a silicon substrate, a backlight surface of the silicon substrate is provided with a plurality of grid lines and a plurality of line marks side by side along a first direction, the grid lines extend along a second direction, the line marks are of concave surface structures, an included angle between the line marks and the grid lines is 0-15 degrees, and the included angle between the line marks and the grid lines is 0-15 degrees. And the cross section of the line mark is arc-shaped. The propagation path of light in the silicon wafer can be increased, the opportunity of light absorption is improved, and the photoelectric conversion efficiency of the cell is further improved.
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Description

TECHNICAL FIELD

[0001] The utility model belongs to photovoltaic technical field especially relates to a solar cell, battery assembly and photovoltaic system. BACKGROUND

[0002] In the solar cell technical field, constantly improving light absorption efficiency and photoelectric conversion efficiency is always the core pursuit of scientific researchers and industry. Traditional solar cells are limited by material properties and surface structure design, and have many bottlenecks in light absorption. When light shines on the surface of the cell, a large amount of light will escape from the silicon wafer due to reflection and refraction, like water continuously flowing out of a container with a leak. These escaped light cannot participate in the photoelectric conversion process, causing a great waste of light energy.

[0003] Moreover, the conventional cell surface structure lacks effective planning and optimization of the light propagation path. After the light enters the silicon wafer, the propagation distance is extremely limited, like walking in a narrow passage, making it difficult to fully interact with the cell material, greatly reducing the opportunity for light absorption. This series of problems directly leads to the difficulty in improving the current output of the cell, and the overall conversion efficiency has long been hovering at a low level, seriously restricting the large-scale application and development of solar cells. SUMMARY

[0004] The utility model provides a solar cell, battery assembly and photovoltaic system, aims at solving the problem of low light absorption efficiency and photoelectric conversion efficiency of the existing solar cell.

[0005] The utility model is realized in this way, a solar cell, characterized in that, comprising:

[0006] The silicon substrate has a plurality of grid lines and a plurality of line marks arranged side by side on the back surface along a first direction. The grid lines extend along a second direction. The line marks are concave structures. The included angle between the line marks and the grid lines is 0-15°. The cross section of the line mark is circular arc shape.

[0007] Optionally, the surface of the line mark has a texture structure.

[0008] Optionally, the texture structure is ">"-shaped, and the sharp corner of the texture structure faces the extension direction of the line mark.

[0009] Optionally, the sharp corners of at least two adjacent texture structures are reversely arranged, and the length between the two sharp corners is 10-40 microns.

[0010] Optionally, two adjacent texture structures enclose at least one of a rhombus, a square and a rectangle.

[0011] Optionally, the distance between adjacent texture structures is greater than 5 μm.

[0012] Optionally, the opening of the line mark is wavy along the extension direction of the line mark.

[0013] Optionally, the distance between the wave crest and the wave trough of the wavy structure is less than 10 μm.

[0014] Optionally, the depth of the line mark is 0.5-5 μm.

[0015] Optionally, the width of the line mark is 10-80 μm.

[0016] Optionally, the radius of curvature of the line mark is 50-200 μm.

[0017] Optionally, the depth of the circular arc of the cross section of the line mark is different at different positions.

[0018] Optionally, the depth difference of the circular arc of the cross section of the line mark is less than 5 μm.

[0019] Optionally, a doping layer is arranged on the back light surface of the silicon substrate, a plurality of gate lines are arranged side by side on the doping layer, and the forming area of the line mark is covered with the doping layer.

[0020] Optionally, the included angle between the edge of the doping layer and the line mark is 0-15°.

[0021] Optionally, the gate line is at least partially arranged on the line mark.

[0022] Optionally, the gate line comprises a first polarity gate line and a second polarity gate line, and the polarities of the first polarity gate line and the second polarity gate line are different.

[0023] Optionally, the back light surface is alternately provided with a first doping area and a second doping area along the first direction, the first polarity gate line is arranged on the first doping area, and the second polarity gate line is arranged on the second doping area.

[0024] Optionally, a plurality of gate lines and a plurality of line marks are arranged side by side on the light receiving surface of the silicon substrate along a first direction, the gate lines extend along a second direction, the line marks are circular arc-shaped concave structures, and the included angle between the line mark and the gate line is 0-15°, wherein the polarities of the gate lines arranged on the light receiving surface and the gate lines arranged on the back light surface are different.

[0025] The utility model also provides a battery assembly, including above-mentioned solar cell.

[0026] The utility model also provides a photovoltaic system, including above-mentioned battery assembly.

[0027] The utility model discloses a beneficial effect reached, because set the line mark of arc concave structure, the included angle between line mark and grid line is 0~15 DEG, part of the light originally will escape the silicon wafer because of the angle change, when reaching the front again will be reflected back to the silicon wafer body, this helps to increase the absorption path of light in the silicon wafer, thereby improve the absorption efficiency of light, finally improve the current output and overall conversion efficiency of battery. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is two -dimensional structure schematic diagram of solar cell that the utility model provides;

[0029] Figure 2 It is local enlarged structure schematic diagram of solar cell that the utility model provides;

[0030] Figure 3 It is one local SEM diagram of solar cell that the utility model provides;

[0031] Figure 4 It is another local SEM diagram of solar cell that the utility model provides.

[0032] BRIEF DESCRIPTION OF DRAWINGS

[0033] 100, solar cell;101, silicon substrate;102, grid line;103, line mark;1031, texture structure;104, tunneling layer;105, doped layer;106, passivation layer. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantage of the utility model more clear and obvious, the following combines the drawing and example, and further detailedly explains the utility model. The example of the example is shown in the drawing, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar function throughout. The example described below by referring to the drawing is exemplary, and is only used for explaining the utility model, and can not be understood as the limitation of the utility model. In addition, it should be understood that the specific embodiments described herein are only used to explain the utility model, and are not used to limit the utility model.

[0035] In the description of the utility model, it is necessary to understand that the orientation or positional relation indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom" and the like is the orientation or positional relation based on the drawing shown, and is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the utility model.

[0036] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the utility model, the meaning of "multiple" is two or more than two, unless otherwise specifically limited.

[0037] In the description of the utility model, it should be noted that, unless otherwise specifically defined and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; can be mechanical connection, or electrical connection or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium, can be the communication or interaction between two elements. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.

[0038] In the utility model, unless otherwise specifically defined and limited, the "upper" or "lower" of the first feature in the second feature can include the direct contact of the first and second features, or the indirect contact of the first and second features through another feature between them. Moreover, the "upper", "upper" and "upper" of the first feature in the second feature include the vertical and inclined upper of the first feature in the second feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The "below", "below" and "below" of the first feature in the second feature include the vertical and inclined lower of the first feature in the second feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0039] The disclosure below provides many different embodiments or examples for implementing different structures of the present application. For the sake of simplicity, the description below of a particular embodiment or example does not cite every feature of the application. This omission, however, does not result in a disclaimer of those features. Indeed, all features described below for a particular embodiment or example apply equally to other embodiments or examples, unless otherwise noted, even if not specifically stated in the description. Furthermore, the disclosure provides examples of various processes and materials that can be used with the present application. One skilled in the art will recognize, however, that the application is not limited to the specific processes and materials described, but rather can utilize any process and materials that provide similar results.

[0040] The line mark in the arc-shaped concave structure is arranged, the included angle between the line mark and the grid line is 0-15°, part of the light originally escaping from the silicon wafer will be reflected back into the silicon wafer body when reaching the front surface again due to the change of the angle, which helps to increase the absorption path of the light in the silicon wafer, thereby improving the light absorption efficiency, finally improving the current output and overall conversion efficiency of the battery. The cross section of the line mark is arc-shaped, which can further increase the propagation path of the light in the silicon wafer, improve the opportunity of light absorption, and further enhance the photoelectric conversion efficiency of the battery.

[0041] Example One

[0042] As shown in Figures 1 to 4 The present embodiment provides a solar cell 100, comprising:

[0043] A silicon substrate 101, a plurality of grid lines 102 and a plurality of line marks 103 are arranged side by side on the back light surface of the silicon substrate 101 along a first direction, the grid lines 102 extend along a second direction, the line marks 103 are arc-shaped concave structures, the included angle between the line marks 103 and the grid lines 102 is 0-15°, and the cross section of the line marks 103 is arc-shaped.

[0044] The silicon substrate 101 is usually made of single crystal silicon or polycrystalline silicon material, which has good semiconductor properties. The silicon substrate 101 has two opposite surfaces, one of which is the back surface facing away from the sun, and the other is the front surface facing the sun. The back surface of the silicon substrate 101 is provided with a doped region, specifically, the back surface can be provided with a first doped region and a second doped region in sequence, and the polarities of the first doped region and the second doped region are different. The gate lines 102 provided in the first doped region are first polarity gate lines for collecting carriers in the first doped region, and the gate lines 102 provided in the second doped region are second polarity gate lines for collecting carriers in the second doped region. When the first polarity gate lines collect electrons, the second polarity gate lines collect holes; when the second polarity gate lines collect electrons, the first polarity gate lines collect holes. The first doped region can also be provided on the back surface, and the second doped region can be provided on the front surface, and the polarities of the first doped region and the second doped region are different. The gate lines 102 provided on the back surface are first polarity gate lines for collecting carriers in the first doped region, and the gate lines 102 provided on the front surface are second polarity gate lines for collecting carriers in the second doped region. The second polarity gate lines extend in a second direction, and the front surface is also provided with a plurality of line marks 103 in parallel in a first direction, and the included angle between the second polarity gate lines and the line marks 103 is 0-15°

[0045] The plurality of gate lines 102 and the plurality of line marks 103 are arranged in the first direction respectively, and the gate lines 102 extend in the second direction, and the second direction intersects the first direction. The gate lines 102 can be arranged in the longitudinal direction of the silicon substrate 101 and extend in the transverse direction, that is, the first direction can be the longitudinal direction of the back contact cell, and the second direction can be the transverse direction of the back contact cell, and the two directions are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, the two directions can be diagonal directions of the silicon substrate 101, which are not limited here. The plurality of gate lines 102 and the plurality of line marks 103 can overlap each other.

[0046] As shown in Figure 1 , the first direction is the longitudinal direction of the silicon substrate 101, and a plurality of line marks 103 and gate lines 102 are arranged in parallel in the first direction on the back surface. Usually, the gate lines 102 are linear, and extend in the second direction, which is perpendicular to the first direction, that is, extend in the transverse direction of the silicon substrate 101. The line mark 103 is a mark left during mechanical processing of the silicon substrate 101, and the shape (such as the extension direction and the cross-sectional shape) of the line mark 103 can be controlled by controlling the mechanical processing process.

[0047] The line mark 103 extends linearly, and the included angle between the line mark 103 and the gate line 102 is 0-15°, that is, the line mark 103 has a certain extension direction, and the included angle between the extension direction of the line mark 103 and the first direction is 0-15°, as shown inFigure 1 It should be noted that the two adjacent line marks 103 can be parallel or have an included angle, so the angle of the included angle between different line marks 103 and the grid lines 102 can be different. The grid lines 102 and the line marks 103 themselves have a certain width, and when measuring the included angle, the width of the grid lines 102 and the line marks 103 is not considered, for example, the included angle between the edge of the grid line 102 closest to the line mark 103 and the edge adjacent to the line mark 103 can be measured, or the included angle between the center line of the grid line 102 and the center line of the line mark 103 can be measured. Since the line mark 103 is a mark left during mechanical processing of the silicon substrate 101, due to the difference in the mechanical processing process, the shape, size, length, etc. of the line mark 103 are different, so the included angle between different line marks 103 and the grid lines 102 is different, and the included angle can be measured based on the actual situation.

[0048] The included angle between the line mark 103 and the grid line 102 is 0-15°, and when the line mark 103 is tangent to the grid line 102 or the tangent line of the line mark 103 is parallel to the grid line 102, the included angle between the line mark 103 and the grid line 102 is 0°.

[0049] A number of different solar cells 100 are detected to obtain the following experimental data:

[0050] Table 1

[0051]

[0052] As shown in Table 1, through the experimental data, it can be known that with the increase of the angle, the short-circuit current density increases, the contact area increases, the contact resistance decreases, and the fill factor FF improves. However, the surface area increases, the total recombination rate on the surface increases, the open-circuit voltage decreases, and when the angle is greater than 15°, the influence on the recombination will reduce the fill factor, causing the total efficiency to decrease. Therefore, when the included angle between the line mark 103 and the grid line 102 is 0-15°, the photoelectric conversion efficiency is relatively high.

[0053] As shown in Figure 2 and Figure 3 , the cross section of the line mark 103 is in the shape of a circular arc, and when light shines on the back of the cell, the cross section of the circular arc-shaped line mark 103 can cause multiple reflections of the light. Compared with a planar structure, the circular arc-shaped structure can change the propagation direction of the light, so that more light is reflected back into the cell, thereby increasing the absorption and utilization efficiency of the cell to the light and improving the photoelectric conversion efficiency. At the same time, the circular arc-shaped line mark 103 structure can reduce the electric field strength on the surface of the cell, reduce the recombination probability of electrons and holes on the surface. In addition, the arc surface arrangement can also increase the surface area of the cell, so that electrons and holes have more opportunities to be collected into the grid lines 102, thereby greatly reducing the surface recombination loss failure and improving the performance of the cell.

[0054] In the present embodiment, by setting the concave structure of the line mark 103, the included angle between the line mark 103 and the gate line 102 is 0-15°. Due to the change in the angle, the light originally escaping from the silicon wafer will be reflected back into the silicon wafer when it reaches the front surface again, which helps to increase the absorption path of the light in the silicon wafer, thereby improving the light absorption efficiency, and ultimately improving the current output and overall conversion efficiency of the battery. The cross section of the line mark 103 is in the shape of a circular arc, which can further increase the propagation path of the light in the silicon wafer, improve the opportunity for light absorption, and further enhance the photoelectric conversion efficiency of the battery.

[0055] In some embodiments, the depth of the line mark 103 is 0.5-5 μm. A suitable depth can enable the line mark 103 to effectively reflect and scatter light. A shallower depth (less than 0.5 μm) can result in fewer reflections of light within the line mark 103, which can not sufficiently increase the propagation path of the light within the battery; while a deeper depth (greater than 5 μm) can cause the light to be difficult to reflect again after entering the line mark 103, resulting in light loss.

[0056] In some embodiments, the width of the line mark 103 is 10-80 μm. A suitable width can enable the line mark 103 to effectively capture and reflect light. A narrower width (less than 10 μm) can limit the ability of the line mark 103 to capture light, while a wider width (greater than 80 μm) can cause the line mark 103 to occupy too much surface area of the battery, affecting the overall performance of the battery.

[0057] In some embodiments, the radius of curvature of the line mark 103 is 50-200 μm. A suitable radius of curvature can enable the light to be ideally reflected and refracted within the line mark 103.

[0058] In some embodiments, the depth of the circular arc of the cross section of the line mark 103 varies at different positions. The depth of the circular arc of the cross section of the line mark 103 varies at different positions. This means that the depth of the concave surface of the line mark 103 varies along its extension direction or at different lateral positions, forming a non-uniform depth distribution. This non-uniform depth distribution can enable the line mark 103 to respond well to light of different angles and wavelengths. For example, for light incident at different angles, a deeper cross-sectional circular arc can capture and reflect some light incident at a large angle, while a shallower cross-sectional circular arc can handle light incident at a small angle, thereby improving the light absorption capacity of the battery for various light.

[0059] In some embodiments, the depth difference of the circular arc of the cross section of the different position lines 103 is less than 5 μm, and specifically can be 0 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, or other values between 0 μm and 5 μm.

[0060] When the difference is 0 μm, the depth of the circular arc of the cross section of the different position lines 103 is consistent. A smaller depth difference can avoid a too large difference in reflection and absorption of light at different positions due to a too large depth difference, and ensure a relatively uniform propagation and absorption effect of light in the entire line 103 area. For example, if the depth difference is too large, there can be a situation that light is absorbed too much in some areas and not enough in other areas.

[0061] In some embodiments, the back surface of the silicon substrate 101 is provided with a doped layer 105, and a plurality of grid lines 102 are arranged side by side on the doped layer 105. The line 103 formation area is covered with the doped layer 105.

[0062] It should be noted that the doped layer 105 is arranged on the back surface of the silicon substrate 101, and specifically, the doped layer 105 can be in direct contact with the back surface of the silicon substrate 101, or other functional layers can be arranged between the doped layer 105 and the silicon substrate 101, such as a tunneling layer 104. A plurality of grid lines 102 are arranged on the doped layer 105, and the grid lines 102 are arranged side by side. Other functional layers, such as a passivation layer 106, can be arranged between the grid lines 102 and the doped layer 105. The grid lines 102 need to be in electrical contact with the doped layer 105, and when other functional layers are arranged on the doped layer 105, the grid lines 102 penetrate the functional layers to be in direct contact with the doped layer 105.

[0063] In some embodiments, the line 103 is a concave structure formed on the silicon substrate 101, and the line 103 formation area is covered with the doped layer 105.

[0064] In some embodiments, the grid lines 102 can not overlap the line 103, that is, the orthographic projection of the grid lines 102 does not overlap the line 103, or the grid lines 102 can at least partially cover the line 103, that is, the orthographic projection of the grid lines 102 overlaps the line 103. Since the grid lines 102 are partially arranged on the line 103, the concave surface of the line 102 increases the contact area with the grid lines 102, and the carriers can be more easily collected by the grid lines 102, reducing the loss of carriers in the transmission process.

[0065] The back surface of the silicon substrate 101 is provided with a doped layer 105. Specifically, the back surface can be provided with a first doped layer and a second doped layer in sequence, or the back surface can be provided with the first doped layer, and the second doped layer can be provided on the light surface. The first doped layer and the second doped layer have different polarities. Specifically, the first doped layer can be an N-type doped layer, and the second doped layer can be a P-type doped layer. Alternatively, the first doped layer can be a P-type doped layer, and the second doped layer can be an N-type doped layer. The N-type doped layer and the P-type doped layer form regions with different chemical properties, support the formation of a PN junction, and separate carriers.

[0066] In a specific example, the back surface of the silicon substrate 101 is sequentially provided with a tunneling layer 104, a doped layer 105, and a passivation layer 106. The gate line is provided on the passivation layer 106 and electrically contacts the doped layer 105 through the passivation layer 106. The line mark 103 is formed on the silicon substrate 101. At the line mark 103, the sequentially stacked tunneling layer 104, doped layer 105, and passivation layer 106 form corresponding recesses following the profile of the line mark 103. The doped layer 105 is provided on the line mark 103, which can avoid the problems of poor passivation and low efficiency caused by preparing the doped layer 105 on the textured surface.

[0067] The tunneling layer 104 is composed of one or more of an oxide layer, a nitride layer, an oxynitride layer, a carbide layer, and an amorphous silicon layer. Of course, in other embodiments, other materials can also be used. The provision of the tunneling layer 104 can achieve efficient selective tunneling transmission of carriers, greatly reduce the surface recombination loss caused by direct contact between the metal electrode and the silicon substrate 101, and significantly improve the open-circuit voltage and the fill factor.

[0068] The passivation layer 106 is composed of one or more of an oxide layer, a nitride layer, an oxynitride layer, a carbide layer, and an amorphous silicon layer. As some examples of the present application, for example, the passivation layer can be made of a single material, a combination of multiple materials, or a combination of multiple layers of different refractive indexes of a single material. It can be understood that the specific structure of the passivation layer includes but is not limited to the above-mentioned several ways. The passivation layer is set according to the actual use needs, which is not limited here. The provision of the passivation layer 106 neutralizes the dangling bonds on the surface of the textured region, passivates the defects of the textured region, and reduces the recombination centers.

[0069] For example, the passivation layer 106 can be one or more of a titanium dioxide layer, a zinc oxide layer, a silicon oxide layer, an aluminum oxide layer, silicon nitride, silicon oxynitride. Further, the advantages of using one or more of a titanium dioxide layer, a zinc oxide layer, a silicon oxide layer, an aluminum oxide layer, silicon nitride, silicon oxynitride to form the passivation layer are as follows: the titanium dioxide (TiO2) layer has a high refractive index (about 2.4%), which can be used as an anti-reflection layer to improve light absorption. The zinc oxide (ZnO) layer is a transparent conductive material that can simultaneously improve light transmittance and electrical conductivity. At the same time, zinc oxide has a low refractive index (about 2.0%), which can reduce light reflection. The silicon dioxide (SiO2) layer has stable insulation properties, can prevent charge leakage, and is easy to prepare by mature processes such as thermal oxidation. The aluminum oxide (Al2O3) layer has a high breakdown voltage and can work stably at high voltage. At the same time, aluminum oxide has excellent insulation properties, which can further improve the reliability of the device.

[0070] Specifically, the passivation layer 106 can be a titanium dioxide layer, a zinc oxide layer, a silicon oxide layer, an aluminum oxide layer, or a combination of a titanium dioxide layer and a zinc oxide layer, a combination of a zinc oxide layer, a silicon oxide layer, and an aluminum oxide layer, or a combination of at least any two of a titanium dioxide layer, a zinc oxide layer, a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer, without limitation.

[0071] Further, the angle between the edge of the doped layer 105 and the line mark 103 is 0-15°.

[0072] The silicon substrate 101 is usually obtained by processing a single crystal silicon rod, which is usually grown by the Czochralski method or the zone melting method. The single crystal silicon rod is cut into the silicon substrate 101 by a cutting process, and the growth angle of the single crystal and the cutting direction jointly determine the extension direction of the line mark 103.

[0073] The doped layer 105 is formed on the surface of the silicon wafer by diffusion or ion implantation, and after the preparation of the doped layer 105, the doped layer 105 is patterned using laser etching technology. The direction of laser etching is consistent with the extension direction of the edge of the doped layer 105.

[0074] The angle between the edge of the doped layer 105 and the line mark 103 is 0–15°, which allows a synergistic light reflection and absorption mechanism to be formed between them. When light shines on the surface of the battery, the appropriately angled edge of the doped layer 105 and the line mark 103 can cause multiple reflections and refractions of the light between them, increasing the propagation path and residence time of the light inside the battery and improving the light absorption efficiency. For example, the light may first be reflected at the edge of the doped layer 105 and then enter the line mark 103 for further reflection and scattering.

[0075] In some embodiments, the gate line 102 is at least partially disposed on the trace 103. The gate line 102 is a conductive line for collecting the current generated by the battery. Compared to a planar position, the recessed trace 103 has a larger surface area, increasing the contact area between the gate line 102 and the silicon substrate 101. Just as in connecting circuits, a larger contact area can reduce contact resistance and improve current transmission efficiency. For example, when charge carriers generated by the battery are transported to the region of the trace 103, since the gate line 102 is partially disposed on the trace 103, the charge carriers can be more easily collected by the gate line 102, reducing the loss of charge carriers during transmission.

[0076] Example Two

[0077] like Figure 4 As shown, in some embodiments, the surface of the line mark 103 has a textured structure 1031. The line mark 103 itself is an arc-shaped concave structure, and the texture on its surface is a more subtle pattern on the concave surface, increasing the microscopic complexity of the surface. This can further change the optical and electrical properties of the surface of the line mark 103, causing the light irradiated onto the surface of the line mark 103 to undergo more complex scattering and reflection, further increasing the propagation path and residence time of light inside the battery, and improving the battery's light absorption efficiency. For example, when light irradiates the textured surface of the line mark 103, some of the light will be reflected multiple times at the protrusions and depressions of the texture. Light that might have been directly reflected out of the battery has a greater chance of being absorbed by the battery and converted into electrical energy after being scattered multiple times.

[0078] Furthermore, the texture structure 1031 is shaped like a ">", with its sharp corners pointing towards the extension direction of the line mark 103. This ">" shaped texture structure 1031 can guide light to propagate in a specific direction. When light shines on the ">" shaped texture, the shape of the sharp corners causes the light to refract and reflect in the direction of the line mark 103, making the light propagate more orderly inside the battery and reducing disordered scattering losses. It should be noted that the line mark 103 has two opposing ends; it can extend to one end or to the other. Therefore, the line mark 103 has two extension directions, and the sharp corners of the different texture structures 1031 can point towards two opposing directions.

[0079] In some embodiments, the two adjacent texture structures 1031 are oppositely arranged at the sharp corners, and the length between the two sharp corners is 10-40 μm. In this size range, the movement path and distribution of the carriers inside the battery are more reasonable, and the shorter distance between the sharp corners avoids the problem of increased recombination probability of the carriers during the diffusion process due to the excessive distance, effectively reducing the interface recombination. In the wet process of battery manufacturing, the liquid needs to flow in the texture structure to remove impurities and defects, and the sharp corner distance of 10-40 μm provides a suitable flow channel for the wet liquid. If the distance is too small, the liquid flow resistance increases, and it is difficult to flow into the interior of the texture structure; while if the distance is too large, the liquid's flushing and carrying capacity for defects will be weakened. In this specific size range, the wet liquid can fully contact each part of the texture structure, effectively carrying out the defects therein, and reducing the surface defect state. At the same time, this size can increase the roughness of the battery surface, and the increase in roughness provides more attachment points for these layers, so that the passivation layer 106, the grid line 102 and the doped layer 105 can be more firmly attached to the surface of the silicon substrate 101, improving the reliability of the battery structure and reducing problems such as passivation failure caused by poor adhesion.

[0080] Specifically, the two adjacent texture structures 1031 form at least one of a rhombus, a square, and a rectangle.

[0081] Further, the distance between the adjacent texture structures 1031 is greater than 5 μm. If the distance is too small, such as less than 5 μm, the adjacent texture structures 1031 are densely arranged, and the light may be absorbed multiple times between the dense textures and cannot be effectively transmitted to the interior of the battery. The distance between the texture structures 1031 is greater than 5 μm, which can avoid the problem of excessive mutual interference and absorption of light between the textures caused by too dense textures, and ensure that the light can have enough space to propagate and reflect between the textures, thereby fully playing the role of the texture structure 1031 in regulating the light.

[0082] In some embodiments, when at least one of the first doped region and the second doped region is polished, a plurality of topographic regions of polishing topography can be formed in the first doped region or the second doped region by an alkaline solution or an acid solution wet etching process. When the acid solution is used for wet etching, the solution can be hydrofluoric acid or nitric acid, etc. The acid solution wet process can use potassium hydroxide, sodium hydroxide, etc.

[0083] For example, at least one of the first doped region and the second doped region is polished to form a plurality of topographic regions of polishing topography by using an alkaline solution or an acid solution, and a mask is used to block a local region, so that the etching rates of different regions are different, and the polishing degrees of different topographic regions are different.

[0084] For example, the morphology region with different tower base morphology can be formed by controlling the concentration of the alkali solution or the acid solution, the reaction time, and the reaction temperature for polishing at least one of the first doped region and the second doped region. For example, the wet etching process of the first morphology region of the first doped region uses potassium hydroxide with a concentration of 1-3%, an additive concentration of 0.5-1.5%, a reaction temperature of 60-80°C, and a reaction time of 100-400 seconds. The wet etching process of the second morphology region of the first doped region uses potassium hydroxide with a concentration of 3-10%, an additive concentration of 0.5-1.5%, a reaction temperature of 70-90°C, and a reaction time of 100-300 seconds.

[0085] In this embodiment, since the texture structure 1031 is to be formed on the surface of the line mark 103, the surface of the line mark 103 can be polished at the same time when the alkali solution is used to polish at least one of the first doped region and the second doped region, so as to form a regular texture structure 1031. Since the regular texture structure 1031 is formed, the light can be guided to propagate along a specific direction. When the light is irradiated on the ">"-shaped texture, the sharp angle shape causes the light to be refracted and reflected towards the extension direction of the line mark 103, so that the light is more orderly propagated inside the battery, and the loss of the light due to disordered scattering is reduced.

[0086] Example Three

[0087] In some embodiments, the opening of the line mark 103 is wavy along the extension direction of the line mark 103. The line mark 103 is a concave structure, and the opening of the line mark 103 is the edge position of the concave surface. The wavy structure makes the opening of the line mark 103 a curve with ups and downs. On the one hand, the wavy opening can change the reflection and refraction path of the light, increase the propagation path and reflection times of the light inside the battery, and improve the light absorption efficiency of the battery. On the other hand, the solar cell 100 generally includes a silicon substrate 101 and functional layers stacked on the silicon substrate 101, and the outermost functional layer is a passivation layer 106. The wavy opening provides a larger adhesion area for the passivation layer 106, increases the contact area between the passivation layer 106 and the surface of the line mark 103, and enables the passivation layer 106 to be more firmly attached to the line mark 103, thereby improving the bonding force.

[0088] In some embodiments, the distance between the wave peaks and wave troughs of the wavy structure formed by the line scratches 103 is less than 10 μm. A suitable wave peak to wave trough distance can allow suitable scattering and reflection of light on the wavy structure. If the distance is too large, such as greater than 10 μm, light can directly pass over the wave peaks and wave troughs without being sufficiently regulated by the wavy structure.

[0089] Example Four

[0090] The present embodiment provides a battery assembly comprising the solar cell 100 described above.

[0091] The battery assembly can comprise a plurality of back contact solar cells 100, and the plurality of back contact solar cells 100 in the battery assembly can be sequentially connected in series to form a cell string. Each cell string can be connected in series, in parallel, or in a combination of series and parallel to achieve a current output. For example, the connection between each cell can be achieved by welding a ribbon, and the connection between each cell string can be achieved by a busbar.

[0092] The battery assembly can further comprise a metal frame, a back plate, a photovoltaic glass, and a glue film (none of which is shown in the figures). The glue film can be filled between the light-receiving surface of the solar cell 100 and the photovoltaic glass, the back surface and the back plate, and adjacent cell pieces, etc. as a filler. The glue film can be a transparent glue with good light transmission and aging resistance, such as EVA glue film or POE glue film, which can be selected according to actual conditions without limitation.

[0093] The photovoltaic glass can be covered on the glue film of the light-receiving surface of the solar cell 100. The photovoltaic glass can be super white glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, the light transmittance of super white glass can be more than 92%, which can protect the solar cell 100 without affecting its efficiency as much as possible. At the same time, the glue film can bond the photovoltaic glass and the solar cell 100 together, and the presence of the glue film can seal and insulate the solar cell 100 and prevent water and moisture.

[0094] The back plate can be attached to the glue film on the back surface of the solar cell 100. The back plate can protect and support the solar cell 100, and has reliable insulation, water resistance, and aging resistance. The back plate can have multiple options, such as tempered glass, organic glass, aluminum alloy TPT composite glue film, etc., which can be set according to specific conditions without limitation. The whole of the back plate, the solar cell 100, the glue film, and the photovoltaic glass can be arranged on the metal frame, which serves as the main external support structure of the entire battery assembly and can stably support and install the battery assembly. For example, the battery assembly can be installed at the desired installation location through the metal frame.

[0095] The battery assembly of the present embodiment has the same advantages as the solar cell 100 described above, and thus will not be repeated here.

[0096] Example Five

[0097] The present embodiment provides a photovoltaic system, which comprises the battery assembly described above.

[0098] The photovoltaic system can be applied in a photovoltaic power station, such as a ground power station, a roof power station, a water surface power station, etc., and can also be applied in a device or apparatus that utilizes solar energy to generate power, such as a user solar power source, a solar street lamp, a solar car, a solar building, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to the above, that is, the photovoltaic system can be applied in all fields that need to utilize solar energy to generate power. Taking a photovoltaic power generation system network as an example, the photovoltaic system can comprise a photovoltaic array, a combiner box and an inverter, the photovoltaic array can be an array combination of a plurality of battery assemblies, for example, a plurality of battery assemblies can form a plurality of photovoltaic arrays, the photovoltaic arrays are connected to the combiner box, the combiner box can combine the currents generated by the photovoltaic arrays, the combined currents flow through the inverter to be converted into alternating current required by a power grid, and then the converted alternating current is connected to a power network to realize solar power supply.

[0099] The photovoltaic system of the present embodiment has the same advantages as the battery assembly described above, and thus will not be repeated here.

[0100] The above only describes the preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A solar cell, characterized by, The application relates to a silicon substrate, which comprises a plurality of grid lines and a plurality of line marks arranged side by side on the back surface of the silicon substrate along a first direction, wherein the grid lines extend along a second direction, and the line marks are concave structures. The included angle between the line marks and the grid lines is 0-15 degrees, and the cross section of the line marks is in the shape of a circular arc. The surface of the line marks has a texture structure, the texture structure is in the shape of "> ", and the sharp corners of the texture structure face the extending direction of the line marks. The sharp corners of at least two adjacent texture structures are arranged reversely, and the length between the two sharp corners is 10-40 microns.

2. The solar cell of claim 1, wherein, Two adjacent texture structures enclose at least one of a rhombus, a square and a rectangle.

3. The solar cell of claim 2, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. The distance between adjacent texture structures is greater than 5 microns.

4. The solar cell of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of silver, aluminum, gold, copper, and combinations thereof. The opening of the line mark is in the shape of a wave along the extending direction of the line mark.

5. The solar cell of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of silver, aluminum, gold, copper, and combinations thereof. The distance between the wave crest and the wave trough of the wave is less than 10 microns.

6. The solar cell of claim 5, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. The depth of the line mark is 0.5-5 microns.

7. The solar cell of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of silver, aluminum, gold, copper, and combinations thereof. The width of the line mark is 10-80 microns.

8. The solar cell of claim 1, wherein, The radius of curvature of the line mark is 50-200 microns.

9. The solar cell of claim 1, wherein, The depth of the circular arc of the cross section of the line mark is different at different positions.

10. The solar cell of claim 1, wherein, The depth difference of the circular arc of the cross section of the line mark at different positions is less than 5 microns.

11. The solar cell of claim 10, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. A doped layer is arranged on the back surface of the silicon substrate, a plurality of grid lines are arranged side by side on the doped layer, and the forming area of the line mark is covered with the doped layer.

12. The solar cell of claim 1, wherein, The included angle between the edge of the doped layer and the line mark is 0-15 degrees.

13. The solar cell of claim 12, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. The grid lines are at least partially arranged on the line mark.

14. The solar cell of claim 12, wherein the first and second doped regions are formed by implanting dopants into the first and second surfaces of the substrate. The grid lines comprise first-polarity grid lines and second-polarity grid lines, and the polarities of the first-polarity grid lines and the second-polarity grid lines are different.

15. The solar cell of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of silver, aluminum, gold, copper, and combinations thereof. First-doped areas and second-doped areas are alternately arranged on the back surface along the first direction, the first-polarity grid lines are arranged on the first-doped areas, and the second-polarity grid lines are arranged on the second-doped areas.

16. The solar cell of claim 15, wherein the first and second conductive layers are formed of a material selected from the group consisting of silver, aluminum, copper, and combinations thereof. A plurality of grid lines and a plurality of line marks are arranged side by side on the light-receiving surface of the silicon substrate along the first direction, the grid lines extend along the second direction, the line marks are circular-arc concave structures, and the included angle between the line marks and the grid lines is 0-15 degrees, wherein the polarities of the grid lines arranged on the light-receiving surface and the grid lines arranged on the back surface are different.

17. The solar cell of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of silver, aluminum, gold, copper, and combinations thereof. The application further relates to a solar cell comprising any one of the silicon substrates as claimed in claims 1-17.

18. A battery assembly characterized by, The application further relates to a battery assembly comprising the battery as claimed in claim 18.

19. A photovoltaic system characterized by, ​