Display device

Abstract

A display device includes: a first substrate including a display element layer; a second substrate facing the first substrate; and a sealing member between the first substrate and the second substrate, in which the second substrate includes: a base layer including a display area overlapping the display element layer and a non-display area surrounding the display area; a light blocking pattern in the non-display area of the base layer; a first dummy pattern between the light blocking pattern and the sealing member in the non-display area; a low refractive layer in the non-display area and the display area, and interrupted by the first dummy pattern; and a second dummy pattern covering the first dummy pattern in the non-display area.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0179930, filed on December 12, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. BACKGROUND

[0004] Recently, as interest in information display has increased, research and development on display devices have been continuously conducted.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and therefore it may contain information that does not constitute prior art. SUMMARY

[0006] Various embodiments of the present disclosure can provide a display device having relatively improved reliability.

[0007] In addition, various embodiments of the present disclosure are directed to a method of manufacturing a display device.

[0008] According to some embodiments of the present disclosure, a display device includes a first substrate including a display element layer, a second substrate facing the first substrate, and a sealing member between the first substrate and the second substrate. According to some embodiments, the second substrate can include a base layer including a display area overlapping the display element layer and a non-display area surrounding the display area, a light-blocking pattern disposed in the non-display area of the base layer, a first dummy pattern disposed between the light-blocking pattern and the sealing member in the non-display area, a low-refraction layer disposed in the non-display area and the display area and interrupted by the first dummy pattern, and a second dummy pattern covering the first dummy pattern in the non-display area.

[0009] According to some embodiments, the first dummy pattern can include an organic material.

[0010] According to some embodiments, the first dummy pattern can have a shape protruding from the light-blocking pattern in a direction toward the sealing member.

[0011] According to some embodiments, the first dummy pattern can include a plurality of first dummy patterns.

[0012] According to some embodiments, the low-refraction layer can be disposed between the plurality of first dummy patterns adjacent to each other in the non-display area.

[0013] According to some embodiments, the second substrate can further include: a bank in the display area and including a plurality of openings in the bank; and the color conversion pattern disposed in at least one of the plurality of openings and the light scattering pattern disposed in another of the plurality of openings. According to some embodiments, the second dummy pattern can include the same material as the bank.

[0014] According to some embodiments, the first dummy pattern can include the same material as the light scattering pattern.

[0015] According to some embodiments, each of the first dummy pattern and the light scattering pattern can include a base resin in which scattering particles are located.

[0016] According to some embodiments, the first dummy pattern can be in a layer different from the light scattering pattern.

[0017] According to some embodiments, the second substrate can further include: a first cap layer on the first dummy pattern and the low-refraction layer in a direction toward the sealing member; and a second cap layer on the second dummy pattern, the first cap layer, and the bank in the direction toward the sealing member.

[0018] According to some embodiments, each of the first cap layer and the second cap layer can include an inorganic material.

[0019] According to some embodiments, the base layer can include a dummy pixel area adjacent to the display area and corresponding to at least one area of the non-display area.

[0020] According to some embodiments, the second substrate can further include: a color filter layer disposed in the display area and the non-display area and between the low-refraction layer and the base layer. According to some embodiments, the color filter layer can include a first color filter, a second color filter, and a third color filter.

[0021] According to some embodiments, in the non-display area, the first color filter, the second color filter, and the third color filter can be stacked on each other to form a light-blocking pattern.

[0022] According to some embodiments, the display device can further include: a filling layer between the first substrate and the second substrate. According to some embodiments, the filling layer can extend from the display area to the non-display area and have at least a portion covered with the sealing member.

[0023] According to some embodiments, the display element layer can include: a transistor on the substrate and corresponding to the display area; and a light emitting element on the transistor and including an emission layer.

[0024] A method of manufacturing a display device according to some embodiments of the present disclosure can include forming a first substrate including a display element layer; forming a second substrate facing the first substrate; and bonding the first substrate and the second substrate to each other by a sealing member. According to some embodiments, the second substrate can include a base layer including a display area overlapping the display element layer and a non-display area surrounding the display area; a light-blocking pattern disposed in the non-display area of the base layer; a first dummy pattern disposed in the non-display area between the light-blocking pattern and the sealing member; a low-refraction layer disposed in the non-display area and the display area and interrupted by the first dummy pattern; an optical layer in the display area and including a bank in the display area and including a plurality of openings in the bank; and a color conversion pattern disposed in at least one of the plurality of openings and a light scattering pattern disposed in another of the plurality of openings; and a second dummy pattern covering the first dummy pattern in the non-display area.

[0025] According to some embodiments, the first dummy pattern can include an organic material. According to some embodiments, the second dummy pattern can include the same material as the bank.

[0026] According to some embodiments, forming the second substrate can include forming a first color filter, a second color filter, and a third color filter on one surface of the base layer in the display area and forming the light-blocking pattern on the one surface of the base layer in the non-display area; forming the first dummy pattern on the light-blocking pattern; forming the low-refraction layer on the first dummy pattern and the first color filter to the third color filter; forming a first cap layer on the low-refraction layer and the first dummy pattern; forming the second dummy pattern on the first cap layer on the first dummy pattern and forming the bank on the first cap layer in the display area; forming the color conversion pattern and the light scattering pattern in corresponding ones of the plurality of openings of the bank, respectively; and forming a second cap layer on the second dummy pattern, the bank, the color conversion pattern, the light scattering pattern, and the first cap layer. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a schematic plan view illustrating a display device according to some embodiments.

[0028] Figure 2 is a schematic cross-sectional view illustrating Figure 1 the display device illustrated in FIG. 1A.

[0029] Figure 3 is a circuit diagram schematically illustrating an electrical connection relationship of components included in Figure 1 a sub-pixel illustrated in FIG. 1A.

[0030] Figure 4 is a schematic plan view illustrating an aspect of one of the pixels of Figure 1 the display device according to some embodiments.

[0031] Figure 5 is a schematic cross-sectional view taken along line II-II’ of Figure 4

[0032] Figure 6 is a schematic cross-sectional view illustrating aspects of the emission structure in one of the first light emitting element to the third light emitting element of Figure 5

[0033] Figures 7 to 10 is a schematic cross-sectional view taken along line I-I’ of Figure 1

[0034] Figures 11 to 19 is a schematic cross-sectional view illustrating a method of forming the second substrate of Figure 7 DETAILED DESCRIPTION

[0035] As the present disclosure allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to particular modes of practice, and it is to be understood that all changes, equivalents, and substitutes fall within the technical scope of the present disclosure.

[0036] Throughout the present disclosure, like reference numerals refer to like parts throughout the various drawings and embodiments of the present disclosure. The size of the elements in the drawings can be exaggerated for the purpose of illustration. It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element could be termed a first element.

[0037] ​​​​It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, in the case where a first portion is on a second portion, the first portion can not only be directly on the second portion, but a third portion can be interposed therebetween. In addition, in the case where it is stated that a first portion is formed on a second portion, such as a layer, film, region, or plate, a surface of the second portion on which the first portion is formed is not limited to an upper surface of the second portion, but can include other surfaces such as a side surface or a lower surface of the second portion. Conversely, in the case where it is stated that a first portion is under a second portion, such as a layer, film, region, or plate, the first portion can not only be directly under the second portion, but a third portion can be interposed therebetween.

[0038] Aspects of some embodiments of the present disclosure are described in more detail with reference to the accompanying drawings, in order to describe aspects of some embodiments of the present disclosure in more detail, so that those of ordinary skill in the art to which the present disclosure pertains can easily practice embodiments according to the present disclosure. In addition, the singular form can include the plural form as long as it is not specifically mentioned in the sentence.

[0039] Figure 1 is a schematic plan view illustrating a display device DD according to some embodiments.

[0040] In Figure 1 , for the purpose of illustration, a structure of the display device DD is schematically illustrated, for example, a display panel DP is provided in the display device DD, centered on a display area DA formed to display an image.

[0041] Referring to Figure 1 , the display panel DP (or the display device DD) can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be arranged around the display area DA (for example, at a periphery of the display area DA or outside a coverage area of the display area DA).

[0042] The display panel DP can include a substrate SUB, a sub-pixel SP, and a pad PD.

[0043] The substrate SUB can include a transparent insulating material to allow light transmission. The substrate SUB can be a rigid substrate or a flexible substrate.

[0044] For example, the rigid substrate can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0045] The flexible substrate can be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0046] One area on the substrate SUB can be provided as a display area DA in which the sub-pixels SP (or the pixels PXL) are located, and another area on the substrate SUB can be provided as a non-display area NDA. For example, the substrate SUB can include a display area DA including a plurality of pixel areas in which the corresponding sub-pixels SP (or the pixels PXL) are located, and a non-display area NDA arranged around a periphery of the display area DA (e.g., in a peripheral area of the display area DA or outside of an area of coverage) (or adjacent to the display area DA).

[0047] The display area DA can have various shapes. For example, the display area DA can be provided in a plan view in various forms or shapes such as a closed polygon including sides formed of linear lines, a circular or elliptical shape including sides formed of curved lines, and a semi-circular or semi-elliptical shape including sides formed of linear lines and curved lines, and the like.

[0048] The non-display area NDA can be provided at least one side of the display area DA. For example, the non-display area NDA can surround a periphery of the display area DA. The sub-pixels SP can be arranged in a matrix (e.g., rows and columns of the sub-pixels SP) on the substrate SUB in a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of the sub-pixels SP is not limited thereto. For example, the sub-pixels SP can be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. For example, the first direction DR1 can refer to a row direction, and the second direction DR2 can refer to a column direction.

[0049] Two or more sub-pixels SP among the plurality of sub-pixels SP can form one pixel PXL, but embodiments according to the disclosure are not limited thereto.

[0050] The components for controlling the sub-pixels SP can be located in the non-display area NDA on the substrate SUB. For example, lines electrically connected to the sub-pixels SP can be located in the non-display area NDA. The lines can include, for example, gate lines and data lines, and the like.

[0051] The driver electrically connected to the sub-pixel SP to drive the sub-pixel SP can be located (or integrated in) the non-display area NDA of the display panel DP. Also, the pad PD can be located in the non-display area NDA on the substrate SUB. The pad PD can be electrically connected to the sub-pixel SP through a wire. For example, the pad PD can be electrically connected to the sub-pixel SP through a data line.

[0052] According to some embodiments, the circuit board can be electrically connected to the pad PD through a conductive adhesive member such as an anisotropic conductive film. The circuit board can be a flexible circuit board or a flexible film made of a flexible material. The driver can be mounted on the circuit board and electrically connected to the pad PD.

[0053] According to some embodiments, the display panel DP can have a planar display surface. According to some embodiments, the display panel DP can have a display surface that is at least partially circular. According to some embodiments, the display panel DP can be bendable, foldable, or rollable. In the above cases, the display panel DP and / or the substrate SUB can include a material having a flexible property.

[0054] Figure 2 is a schematic cross-sectional view of a display device DD. Figure 1

[0055] Referring to Figure 1 and Figure 2 , the display device DD (or the display panel DP) can include a first substrate 100, a second substrate 200, and a sealing member 300. The sealing member 300 can couple the first substrate 100 and the second substrate 200 to each other. The first substrate 100 and the second substrate 200 can include a display area (referring to "DA" of Figure 1 ) and a non-display area (referring to "NDA" of Figure 1 ).

[0056] The first substrate 100 can include a plurality of sub-pixels (referring to "SP" of Figure 1 ) {or pixels (referring to "PXL" of Figure 1 )} for displaying an image. The sub-pixels SP can be located in the display area DA of the first substrate 100. Each of the sub-pixels SP (or the pixels PXL) can include a light emitting element configured to emit light and a circuit element (or a driving element) configured to drive the light emitting element. For example, the light emitting element can be an organic light emitting diode, and the circuit element can be a transistor, but embodiments of the disclosure are not limited thereto.

[0057] The second substrate 200 can include an optical layer configured to selectively convert or transmit light emitted from the light emitting element. For example, the optical layer can be located in the display area DA of the second substrate 200 and can convert or transmit as is the wavelength of light emitted from the light emitting element of the first substrate 100.​

[0058] The first substrate 100 and the second substrate 200 can be coupled to each other by the sealing member 300. The sealing member 300 can be located in the non-display area NDA between the first substrate 100 and the second substrate 200. For example, the sealing member 300 can not be located in the display area DA and can be located in the non-display area NDA between the first substrate 100 and the second substrate 200 to enclose the display area DA. For example, the sealing member 300 can have various planar shapes according to the planar shape of the first substrate 100 and / or the second substrate 200.

[0059] The sealing member 300 can include a glass frit or the like. According to some embodiments, the sealing member 300 can include a photocurable resin such as an epoxy acrylate resin, a polyester acrylate resin, a urethane acrylate resin, a polybutadiene acrylate resin, a silicone acrylate resin, and an alkyl acrylate resin. For example, laser light can be irradiated to the sealing member 300 coated between the first substrate 100 and the second substrate 200. The sealing member 300 can be cured by the laser light, thus sealing the first substrate 100 and the second substrate 200. According to some embodiments, the sealing member 300 can control the flow of monomers included in the encapsulation layer in the first substrate 100, thus defining the location where the monomers are formed.

[0060] The filling layer 400 can be located in the display area DA between the first substrate 100 and the second substrate 200. The filling layer 400 can perform a shock-absorbing function with respect to external pressure applied to the display device DD (or the display panel DP), but embodiments according to the present disclosure are not limited thereto. The filling layer 400 can maintain a gap between the first substrate 100 and the second substrate 200. The filling layer 400 can extend from the display area DA to the non-display area NDA between the first substrate 100 and the second substrate 200 and have at least a portion covered with the sealing member 300, thus being connected to (or contacting) the sealing member 300.

[0061] The filling layer 400 can include a material that allows light to pass therethrough. For example, the filling layer 400 can include an organic material such as silicone, epoxy, or epoxy acrylate resin. In addition, the filling layer 400 can include a suitable material for refractive index matching.

[0062] Figure 3 is a circuit diagram schematically illustrating an electrical connection relationship of components included in the sub-pixel SP illustrated in Figure 1 is a circuit diagram schematically illustrating an electrical connection relationship of components included in the sub-pixel SP illustrated in Figure 3The various components are illustrated in the sub-pixel SP, but embodiments according to the present disclosure are not limited thereto. For example, the sub-pixel SP can include additional components or fewer components according to various embodiments without departing from the spirit and scope of embodiments according to the present disclosure. For ease of description, Figure 3 A sub-pixel SP located on an i-th horizontal line (or i-th pixel row) and connected to a j-th data line Dj is illustrated.

[0063] Referring to Figures 1 to 3 The sub-pixel SP can be located on an i-th horizontal line (or i-th pixel row). The sub-pixel SP can include a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a storage capacitor Cst.

[0064] The light emitting element LD can include a first electrode electrically connected to the fourth node N4 and a second electrode electrically connected to the fourth power line PL4. The light emitting element LD can emit light of a certain brightness corresponding to an amount of current (or driving current) supplied from the first transistor T1. According to some embodiments, the light emitting element LD can be an organic light emitting diode including an organic light emitting layer.

[0065] The first transistor T1 (or driving transistor) can be electrically connected between the first power line PL1 and the first electrode of the light emitting element LD. The first transistor T1 can include a gate electrode electrically connected to the first node N1. The first transistor T1 can control an amount of current (or driving current) flowing from the first power line PL1 to the fourth power line PL4 via the light emitting element LD based on a voltage of the first node N1. A first power voltage VDD can be applied to the first power line PL1. A second power voltage VSS can be applied to the fourth power line PL4. The first power voltage VDD can be set to a voltage higher than the second power voltage VSS.

[0066] The second transistor T2 can be electrically connected between the j-th data line Dj and the second node N2. A gate electrode of the second transistor T2 can be electrically connected to the 1i-th scan line S1i (or first scan line). In a case where a first scan signal GW[i] (e.g., a first scan signal of a low level) is supplied to the 1i-th scan line S1i, the second transistor T2 can be turned on to electrically connect the j-th data line Dj to the second node N2. If each of the first transistor T1 and the third transistor T3 is turned on, the second transistor T2 can transmit a data signal of the j-th data line Dj to the second node N2 in response to the first scan signal GW[i].

[0067] The third transistor T3 can be electrically connected between the first node N1 and the third node N3. A gate electrode of the third transistor T3 can be electrically connected to the 1st i scan line S1i. In a case where the first scan signal GW[i] is supplied to the 1st i scan line S1i, the third transistor T3 can be turned on. If the third transistor T3 is turned on, the first transistor T1 can have a diode-connected form.

[0068] The fourth transistor T4 can be electrically connected between the first node N1 and the second power line PL2. A gate electrode of the fourth transistor T4 can be electrically connected to the 2nd i scan line S2i (or second scan line). The first initialization power voltage Vint1 can be applied to the second power line PL2. The fourth transistor T4 can be turned on in response to the second scan signal GI[i]. If the fourth transistor T4 is turned on, the first initialization power voltage Vint1 can be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0069] The fifth transistor T5 can be electrically connected between the first power line PL1 and the second node N2. A gate electrode of the fifth transistor T5 can be electrically connected to the i-th emission control line Ei (or emission control line). The sixth transistor T6 can be electrically connected between the third node N3 and the light emitting element LD (or the fourth node N4). A gate electrode of the sixth transistor T6 can be electrically connected to the i-th emission control line Ei. The fifth transistor T5 and the sixth transistor T6 can be turned off in a case where the emission control signal EM[i] (e.g., the emission control signal EM[i] of a high level) is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0070] The seventh transistor T7 can be electrically connected between the first electrode of the light emitting element LD (i.e., the fourth node N4) and the third power line PL3. A gate electrode of the seventh transistor T7 can be electrically connected to the 3rd i scan line S3i (or third scan line). The second initialization power voltage Vint2 can be applied to the third power line PL3. According to some embodiments, the second initialization power voltage Vint2 can be the same as or different from the first initialization power voltage Vint1. The seventh transistor T7 can be turned on by the third scan signal GB[i] supplied to the 3rd i scan line S3i to supply the second initialization power voltage Vint2 to the first electrode of the light emitting element LD.

[0071] The storage capacitor Cst can be connected or formed between the first power line PL1 and the first node N1.

[0072] According to some embodiments, the pixel circuit PXC can include P-type transistors and N-type transistors. The third transistor T3 and the fourth transistor T4 can each be formed of an oxide semiconductor transistor including an oxide semiconductor layer. For example, each of the third transistor T3 and the fourth transistor T4 can be formed of an N-type oxide semiconductor transistor and include an oxide semiconductor layer as an active layer, but is not limited thereto. The oxide semiconductor transistor can be produced by a low-temperature process and has a low charge mobility compared to that of a polysilicon semiconductor transistor. In other words, the oxide semiconductor transistor can have excellent off-current characteristics. Thus, a leakage current between the third transistor T3 and the fourth transistor T4 can be minimized.

[0073] Each of the remaining transistors other than the third transistor T3 and the fourth transistor T4 (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) can be formed of a polysilicon semiconductor transistor including a silicon semiconductor and can include a polysilicon semiconductor layer as an active layer. For example, the active layer can be formed by a low-temperature polysilicon (LTPS) process. For example, the polysilicon semiconductor transistor can be a P-type polysilicon semiconductor transistor. Since the polysilicon semiconductor transistor has an advantage of high response speed, the polysilicon semiconductor transistor can be applied to a switching element in which high-speed switching operation is required.

[0074] Figure 4 is a schematic plan view of an aspect of one of the pixels PXL of the display panel DP according to some embodiments. Figure 1

[0075] Referring to Figures 1 to 4 , the pixel PXL can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged in a first direction DR1.

[0076] The first sub-pixel SP1 can include a first emission area EMA1 and a non-emission area NEA formed around the first emission area EMA1. The second sub-pixel SP2 can include a second emission area EMA2 and a non-emission area NEA formed around the second emission area EMA2. The third sub-pixel SP3 can include a third emission area EMA3 and a non-emission area NEA formed around the third emission area EMA3.

[0077] The first emission area EMA1 can be an area from which light is emitted from a portion of an emission structure (see "EMS" of Figure 5 corresponding to the first sub-pixel SP1. The second emission area EMA2 can be an area from which light is emitted from a portion of the emission structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 can be an area from which light is emitted from a portion of the emission structure EMS corresponding to the third sub-pixel SP3.​

[0078] The first, second, and third sub-pixels SP1, SP2, and SP3 can have substantially the same surface area, but are not limited thereto. According to some embodiments, the second sub-pixel SP2 can have a surface area greater than that of the first sub-pixel SP1. The third sub-pixel SP3 can have a surface area greater than that of the second sub-pixel SP2.

[0079] Each of the first, second, and third sub-pixels SP1, SP2, and SP3 can have a polygonal shape. For example, each of the first, second, and third sub-pixels SP1, SP2, and SP3 can have a rectangular shape or a hexagonal shape, but are not limited thereto. According to some embodiments, each of the first, second, and third sub-pixels SP1, SP2, and SP3 can have a circular shape, a semi-elliptical shape, or the like.

[0080] Figure 4 The arrangement of sub-pixels illustrated in FIG. 1 is an illustrative example, and embodiments of the present disclosure are not limited thereto. Each pixel PXL can include two or more sub-pixels, and the sub-pixels can be arranged in various ways. Each of the sub-pixels can have various shapes. Each of the emission regions of the sub-pixels can also have various shapes.

[0081] Figure 5 is a schematic cross-sectional view taken along line II-II’ of Figure 4 .

[0082] For ease of description, in Figure 5 , a simple diagram shows a cross-sectional structure (or a stack structure) of a pixel PXL of the display device DD formed on a substrate SUB, and a thickness direction of the substrate SUB is indicated in a third direction DR3.

[0083] Referring to Figures 1 to 5 , the display device DD can include one or more pixels PXL located in a display area DA. The pixel PXL can be provided in a pixel area of the display area DA.

[0084] The pixel PXL can include one or more sub-pixels SP. For example, the pixel PXL can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. According to some embodiments, the first sub-pixel SP1 can be a green sub-pixel, the second sub-pixel SP2 can be a red sub-pixel, and the third sub-pixel SP3 can be a blue sub-pixel, but embodiments according to the present disclosure are not limited thereto. In the following embodiments, the term “sub-pixel SP” will be used to collectively designate the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0085] Each of the first, second, and third sub-pixels SP1, SP2, and SP3 can include the first substrate 100 and the second substrate 200. The fill layer 400 can be located between the first substrate 100 and the second substrate 200.

[0086] The first substrate 100 can include a substrate SUB, a display element layer DPL, and a package layer TFE. The display element layer DPL can include a pixel circuit layer PCL and a light emitting element layer LDL.

[0087] The substrate SUB can include a transparent insulating material to allow light transmission. The substrate SUB can be a rigid substrate or a flexible substrate.

[0088] The pixel circuit layer PCL and the light emitting element layer LDL can be arranged to overlap each other on one surface of the substrate SUB.

[0089] One or more insulating layers can be located in the pixel circuit layer PCL. For example, the insulating layers can include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a via layer VIA, which are sequentially stacked on the substrate SUB in the third direction DR3. The insulating layers located in the pixel circuit layer PCL are not limited to the foregoing embodiments, and other insulating layers can be added or some of the insulating layers can be omitted.

[0090] The buffer layer BFL can be arranged on the entire surface of the substrate SUB. The buffer layer BFL can prevent or reduce diffusion of impurities into circuit elements (or driving elements) constituting a pixel circuit PXC, such as a transistor. The buffer layer BFL can be an inorganic insulating layer including an inorganic material (or substance). The buffer layer BFL can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). Although the buffer layer BFL can be provided in a single layer structure, the buffer layer BFL can be provided in a multi-layer structure having two or more layers. In the case where the buffer layer BFL has a multi-layer structure, the respective layers can be formed of the same material or different materials. The buffer layer BFL can be omitted depending on the material of the substrate SUB or a processing condition.

[0091] The gate insulating layer GI can be located on the entire surface of the buffer layer BFL. The gate insulating layer GI can include the same material as that of the buffer layer BFL, or include one or more appropriate (or selected) materials among the materials mentioned (or illustrated) as constituent materials of the buffer layer BFL. For example, the gate insulating layer GI can be an inorganic insulating layer including an inorganic material.

[0092] The interlayer insulating layer ILD can be provided and / or formed on the entire surface of the gate insulating layer GI. The interlayer insulating layer ILD can include the same material as that of the buffer layer BFL or include one or more suitable (or selected) materials among the materials mentioned (or illustrated) as constituent materials of the buffer layer BFL.

[0093] The via layer VIA can be provided and / or formed on the entire surface of the interlayer insulating layer ILD. The via layer VIA can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material (or substance). The inorganic insulating layer can include at least one of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). For example, the organic insulating layer can include at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin. According to some embodiments, the via layer VIA can be formed of an organic insulating layer including an organic material.

[0094] The via layer VIA can be partially opened to include a via hole. The via hole can be a connection point for electrically connecting the pixel circuit PXC of the sub-pixel SP with the light emitting element LD.

[0095] Respective circuit elements (or driving elements) of the first to third sub-pixels SP1 to SP3 can be located in the pixel circuit layer PCL. For example, the transistor T_SP1 of the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 can be located in the pixel circuit layer PCL. The transistor T_SP1 of the first sub-pixel SP1 can be one of the transistors included in the pixel circuit PXC of the first sub-pixel SP1. The transistor T_SP2 of the second sub-pixel SP2 can be one of the transistors included in the pixel circuit PXC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 can be one of the transistors included in the pixel circuit PXC of the third sub-pixel SP3. In Figure 5 , one of the transistors of each sub-pixel SP is illustrated for the purpose of clear and brief explanation, and the remaining circuit elements are omitted.

[0096] The transistor T_SP1 of the first sub-pixel SP1 can include a semiconductor pattern SCP, a gate electrode GE, a first terminal EL1, and a second terminal EL2.

[0097] The gate electrode GE can be located on the gate insulating layer GI and covered with the interlayer insulating layer ILD. For example, the gate electrode GE can be a gate conductive layer located between the gate insulating layer GI and the interlayer insulating layer ILD. The gate electrode GE can overlap with a portion of the semiconductor pattern SCP. For example, the gate electrode GE can overlap with an active pattern of the semiconductor pattern SCP.

[0098] The semiconductor pattern SCP can be provided and / or formed on the buffer layer BFL. The semiconductor pattern SCP can be a semiconductor layer formed of polysilicon, amorphous silicon, oxide semiconductor, or the like. The semiconductor pattern SCP can include an active pattern, a first contact region, and a second contact region. Each of the active pattern, the first contact region, and the second contact region can be formed of a semiconductor layer that is not doped with impurities or doped with impurities. For example, each of the first contact region and the second contact region can be formed of a semiconductor layer doped with impurities, and the active pattern can be composed of an undoped semiconductor layer.

[0099] The active pattern of the semiconductor pattern SCP can be a region overlapping with the gate electrode GE and can be a channel region. The first contact region of the semiconductor pattern SCP can contact one end of the active pattern. The first contact region can be electrically connected to the first terminal EL1. The second contact region of the semiconductor pattern SCP can contact the remaining end of the active pattern. The second contact region can be electrically connected to the second terminal EL2.

[0100] The first terminal EL1 can be provided and / or formed on the interlayer insulating layer ILD. For example, the first terminal EL1 can be formed of a source-drain conductive layer formed between the interlayer insulating layer ILD and the via layer VIA. The first terminal EL1 can contact the first contact region of the semiconductor pattern SCP through a contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0101] The second terminal EL2 can be provided and / or formed on the interlayer insulating layer ILD and spaced apart from the first terminal EL1. The second terminal EL2 can be formed of a source-drain conductive layer formed between the interlayer insulating layer ILD and the via layer VIA. The second terminal EL2 can contact the second contact region of the semiconductor pattern SCP through a contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0102] The bottom metal pattern BML can be located under the transistor T_SP1 of the first sub-pixel SP1.

[0103] The bottom metal pattern BML can be a first conductive layer located between the substrate SUB and the buffer layer BFL. According to some embodiments, the bottom metal pattern BML can be electrically connected to the transistor T_SP1 of the first sub-pixel SP1, thus increasing a driving range of a voltage supplied to the gate electrode GE.

[0104] Since the gate electrode GE, the first terminal EL1, and the second terminal EL2 are electrically connected to other circuit elements and / or lines, the transistor T SP1 of the first sub-pixel SP1 can be provided as one of the transistors of the pixel circuit PXC constituting the first sub-pixel SP1.

[0105] Each of the transistor T SP2 of the second sub-pixel SP2 and the transistor T SP3 of the third sub-pixel SP3 can have the same (or substantially the same) configuration as the transistor T SP1 of the first sub-pixel SP1.

[0106] As described above, the pixel circuit layer PCL can include respective circuit elements of the first sub-pixel SP1 to the third sub-pixel SP3.

[0107] The light-emitting element layer LDL can be located on the pixel circuit layer PCL. The light-emitting element layer LDL can include the first lower electrode LE1, the second lower electrode LE2, the third lower electrode LE3, the pixel definition layer PDL, the emissive structure EMS, and the upper electrode UE.

[0108] The first lower electrode LE1 to the third lower electrode LE3 can be respectively arranged in the first sub-pixel SP1 to the third sub-pixel SP3 on the pixel circuit layer PCL (or the via layer VIA). For example, the first lower electrode LE1 can be located on the via layer VIA of the first sub-pixel SP1, the second lower electrode LE2 can be located on the via layer VIA of the second sub-pixel SP2, and the third lower electrode LE3 can be located on the via layer VIA of the third sub-pixel SP3.

[0109] Each of the first lower electrode LE1 to the third lower electrode LE3 can be electrically connected to a circuit element located in the pixel circuit layer PCL through a corresponding via hole passing through the via layer VIA. For example, the first lower electrode LE1 can be electrically connected to the transistor T SP1 of the first sub-pixel SP1 through a first via hole VIH1 passing through the via layer VIA. The second lower electrode LE2 can be electrically connected to the transistor T SP2 of the second sub-pixel SP2 through a second via hole VIH2 passing through the via layer VIA. The third lower electrode LE3 can be electrically connected to the transistor T SP3 of the third sub-pixel SP3 through a third via hole VIH3 passing through the via layer VIA.

[0110] According to some embodiments, each of the first lower electrode LE1, the second lower electrode LE2, and the third lower electrode LE3 can be an anode electrode. When viewed in the third direction DR3, the first lower electrode LE1 to the third lower electrode LE3 can respectively have a shape corresponding to the shape of the pixel circuit layer PCL. Figure 4The first lower electrode LE1 to the third lower electrode LE3 can have similar shapes to the first emission area EMA1 to the third emission area EMA3. For example, the first lower electrode LE1 can have a similar shape to the first emission area EMA1 when viewed in the third direction DR3. The second lower electrode LE2 can have a similar shape to the second emission area EMA2 when viewed in the third direction DR3. The third lower electrode LE3 can have a similar shape to the third emission area EMA3 when viewed in the third direction DR3. However, embodiments of the disclosure are not limited thereto.

[0111] Each of the first lower electrode LE1 to the third lower electrode LE3 can be electrically connected to the corresponding pixel circuit PXC to receive a driving current. The first lower electrode LE1 to the third lower electrode LE3 can include an opaque conductive material to reflect light, but embodiments according to the disclosure are not limited thereto. According to some embodiments, the first lower electrode LE1 to the third lower electrode LE3 can include a transparent conductive material.

[0112] The pixel definition layer PDL can be disposed on the first lower electrode LE1 to the third lower electrode LE3. The pixel definition layer PDL can include a first opening OP1 that exposes a portion of the first lower electrode LE1, a portion of the second lower electrode LE2, and a portion of the third lower electrode LE3, respectively. The pixel definition layer PDL can be a structure for defining (or partitioning) respective emission areas of the first sub-pixel SP1 to the third sub-pixel SP3. For example, the pixel definition layer PDL can define the first emission area EMA1 of the first sub-pixel SP1, the second emission area EMA2 of the second sub-pixel SP2, and the third emission area EMA3 of the third sub-pixel SP3.

[0113] The pixel definition layer PDL can be composed of an organic insulating layer including an organic material. The organic material can include an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin, etc. According to some embodiments, the pixel definition layer PDL can include a light-absorbing material or be coated with a light-absorbing agent, so that the pixel definition layer PDL can function to absorb light introduced from the outside. For example, the pixel definition layer PDL can include a carbon-based black pigment. However, embodiments are not limited to the foregoing examples.

[0114] The pixel definition layer PDL can protrude from the via layer VIA in the third direction DR3.

[0115] The emission structure EMS can be located on the first lower electrode LE1 to the third lower electrode LE3 exposed through the first opening OP1 of the pixel definition layer PDL. The emission structure EMS can include an emission layer configured to generate light, an electron transport part configured to transport electrons, and a hole transport part configured to transport holes, but is not limited thereto.

[0116] According to some embodiments, the emission structure EMS can fill the first opening OP in the pixel definition layer PDL and be disposed on the pixel definition layer PDL, but embodiments according to the present disclosure are not limited thereto. The emission structure EMS can be formed by a process such as vacuum deposition or inkjet printing.

[0117] The emission structure EMS can be located on the upper electrode UE. According to some embodiments, the upper electrode UE can be a cathode electrode. The upper electrode UE can be a common layer commonly provided to the first to third sub-pixels SP1 to SP3. The upper electrode UE can be provided in the form of a plate in the entire area of the display area DA. The upper electrode UE can function as a half mirror that partially transmits and partially reflects light emitted from the emission structure EMS.

[0118] The upper electrode UE can be a thin film metal layer having a thickness that allows light emitted from the emission structure EMS to pass therethrough. The upper electrode UE can be made of a metal material or a transparent conductive material having a relatively small thickness. According to some embodiments, the upper electrode UE can include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. According to some embodiments, the upper electrode UE can include at least one of magnesium, silver, and compounds thereof. However, the material of the upper electrode UE is not limited to the foregoing embodiments.

[0119] The first lower electrode LE1, a portion of the emission structure EMS overlapping the first lower electrode LE1, and a portion of the upper electrode UE overlapping the first lower electrode LE1 can form a first light emitting element LD1. The second lower electrode LE2, a portion of the emission structure EMS overlapping the second lower electrode LE2, and a portion of the upper electrode UE overlapping the second lower electrode LE2 can form a second light emitting element LD2. The third lower electrode LE3, a portion of the emission structure EMS overlapping the third lower electrode LE3, and a portion of the upper electrode UE overlapping the third lower electrode LE3 can form a third light emitting element LD3.

[0120] The encapsulation layer TFE can be located on the upper electrode UE. The encapsulation layer TFE can cover the display element layer DPL. The encapsulation layer TFE can be configured to prevent or reduce penetration of contaminants such as oxygen and / or water, etc. into the light emitting element layer LDL. According to some embodiments, the encapsulation layer TFE can include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layer can include, for example, silicon nitride, silicon oxide, or silicon oxynitride. For example, the organic film can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polystyrene resin, a polyphenylene sulfide resin, or a benzocyclobutene. However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited to the foregoing examples.

[0121] The second substrate 200 can be disposed on the first substrate 100 including the above-described components. The second substrate 200 can face the first substrate 100 in the third direction DR3.

[0122] The second substrate 200 can include a base layer BSL, a color filter layer CFL, a low-refraction layer LRL, a first cover layer CPL1, an optical layer OPL, and a second cover layer CPL2.

[0123] The base layer BSL can be a rigid or flexible substrate, and its material or characteristics are not particularly limited. The base layer BSL can be formed of the same material as that of the substrate SUB, or can be formed of a different material from that of the substrate SUB. The base layer BSL can include a display area DA overlapping the display element layer DPL and a non-display area NDA surrounding the display area DA.

[0124] The color filter layer CFL can be located on one surface of the base layer BSL. The one surface of the base layer BSL can refer to a surface facing the first substrate 100. The color filter layer CFL can include a first color filter CF1, a second color filter CF2, a third color filter CF3, and a light-blocking pattern LBP. The first color filter CF1 can be located on the one surface of the base layer BSL to correspond to the third emission area EMA3 of the third sub-pixel SP3. The second color filter CF2 can be located on the one surface of the base layer BSL to correspond to the second emission area EMA2 of the second sub-pixel SP2. The third color filter CF3 can be located on the one surface of the base layer BSL to correspond to the first emission area EMA1 of the first sub-pixel SP1.

[0125] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be arranged to overlap each other in the non-emission area NEA, thus functioning as the light-blocking pattern LBP for preventing or reducing optical interference between adjacent sub-pixels SP. The light-blocking pattern LBP can include the first color filter CF1, the second color filter CF2, and the third color filter CF3 sequentially stacked on the one surface of the base layer BSL. For example, the first color filter CF1 can be a blue color filter, the second color filter CF2 can be a red color filter, and the third color filter CF3 can be a green color filter, but the present disclosure is not limited thereto.

[0126] The low-refraction layer LRL can be located on the color filter layer CFL in a direction facing the first substrate 100. The low-refraction layer LRL (or referred to as a low-refractive layer) can change a path of light emitted from the optical layer OPL toward a front direction (or an image display direction of the display device DD) using a difference in refractive index in the display area DA, thus enhancing front output light brightness.

[0127] The first cap layer CPL1 can be located on the low-refractive layer LRL. The first cap layer CPL1 can be located on and cover the color filter layer CFL, thus protecting the color filter layer CFL. For example, the first cap layer CPL1 can be formed of an inorganic layer (or inorganic insulating layer) including an inorganic material.

[0128] The optical layer OPL can be located on the first cap layer CPL1 in a direction facing the first substrate 100. The optical layer OPL can include the bank BNK, the first color conversion pattern CCP1, the second color conversion pattern CCP2, and the light scattering pattern LSP.

[0129] The bank BNK can be configured to include at least one light-blocking material and / or a reflective material, and enable light emitted from each of the first color conversion pattern CCP1, the second color conversion pattern CCP2, and the light scattering pattern LSP to travel more reliably in an image display direction of the display device DD, thus enhancing light output efficiency of each sub-pixel SP. According to some embodiments, the bank BNK can prevent or reduce a light leakage defect in which light leaks between adjacent sub-pixels SP. According to some embodiments, the bank BNK can include a transparent material (or substance). The transparent material can include, for example, polyamide resin and polyimide resin, etc., but the present disclosure is not limited thereto. According to some embodiments, in order to enhance efficiency of light emitted from each sub-pixel SP, a separate reflective material layer can be provided and / or formed on the bank BNK.

[0130] The bank BNK can include a second opening OP2 that exposes a portion of the first cap layer CPL1 in each of the first sub-pixel SP1 to the third sub-pixel SP3. For example, the bank BNK can include a second opening OP2 that exposes a portion of the first cap layer CPL1 in the first sub-pixel SP1, a second opening OP2 that exposes a portion of the first cap layer CPL1 in the second sub-pixel SP2, and a second opening OP2 that exposes a portion of the first cap layer CPL1 in the third sub-pixel SP3. The second opening OP2 of the bank BNK can correspond to the emission area EMA of each sub-pixel SP. For example, in the first sub-pixel SP1, the second opening OP2 of the bank BNK can correspond to the first emission area EMA1. In the second sub-pixel SP2, the second opening OP2 of the bank BNK can correspond to the second emission area EMA2. In the third sub-pixel SP3, the second opening OP2 of the bank BNK can correspond to the third emission area EMA3.

[0131] The bank BNK can be a structure for defining a position of the first color conversion pattern CCP1, the second color conversion pattern CCP2, and the light scattering pattern LSP.

[0132] The first color conversion pattern CCP1 can be disposed in the second opening OP2 of the bank BNK of the first sub-pixel SP1 to correspond to the first light emitting element LD1. The first color conversion pattern CCP1 can include a plurality of first color conversion particles QD1 dispersed in a matrix material such as a base resin. For example, the first color conversion particles QD1 can be green quantum dots that absorb incident blue light, shift the wavelength of light according to an energy transition, and emit green light. In this case, the first sub-pixel SP1 can be a green sub-pixel. The first color conversion pattern CCP1 can be located at least in the first emission area EMA1.

[0133] The second color conversion pattern CCP2 can be disposed in the second opening OP2 of the bank BNK of the second sub-pixel SP2 to correspond to the second light emitting element LD2. The second color conversion pattern CCP2 can include a plurality of second color conversion particles QD2 dispersed in a matrix material such as a base resin. For example, the second color conversion particles QD2 can be red quantum dots that absorb incident blue light, shift the wavelength of light according to an energy transition, and emit red light. In this case, the second sub-pixel SP2 can be a red sub-pixel. The second color conversion pattern CCP2 can be located at least in the second emission area EMA2.

[0134] The light scattering pattern LSP can be disposed in the second opening OP2 of the bank BNK of the third sub-pixel SP3 to correspond to the third light emitting element LD3. The light scattering pattern LSP can include a plurality of light scattering particles SCT dispersed in a matrix material such as a base resin. The light scattering pattern LSP can include light scattering particles SCT formed of a material such as silicon dioxide, but the constituent material of the light scattering particles SCT is not limited thereto. According to some embodiments, the light scattering particles SCT can be omitted, and a light scattering pattern LSP formed of a transparent polymer can be provided. For example, the light scattering pattern LSP can transmit incident blue light in the image display direction. In this case, the third sub-pixel SP3 can be a blue sub-pixel. The light scattering pattern LSP can be located at least in the third emission area EMA3.

[0135] The second cap layer CPL2 can be located on the optical layer OPL in a direction facing the first substrate 100. The second cap layer CPL2 can be composed of an inorganic layer (or an inorganic insulating layer) including an inorganic material. For example, the second cap layer CPL2 can include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and an inorganic material such as aluminum oxide (AlO xThe second cap layer CPL2 can be disposed on the optical layer OPL to protect the optical layer OPL from external water or oxygen, etc., thus further enhancing the reliability of the optical layer OPL. The second cap layer CPL2 can be formed of at least one of a metal oxide, an organic insulating layer including an organic material, etc., but embodiments according to the present disclosure are not limited thereto. According to some embodiments, the second cap layer CPL2 can be formed of an organic insulating layer including an organic material. The second cap layer CPL2 can be disposed on the optical layer OPL to protect the optical layer OPL from external water or oxygen, etc., thus further enhancing the reliability of the optical layer OPL.

[0136] The filling layer 400 can be located in the display area DA between the first substrate 100 and the second substrate 200 having the foregoing configuration. For example, the filling layer 400 can be located between the encapsulation layer TFE of the first substrate 100 and the second cap layer CPL2 of the second substrate 200. The filling layer 400 can maintain a gap between the first substrate 100 and the second substrate 200.

[0137] Figure 6 is a schematic sectional view illustrating aspects of an emission structure EMS in one of the first to third light emitting elements LD1 to LD3 according to some embodiments. Figure 5

[0138] Referring to Figure 5 and Figure 6 , the emission structure EMS can have a series structure in which the first and second emission parts EU1 and EU2 are stacked. The emission structure EMS can have substantially the same configuration in each of the first to third light emitting elements LD1 to LD3. Figure 5

[0139] Each of the first and second emission parts EU1 and EU2 can include at least one emission layer configured to generate light in response to a current applied thereto. The first emission part EU1 can include a first emission layer EML1, a first electron transport part ETU1, and a first hole transport part HTU1. The first emission layer EML1 can be located between the first electron transport part ETU1 and the first hole transport part HTU1. The second emission part EU2 can include a second emission layer EML2, a second electron transport part ETU2, and a second hole transport part HTU2. The second emission layer EML2 can be located between the second electron transport part ETU2 and the second hole transport part HTU2.

[0140] Each of the first and second hole transport parts HTU1 and HTU2 can include at least one of a hole injection layer and a hole transport layer, and can further include a hole buffer layer and an electron blocking layer, etc., as needed. The first and second hole transport parts HTU1 and HTU2 can have the same configuration or have different configurations.

[0141] ​​Each of the first and second electron transport parts ETU1 and ETU2 can include at least one of an electron injection layer and an electron transport layer, and can further include an electron buffer layer and a hole blocking layer, etc. as necessary. The first and second electron transport parts ETU1 and ETU2 can have the same configuration or have different configurations.

[0142] The intermediate layer (or connection layer) which can be provided in the form of a charge generation layer CGL can be located between the first and second emission parts EU1 and EU2, thus connecting the first and second emission parts EU1 and EU2 to each other. Hereinafter, the charge generation layer CGL will be referred to as an intermediate layer. According to some embodiments, the intermediate layer CGL can have a stack structure including a p-dopant layer and an n-dopant layer. For example, the p-dopant layer can include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer can include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the structure (or material) of the intermediate layer CGL is not limited to the foregoing embodiments. According to some embodiments, the intermediate layer CGL can include a material having a relatively high charge conductivity (or charge mobility) compared to the first and second emission parts EU1 and EU2, thus having an electrically conductive property.

[0143] According to some embodiments, the first and second emission layers EML1 and EML2 can generate different colors of light, but are not limited thereto. In some embodiments, the first and second emission layers EML1 and EML2 can generate the same color of light.

[0144] In the foregoing embodiments, the emission structure EMS has been described as having a series structure including the first and second emission parts EU1 and EU2 stacked on each other, but the structure thereof is not limited thereto. According to some embodiments, the emission structure EMS can be constituted of a series structure including three emission parts stacked on each other.

[0145] Figures 7 to 10 is a schematic cross-sectional view taken along the line I-I’ of Figure 1 .

[0146] Figures 8 to 10 FIGS. 10A and 10B illustrate modification examples of the first dummy pattern DMP1, etc. Figure 7 .

[0147] The following description related to embodiments of the Figures 7 to 10 will focus on differences from the above-described embodiments in order to avoid redundant description.

[0148] Referring to Figure 1 and Figures 7 to 10The display device DD can include the first substrate 100 and the second substrate 200 connected to each other using the sealing member 300. The fill layer 400 can be located in the display area DA between the first substrate 100 and the second substrate 200. The fill layer 400 can extend to at least a portion of the non-display area NDA between the first substrate 100 and the second substrate 200, thus contacting the sealing member 300.

[0149] The display area DA can include a pixel area PXA. Each of the first to third sub-pixels SP1 to SP3 can be located in the pixel area PXA.

[0150] Hereinafter, the configuration of the second substrate 200 in the display area DA and the non-display area NDA will be described.

[0151] The second substrate 200 can include a base layer BSL, a color filter layer CFL, a low-refraction layer LRL, and an optical layer OPL. The base layer BSL, the color filter layer CFL, and the low-refraction layer LRL can be located in the display area DA and the non-display area NDA. The optical layer OPL can be located in the display area DA.

[0152] The base layer BSL can include a first surface SF1 and a second surface SF2 opposite to each other in the third direction DR3. The second surface SF2 can be disposed on the uppermost layer in the third direction DR3 to provide an input surface and / or a display surface to a user.

[0153] In the display area DA, the color filter layer CFL can be located on the first surface SF1 of the base layer BSL. The first cover layer CPL1 can be located on the color filter layer CFL. The optical layer OPL can be located on the first cover layer CPL1. The second cover layer CPL2 can be located on the optical layer OPL.

[0154] In the non-display area NDA, the color filter layer CFL can be located on the first surface SF1 of the base layer BSL. The color filter layer CFL can include a first color filter CF1 located directly on the first surface SF1 of the base layer BSL, a second color filter CF2 located on the first color filter CF1, and a third color filter CF3 located on the second color filter CF2. The first color filter CF1 can be a blue color filter overlapping the third emission area (refer to "EMA3" of FIG. 2) and transmitting blue light. The second color filter CF2 can be a red color filter overlapping the second emission area (refer to "EMA2" of FIG. 2) and transmitting red light. The third color filter CF3 can be a green color filter overlapping the first emission area (refer to "EMA1" of FIG. 2) and transmitting green light. Figure 5 Figure 5 Figure 5

[0155] ​​​The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be stacked on top of each other, thus forming a light blocking pattern LBP. The light blocking pattern LBP can be disposed throughout an entire area of the non-display area NDA. The light blocking pattern LBP can overlap with a non-emission area (refer to "NEA") in the display area DA (or the pixel area PXA). Figure 5

[0156] According to some embodiments, the first dummy pattern DMP1 can be located on the light blocking pattern LBP. The first dummy pattern DMP1 can be located on the light blocking pattern LBP disposed in the non-display area NDA to correspond to the sealing member 300. The first dummy pattern DMP1 can be disposed between the light blocking pattern LBP and the sealing member 300 in the non-display area NDA.

[0157] The first dummy pattern DMP1 can block penetration of oxygen or water that can be sucked from the non-display area NDA to the display area DA, thus preventing or reducing damage to elements, such as the first to third sub-pixels SP1 to SP3, located in the display area DA. The first dummy pattern DMP1 can protrude in a direction opposite to the third direction DR3 in a direction from the light blocking pattern LBP (or the third color filter CF3) toward the first substrate 100. The first dummy pattern DMP1 can have a certain height h in the direction opposite to the third direction DR3. For example, the first dummy pattern DMP1 can have a height h ranging from approximately 3 µm to approximately 8 µm. A plurality of first dummy patterns DMP1 can be provided, but the present disclosure is not limited thereto. The first dummy patterns DMP1 adjacent to each other can be arranged to be spaced apart from each other.

[0158] The first dummy pattern DMP1 can include an organic material including titanium dioxide in the form of nanoparticles, but is not limited thereto. According to some embodiments, the first dummy pattern DMP1 can include the same material as some components of the optical layer OPL. For example, the first dummy pattern DMP1 can include the same material as the light scattering pattern LSP including the light scattering particles SCT.

[0159] The low-refraction layer LRL can be located on the color filter layer CFL. The low-refraction layer LRL (or referred to as a low-refractive layer) can change a path of light emitted from the optical layer OPL toward a front direction (or an image display direction of the display device DD) using a difference in refractive index in the display area DA, thus enhancing front output light brightness. The low-refraction layer LRL can reuse light (e.g., blue-based light) that does not react with the first and second color conversion patterns CCP1 and CCP2, enabling light to react with the first and second color conversion patterns CCP1 and CCP2, by which output light brightness of the first and second color conversion patterns CCP1 and CCP2 can be increased. ​

[0160] The low-refraction layer LRL can include a resin and hollow particles distributed in the resin and have a refractive index in the range of 1.1 to 1.3, but embodiments according to the present disclosure are not limited thereto. Here, the hollow particles can refer to particles each having a form in which a space exists in a surface and / or an interior of an organic or inorganic particle. The hollow particles can be hollow silica particles.

[0161] A portion of the low-refraction layer LRL can be separated from another portion thereof in the non-display area NDA by the first dummy pattern DMP1. In other words, the low-refraction layer LRL can include an interrupted portion (or an open portion) separated by the first dummy pattern DMP1. The interrupted portion can be defined as a portion of the low-refraction layer LRL that is broken from the other portion thereof due to the first dummy pattern DMP1, rather than continuously formed in the non-display area NDA on the sealing member 300. The low-refraction layer LRL can have a thickness in the range of 1 µm to 2 µm (or approximately 1 µm to approximately 2 µm) in the third direction DR3. The low-refraction layer LRL can be formed on the light-blocking pattern LBP in the non-display area NDA by a known coating method or the like.

[0162] Since the low-refraction layer LRL is coated on the first dummy pattern DMP1 having a height h greater (or thicker) than a thickness of the low-refraction layer LRL, the low-refraction layer LRL is not continuously formed in the shape of the first dummy pattern DMP1 and can have a separated interrupted portion. For example, the low-refraction layer LRL can be formed on the light-blocking pattern LBP in a direction facing the first substrate 100 between the first dummy patterns DMP1 adjacent to each other and can not be formed on one surface (e.g., a lower surface facing the sealing member 300) of each of the first dummy patterns DMP1. However, the present disclosure is not limited to the foregoing example. According to some embodiments, as illustrated in FIG. 4B, the low-refraction layer LRL can also be formed on the one surface of the first dummy pattern DMP1. For example, depending on the height of the first dummy pattern DMP1, the low-refraction layer LRL can also be formed on the one surface of the first dummy pattern DMP1. In this case, the first dummy pattern DMP1 can have a height h in the range of approximately 3 µm to approximately 6 µm. Figure 8

[0163] ​The low-refractive layer LRL formed of an organic layer (or an organic insulating layer) has an advantage in flexibility and elasticity, but can be vulnerable to penetration of water or oxygen compared to an inorganic layer (or an inorganic insulating layer). Accordingly, the first dummy pattern DMP1 is formed so that the low-refractive layer LRL can have an interrupted structure in the non-display area NDA in which the sealing member 300 is disposed, thus preventing or reducing contaminants such as external oxygen and water, etc. that can be absorbed into the display area DA from the outside of the sealing member 300 through the low-refractive layer LRL, thereby relatively improving the reliability of the first to third sub-pixels SP1 to SP3.

[0164] The first cap layer CPL1 can be located on the color filter layer CFL, the first dummy pattern DMP1, and the low-refractive layer LRL in a direction facing the first substrate 100 (i.e., a direction toward the sealing member 300). The first cap layer CPL1 can be formed of an inorganic insulating layer including an inorganic material. The second dummy pattern DMP2 can be formed on the first cap layer CPL1 on the first dummy pattern DMP1.

[0165] The second dummy pattern DMP2 can cover at least a portion of the first dummy pattern DMP1, and the first cap layer CPL1 is interposed therebetween. According to some embodiments, the second dummy pattern DMP2 can be formed of an organic layer (organic insulating layer). For example, the second dummy pattern DMP2 can include the same material as the bank BNK. In this case, the second dummy pattern DMP2 can be formed in the same process as the bank BNK and include the same material as the bank BNK, and can be provided in the same layer as the bank BNK, but is not limited thereto. Each of the second dummy pattern DMP2 and the bank BNK can have, for example, a thickness of approximately 10 µm, but is not limited thereto.

[0166] The second dummy pattern DMP2 can cover the first dummy pattern DMP1 in a direction facing the first substrate 100, thus having a flat surface that mitigates a stepped portion caused by the first dummy pattern DMP1.

[0167] According to some embodiments, the second dummy pattern DMP2 can be formed on the first cap layer CPL1 to correspond to the sealing member 300, thus functioning as a shock absorber for mitigating a force applied to the sealing member 300 during a process of bonding (or coupling) the first substrate 100 and the second substrate 200 to each other.

[0168] The second cover layer CPL2 can be located on the second dummy pattern DMP2, the first cover layer CPL1, and the bank BNK in a direction facing the first substrate 100 (i.e., a direction toward the sealing part 300). The second cover layer CPL2 can be composed of an inorganic layer (or an inorganic insulating layer) including an inorganic material. The second cover layer CPL2 can completely cover the second dummy pattern DMP2, thus preventing or reducing the second dummy pattern DMP2 from being exposed to the outside. Accordingly, by blocking a path through which oxygen or water, etc. is introduced along the second dummy pattern DMP2 in the non-display area NDA, it is possible to further enhance the reliability of the first to third sub-pixels SP1 to SP3 in the display area DA.

[0169] According to some embodiments, as illustrated in FIG. 1A, the non-display area NDA can include a dummy pixel area DPXA in which dummy pixels are located. Dummy pixels having substantially the same or similar structures as the first to third sub-pixels SP1 to SP3 can be located in the dummy pixel area DPXA. The dummy pixels can be provided in an isolated shape in the dummy pixel area DPXA. The dummy pixels can be provided in the dummy pixel area DPXA (or the non-display area NDA) in order to prevent or reduce defects due to deviation caused during a manufacturing process, and can be selectively provided depending on embodiments. The base layer BSL can include the dummy pixel area DPXA adjacent to the display area DA and corresponding to at least one area of the non-display area NDA. Figure 9

[0170] In the dummy pixel area DPXA of the second substrate 200, a light-blocking pattern LBP and an optical layer OPL located on the light-blocking pattern LBP can be disposed.

[0171] The optical layer OPL can include the bank BNK and a light-scattering pattern LSP disposed between adjacent banks BNK. The bank BNK can be the same as the bank BNK disposed in the display area DA. The light-scattering pattern LSP can be the same as the light-scattering pattern LSP disposed in the display area DA. The light-scattering pattern LSP can include light-scattering particles SCT.

[0172] According to some embodiments, the first dummy pattern DMP1 can be formed by the same process as one component of the optical layer OPL disposed in the display area DA. For example, as illustrated in FIG. 1A, the first dummy pattern DMP1 can be formed by the same process as the light-blocking pattern LBP disposed in the display area DA. Figure 10 ​As illustrated in the middle, the first dummy pattern DMP1 can be formed by the same process as a light scattering pattern LSP disposed in the third sub-pixel SP3 in the optical layer OPL. For example, the first dummy pattern DMP1 and the light scattering pattern LSP can be formed simultaneously or concurrently by a photolithography process using a mask. In this case, the first dummy pattern DMP1 and the light scattering pattern LSP can include the same material. For example, the first dummy pattern DMP1 and the light scattering pattern LSP can include a plurality of light scattering particles SCT dispersed in a certain matrix material such as a base resin. Here, the light scattering pattern LSP disposed in the display area DA can be located on the first color filter CF1 to correspond to the third emission area EMA3 surrounded by the light blocking pattern LBP in the third sub-pixel SP3. In the third sub-pixel SP3, the bank BNK can be located on the light scattering pattern LSP and the light blocking pattern LBP, and the low-refraction layer LRL is interposed therebetween. According to another embodiment, the first dummy pattern DMP1 can be in a layer different from the light scattering pattern LSP.

[0173] According to some embodiments, the first dummy pattern DMP1 can be located on the sealing member 300 in the non-display area NDA between the first substrate 100 and the second substrate 200. The first dummy pattern DMP1 can separate (or disconnect) a portion of the low-refraction layer LRL from another portion thereof in the non-display area NDA, thus forming a discontinuous portion of the low-refraction layer LRL. Dividing the low-refraction layer LRL in the non-display area NDA into a plurality of portions can reduce or block external oxygen or water, etc. from being absorbed from the non-display area NDA into the display area DA through the low-refraction layer LRL. Accordingly, the reliability of the display device DD (or the first to third sub-pixels SP1 to SP3) can be relatively improved.

[0174] According to some embodiments, in the non-display area NDA of the second substrate 200 with respect to a direction facing the first substrate 100, the first cap layer CPL1 including an inorganic material, the second dummy pattern DMP2 including an organic material and located on the first cap layer CPL1, and the second cap layer CPL2 including an inorganic material and located on the second dummy pattern DMP2 can serve as the same encapsulation member as the encapsulation layer TFE of the first substrate 100. Due to the encapsulation member, external oxygen or water, etc. can be reduced or prevented from being absorbed into the display area DA, whereby the reliability of the display device DD can be further relatively improved.

[0175] Hereinafter, a method of manufacturing the second substrate 200 according to some embodiments will be described in more detail. Figures 11 to 19 A method of manufacturing the second substrate 200 according to some embodiments will be described in more detail.

[0176] Figures 11 to 19 is a schematic cross-sectional view illustrating a method of forming Figure 7 the second substrate 200.

[0177] In the embodiments illustrated and described in relation to Figures 11 to 19 In the embodiments illustrated and described in relation to

[0178] With reference to Figures 11 to 19 the description will focus on the differences with the above-described embodiments, in order to avoid redundant descriptions. Moreover, in Figures 11 to 19 , the direction along which the second surface SF2 of the base layer BSL is disposed at the lower portion and the first surface SF1 of the base layer BSL is disposed at the upper portion is defined as the fourth direction DR4.

[0179] With reference to Figure 7 and Figure 11 , a first color filter CF1 is formed on the first surface SF1 of the base layer BSL. The first color filter CF1 can be a blue color filter.

[0180] The first color filter CF1 can be formed on the entire area of the first surface SF1 of the base layer BSL in the non-display area NDA. The first color filter CF1 can be formed on the first surface SF1 of the base layer BSL so as to correspond to the non-emission area (cf. “NEA” of Figure 5 ) and the third emission area (cf. “EMA3” of Figure 5 ) in the display area DA.

[0181] With reference to Figure 7 , Figure 11 and Figure 12 , a second color filter CF2 is formed on the first color filter CF1. The second color filter CF2 can be a red color filter.

[0182] The second color filter CF2 can be formed on the entire surface of the first color filter CF1 in the non-display area NDA. The second color filter CF2 can be formed on the first color filter CF1 of the non-emission area NEA in the display area DA. Moreover, the second color filter CF2 can be formed on the first surface SF1 of the base layer BSL so as to correspond to the second emission area (cf. “EMA2” of Figure 5 ) in the display area DA.

[0183] With reference to Figure 7 and Figures 11 to 13 , a third color filter CF3 is formed on the second color filter CF2. The third color filter CF3 can be a green color filter.

[0184] The third color filter CF3 can be formed on the entire surface of the second color filter CF2 in the non-display area NDA. The third color filter CF3 can be formed on the second color filter CF2 of the non-emission area NEA in the display area DA. Further, the third color filter CF3 can be formed on the first surface SF1 of the base layer BSL to correspond to the first emission area (refer to "EMA1") in the display area DA. Figure 5

[0185] The first color filter CF1, the second color filter CF2, and the third color filter CF3 arranged to overlap each other in the non-display area NDA and the non-emission area NEA can function as a light-blocking pattern LBP. The first color filter CF1, the second color filter CF2, the third color filter CF3, and the light-blocking pattern LBP can constitute a color filter layer CFL.

[0186] Referring to Figure 7 and Figures 11 to 14 The first dummy pattern DMP1 is formed on the light-blocking pattern LBP in the non-display area NDA. The first dummy patterns DMP1 adjacent to each other can be arranged to be spaced apart from each other. The first dummy pattern DMP1 can be formed by a photolithography process using a mask. The first dummy pattern DMP1 can be constituted of an organic layer (or an organic insulating layer) including an organic material including titanium dioxide in the form of nanoparticles. The first dummy pattern DMP1 can have a shape protruding in the fourth direction DR4. In other words, the first dummy pattern DMP1 can have a shape protruding from the light-blocking pattern LBP in a direction toward the sealing member 300.

[0187] Referring to Figure 7 and Figures 11 to 15 The low-refraction layer LRL is formed on the light-blocking pattern LBP and the color filter layer CFL. For example, the low-refraction layer LRL can be formed by a curing process or the like after being coated on the light-blocking pattern LBP and the color filter layer CFL by an inkjet printing or a spin coating method or the like.

[0188] In the non-display area NDA, the low-refraction layer LRL can include discontinuous portions separated from each other by the first dummy pattern DMP1. Because the coating thickness of the low-refraction layer LRL is sufficiently small (or thin) with respect to the height of the first dummy pattern DMP1, the low-refraction layer LRL can be interrupted by the first dummy pattern DMP1 in the non-display area NDA. In the non-display area NDA, the low-refraction layer LRL can be formed on the light-blocking pattern LBP between the first dummy patterns DMP1 adjacent to each other.

[0189] Referring to Figure 7 and Figures 11 to 16 ​A first cap layer CPL1 is formed on the low-refractive layer LRL and the first dummy pattern DMP1 by a chemical vapor deposition method or the like. The first cap layer CPL1 can be composed of an inorganic layer (or inorganic insulating layer) including an inorganic material. For example, the first cap layer CPL1 can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). However, the material of the first cap layer CPL1 is not limited to the foregoing embodiments.

[0190] Referring to Figure 7 and Figures 11 to 17 , a bank BNK and a second dummy pattern DMP2 are simultaneously or concurrently or sequentially formed on the first cap layer CPL1. The bank BNK and the second dummy pattern DMP2 can have the same material and can be provided in the same layer. The bank BNK and the second dummy pattern DMP2 can have a flat upper surface with respect to the fourth direction DR4.

[0191] The bank BNK can be patterned to include a plurality of second openings OP2 in the display area DA. The second dummy pattern DMP2 can be partially located on the first cap layer CPL1 to correspond to the first dummy pattern DMP1. The second dummy pattern DMP2 can be provided in a shape in which a stepped portion STP of the first cap layer CPL1 disposed on the low-refractive layer LRL between adjacent first dummy patterns DMP1 is filled with the second dummy pattern DMP2, but the disclosure is not limited thereto.

[0192] Referring to Figure 7 and Figures 11 to 18 , a first color conversion pattern CCP1 is formed in at least one of the second openings OP2 of the bank BNK. A second color conversion pattern CCP2 is formed in another of the second openings OP2. A light scattering pattern LSP is formed in still another of the second openings OP2.

[0193] For example, the first color conversion pattern CCP1 is formed in the corresponding second opening OP2 of the bank BNK by an inkjet printing method or the like. After the first color conversion pattern CCP1 is formed, the second color conversion pattern CCP2 is formed in the corresponding second opening OP2 of the bank BNK by an inkjet printing method or the like. After the second color conversion pattern CCP2 is formed, the light scattering pattern LSP is formed in the corresponding second opening OP2 of the bank BNK by an inkjet printing method or by a photolithography process using a mask. Here, the order of manufacturing the first color conversion pattern CCP1, the second color conversion pattern CCP2, and the light scattering pattern LSP is not limited to the foregoing embodiment. According to some embodiments, the light scattering pattern LSP can be formed first, the formation of the light scattering pattern LSP is followed by the formation of the first color conversion pattern CCP1, and thereafter, the second color conversion pattern CCP2 can be formed after the formation of the first color conversion pattern CCP1.

[0194] Referring to Figure 7 and Figures 11 to 19 The second cap layer CPL2 can be formed throughout the display area DA and the non-display area NDA by a chemical vapor deposition method or the like. The second cap layer CPL2 can be formed on the first cap layer CPL1 and the second dummy pattern DMP2 in the non-display area NDA. Further, the second cap layer CPL2 can be formed on the bank BNK, the first color conversion pattern CCP1, and the second color conversion pattern CCP2, and the light scattering pattern LSP in the display area DA.

[0195] The second cap layer CPL2 can be an inorganic layer (or an inorganic insulating layer) including an inorganic material. For example, the second cap layer CPL2 can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). However, the material of the second cap layer CPL2 is not limited to the foregoing embodiment.

[0196] The first substrate 100 including the display element layer DPL can be formed. The second substrate 200 facing the first substrate 100 can be formed. The second substrate 200 having the foregoing configuration can be coupled to the first substrate 100 using a sealing member (refer to "300" of Figure 7 ). Here, a filling layer (refer to "400" of Figure 7 ) can be formed in the display area DA between the first substrate 100 and the second substrate 200.

[0197] According to some embodiments, the structure (or the first dummy pattern) can be located on a sealing member between the first substrate (or lower substrate) and the second substrate (or upper substrate), thereby interrupting the low-refractive layer in the non-display area. Therefore, the absorption of external water or oxygen from the non-display area into the display area through the low-refractive layer can be reduced or prevented. As a result, a display device with relatively improved reliability and a method for manufacturing the display device can be provided.

[0198] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein.

[0199] Although some aspects of embodiments of this disclosure have been described above, those skilled in the art will understand that various modifications, additions and substitutions are possible without departing from the spirit and scope of the embodiments according to this disclosure.

[0200] Therefore, the embodiments disclosed in this specification are for illustrative purposes only and are not intended to limit the technical spirit of this disclosure. The scope of the embodiments according to this disclosure is defined by the claims and their equivalents.

Claims

1. A display device, comprising: The first substrate includes a display element layer; The second substrate faces the first substrate; as well as A sealing component is located between the first substrate and the second substrate. The second substrate includes: The base layer includes a display area that overlaps with the display element layer and a non-display area that surrounds the display area; A light-blocking pattern is present in the non-display area of ​​the substrate layer; A first dummy pattern is located in the non-display area between the light-blocking pattern and the sealing component; A low-refractive-index layer, located in both the non-display area and the display area, and interrupted by the first dummy pattern; and A second dummy pattern covers the first dummy pattern in the non-display area.

2. The display device according to claim 1, wherein, The first dummy pattern includes organic materials.

3. The display device according to claim 1, wherein, The first dummy pattern has a shape that protrudes from the light-blocking pattern in the direction toward the sealing member.

4. The display device according to claim 1, wherein, The first dummy pattern includes multiple first dummy patterns.

5. The display device according to claim 4, wherein, The low-refractive layer is located in the non-display area between the plurality of adjacent first dummy patterns.

6. The display device according to claim 1, wherein, The second substrate further includes: A dam, located in the display area, and comprising a plurality of openings therein; and A color conversion pattern in at least one of the plurality of openings and a light scattering pattern in another of the plurality of openings. The second dummy pattern is made of the same material as the embankment.

7. The display device according to claim 6, wherein, The first dummy pattern and the light scattering pattern use the same material.

8. The display device according to claim 6, wherein, The first dummy pattern is in a layer different from the light scattering pattern.

9. The display device according to claim 6, wherein, The second substrate further includes: A first capping layer, in the direction toward the sealing member, is on the first dummy pattern and the low-refractive layer; and The second cover layer is on the second dummy pattern, the first cover layer, and the embankment in the direction toward the sealing member.

10. The display device according to any one of claims 1 to 9, in, The second substrate further includes a color filter layer in the display area and the non-display area, and between the low-refractive layer and the substrate layer. The color filter layer includes a first color filter, a second color filter, and a third color filter. In the non-display area, the first color filter, the second color filter, and the third color filter are stacked on top of each other to form the light-blocking pattern.

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