Board card automatic calibration testing device and testing machine

Abstract

The utility model relates to a board card automatic calibration testing device and a testing machine, the board card automatic calibration testing device comprises a change-over switch module, an interconnection interface module, a peripheral interface module and a communication unit, the change-over switch module is connected with the interconnection interface module, the peripheral interface module and the communication unit, the interconnection interface module is connected with a board card, and the communication unit is connected with the board card. The peripheral interface module is connected with a peripheral calibration instrument, and the communication unit communicates with an upper computer; the communication unit receives a control instruction issued by an upper computer and transmits the control instruction to the change-over switch module, and the change-over switch module carries out on-off switching of a switch according to the control instruction, so that the peripheral calibration instrument is connected with a corresponding channel of the board card, the board card is calibrated through the peripheral calibration instrument, automatic calibration is achieved, manual channel switching for one-by-one calibration is not needed, and the calibration efficiency is improved. And the calibration efficiency and accuracy are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, in particular to a board card automatic calibration testing device and a testing machine. BACKGROUND

[0002] Semiconductor automatic testing refers to detecting various parameter indexes of a device under test (DUT) by using an automatic test equipment (ATE) to eliminate defective products and control the quality of semiconductor devices before testing the device under test. Before testing the device under test, the related function board card of the automatic test equipment needs to be calibrated and checked to ensure the testing accuracy. The traditional testing machine board card performance testing method mainly manually switches each channel for one-by-one calibration, which has the disadvantage of low calibration efficiency. CONTENT OF THE UTILITY MODEL

[0003] Therefore, it is necessary to provide a board card automatic calibration testing device and a testing machine which can improve the calibration efficiency in view of the above problems.

[0004] The first aspect of the present application provides a board card automatic calibration testing device, which comprises a switching switch module, an interconnection interface module, a peripheral interface module and a communication unit, the switching switch module is connected with the interconnection interface module, the peripheral interface module and the communication unit, the interconnection interface module is connected with a board card, the peripheral interface module is connected with a peripheral calibration instrument, and the communication unit communicates with an upper computer;

[0005] The communication unit receives a control instruction issued by the upper computer and transmits the control instruction to the switching switch module, the switching switch module switches on and off according to the control instruction, so that the peripheral calibration instrument is connected with a corresponding channel of the board card, so as to calibrate the board card by using the peripheral calibration instrument.

[0006] In one embodiment, the switching switch module comprises:

[0007] An AWG switch array is connected with the interconnection interface module, the peripheral interface module and the communication unit, switches on and off according to the control instruction, and connects the peripheral calibration instrument with a corresponding channel of an AWG in the board card.

[0008] A DGT switch array is connected with the interconnection interface module, the peripheral interface module and the communication unit, switches on and off according to the control instruction, and connects the peripheral calibration instrument with a corresponding channel of a DGT in the board card.

[0009] In one of the embodiments, the AWG switch array comprises a first balance converter and two or more switching switches, each of the switching switches being connected between the interconnection interface module and the peripheral interface module in sequence, and the first balance converter being connected between the switching switches in sequence.

[0010] The first balance converter converts the differential signal output by the corresponding channel of the AWG and sent through the interconnection interface module and the corresponding switching switch into a single-ended signal, and then sends the single-ended signal to the peripheral interface module through the corresponding switching switch.

[0011] In one of the embodiments, the DGT switch array comprises a second balance converter and two or more switching switches, each of the switching switches being connected between the interconnection interface module and the peripheral interface module in sequence, and the second balance converter being connected between the switching switches in sequence.

[0012] The second balance converter converts the single-ended signal sent through the peripheral interface module and the corresponding switching switch into a differential signal, and then sends the differential signal to the corresponding channel of the DGT through the corresponding switching switch and the interconnection interface module.

[0013] In one of the embodiments, the switching switch comprises a relay double-parallel single-pole double-throw switch and / or a relay single-pole double-throw switch.

[0014] In one of the embodiments, the interconnection interface module and / or the peripheral interface module comprises an SMA radio frequency connector.

[0015] The second aspect of the application provides a test machine, comprising a board card, a peripheral calibration instrument, and the board card automatic calibration test device.

[0016] In one of the embodiments, the peripheral calibration instrument comprises at least one of a baseband signal analyzer, a power meter, a spectrum analyzer, and a vector signal generator.

[0017] In one of the embodiments, the test machine further comprises a host computer, the host computer being connected to the communication unit in the board card and the board card automatic calibration test device, and issuing a control instruction to the communication unit according to the relevant information of the board card.

[0018] In one of the embodiments, the board card is a digital-analog hybrid board card, and the board card automatic calibration test device performs at least one of power calibration test, IQ signal test, single-ended dynamic performance test, and differential dynamic performance test on the digital-analog hybrid board card.

[0019] The communication unit receives the control instruction issued by the upper computer and transmits it to the switch module, the switch module switches on and off according to the control instruction, connects the peripheral calibration instrument with the corresponding channel of the board card, so as to calibrate the board card by the peripheral calibration instrument, realizes automatic calibration, and improves the calibration efficiency and accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The structure block diagram of the board card automatic calibration test device in one embodiment is shown in the figure.

[0021] Figure 2 The structure schematic diagram of the relay double-parallel single-pole double-throw switch and the relay single-pole double-throw switch in one embodiment is shown in the figure.

[0022] Figure 3 The structure schematic diagram of the board card automatic calibration test device in one embodiment is shown in the figure.

[0023] Figure 4 The structure schematic diagram of the board card automatic calibration test device in another embodiment is shown in the figure.

[0024] Figure 5 The structure schematic diagram of the board card automatic calibration test device in another embodiment is shown in the figure.

[0025] Figure 6 The structure schematic diagram of the test machine in one embodiment is shown in the figure. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0028] It can be understood that, in the following embodiments, if the circuits, modules, units, etc. connected to each other have the transmission of electrical signals or data between each other, it should be understood as "electrically connected", "communicatively connected" and the like.

[0029] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, or combinations thereof.

[0030] In one embodiment, as shown in FIG. 1, a board card automatic calibration test device is provided, which includes a switch module, an interconnection interface module 120, a peripheral interface module 130 and a communication unit 140. The switch module is connected to the interconnection interface module 120, the peripheral interface module 130 and the communication unit 140. The interconnection interface module 120 is connected to a board card FE. The peripheral interface module 130 is connected to a peripheral calibration instrument 210. The communication unit 140 communicates with a host computer. The communication unit 140 receives a control instruction issued by the host computer and transmits it to the switch module. The switch module switches on and off according to the control instruction, so that the peripheral calibration instrument 210 is connected to the corresponding channel of the board card FE, so as to calibrate the board card FE by the peripheral calibration instrument 210. Figure 1

[0031] The board card FE can be a digital-analog hybrid board card of a test machine. The board card automatic calibration test device can be provided with communication, clock and power supply by the test machine, so as to calibrate and test the digital-analog hybrid board card. The digital-analog hybrid board card includes an AWG (arbitrary waveform generator) and a DGT (signal collector). The AWG is an excitation source of the entire digital test machine, which can generate various modes of analog excitation signals as a signal source of the measured chip. The DGT is a signal analysis module of the entire digital test machine, which can analyze data of various analog signal indicators and analyze and detect the output signal of the measured chip. The AWG as a transmitting link has 16 channels, which can be divided into 8 pairs of differential channels and 4 pairs of IQ (quadrature modulation) channels, and is generally composed of operational amplifiers, relays, filters and DACs. The DGT as a receiving link has 16 channels, which can be divided into 8 pairs of differential channels and 4 pairs of IQ channels, and is generally composed of operational amplifiers, relays, filters and ADCs. A plurality of controlled switches (relays, MOS tubes, etc.) can be used in the switch module to change the internal connection relationship by switching on and off according to the control instruction. The specific type of the peripheral calibration instrument 210 is not unique, which can include a baseband signal analyzer, a power meter, a spectrum analyzer, a vector signal generator, etc. The baseband signal analyzer is used to test the IQ signal. The power meter is used for power calibration of the board card FE. The spectrum analyzer is used to test the AWG performance of the board card FE. The vector signal generator is used to test the DGT performance of the board card FE. ​

[0032] Correspondingly, the switching module can include an AWG switch array 112 and a DGT switch array 114. The AWG switch array 112 is connected to the interconnection interface module 120, the peripheral interface module 130 and the communication unit 140, and switches on and off according to the control instruction, so that the peripheral calibration instrument 210 is connected to the corresponding channel of the AWG in the board card FE. The DGT switch array 114 is connected to the interconnection interface module 120, the peripheral interface module 130 and the communication unit 140, and switches on and off according to the control instruction, so that the peripheral calibration instrument 210 is connected to the corresponding channel of the DGT in the board card FE.

[0033] The AWG switch array 112 is mainly used to complete the automatic calibration and testing of the AWG part in the board card FE of the digital tester. The DGT switch array 114 is mainly used to complete the automatic calibration and testing of the DGT part in the board card FE of the digital tester. The interconnection interface module 120 can specifically include an SMA radio frequency connector, which is used for communication between the 32 channels (16 channels of AWG and 16 channels of DGT) on the board card FE side and the corresponding attribute interface of the board card automatic calibration and testing device. The peripheral interface module 130 can also include an SMA radio frequency connector, which is mainly used to connect the peripheral calibration instrument 210 required for testing (each instrument device has its own exclusive corresponding interface). Specifically, the 32 channels of the board card FE are connected to the corresponding 32 FE_SMA radio frequency connectors in the interconnection interface module 120 through cable lines, and the peripheral calibration instrument 210 used for testing is connected to the corresponding 13 Device_SMA radio frequency connectors on the peripheral interface module 130 through cable lines. The communication between the FE_SMA radio frequency connector and the Device_SMA radio frequency connector is realized by controlling the corresponding switch array. The communication unit 140 is connected to the AWG switch array 112 and the DGT switch array 114, and is mainly used for communication between the board card automatic calibration and testing device and the tester.

[0034] In one embodiment, the AWG switch array 112 can include a first balanced converter and two or more switching switches. Each switching switch connected in sequence is connected between the interconnection interface module 120 and the peripheral interface module 130, and the first balanced converter is connected in series between the switching switches. The first balanced converter outputs the corresponding channel of the AWG, and after converting the differential signal input through the interconnection interface module 120 and the corresponding switching switch into a single-ended signal, the single-ended signal is transmitted to the peripheral interface module 130 through the corresponding switching switch. In this embodiment, the switching switch can be a relay double-parallel single-pole double-throw switch or a relay single-pole double-throw switch. Figure 2As shown, the relay double-parallel single-pole double-throw switch is two parallel relay single-pole double-throw switches, one of which has a static contact port C1 and a moving contact port S1 and S2, and the other has a static contact port C2 and a moving contact port S1 and S2. When a single relay single-pole double-throw switch is used as a switching switch, the static contact port is C1 and the moving contact port is S1 and S2. The static contact port and the moving contact port of each relay single-pole double-throw switch are connected in sequence and connected between the interconnection interface module 120 and the peripheral interface module 130, and the control end of each single-pole double-throw switch is connected to the upper computer through the communication unit 140, and according to the received control instruction, the switch is switched to the moving contact port S1 or S2. For the sake of description, the switching state of the switch can be represented by the switch name in the following text, for example, K2_s1c1, that is, the port S1 and the port C1 of the relay single-pole double-throw switch K2 are connected.

[0035] It should be noted that whether the switching switch uses a relay double-parallel single-pole double-throw switch or a relay single-pole double-throw switch, the static contact port can be connected in sequence in the direction close to the interconnection interface module 120, and the moving contact port can be connected in sequence in the direction close to the peripheral interface module 130, or the moving contact port can be connected in sequence in the direction close to the interconnection interface module 120, and the static contact port can be connected in sequence in the direction close to the peripheral interface module 130, or both connection methods can be used.

[0036] As shown in Figure 3 As shown in FIG. 6, the AWG switch array 112 includes switching switches K1-K18 and switching switches K36 and K37. Switching switches K1-K13 and switching switches K36 and K37 are relay double-parallel single-pole double-throw switches, and switching switches K14-K18 are relay single-pole double-throw switches. The AWG switch array 112 includes a first balance converter U1 and can also include a first wave trap group U2, both of which are connected in series between the switching switches. The first balance converter can specifically use a balun converter to convert the input differential signal into a single-ended signal and output, and the first balance converter U1 can be used as a combiner. The peripheral interface module 130 includes interfaces J1-J7, all of which use Device_SMA radio frequency connectors. Interfaces J1, J2, J6 and J7 are used to connect a baseband signal analyzer, interface J3 is used to connect a spectrum analyzer, interface J4 is used to connect a power meter, and interface J5 is used as a reserved peripheral interface, such as connecting a PMU (electric parameter measurement unit) or other instruments. It can be understood that PMU testing of each channel can be completed by controlling the switching switches of the AWG switch array 112.

[0037] In particular, the moving contact ports of the switching switches K1-K4 are connected to the corresponding channels of the AWG through the interface in the interconnection interface module 120 respectively, the static contact ports of the switching switches K1 and K2 are connected to the corresponding moving contact ports of the switching switch K5, the static contact ports of the switching switch K5 are connected to the corresponding static contact ports of the switching switch K7, the static contact ports of the switching switches K3 and K4 are connected to the corresponding moving contact ports of the switching switch K6, the static contact ports of the switching switch K6 are connected to the corresponding static contact ports of the switching switch K8. The moving contact ports of the switching switch K7 are connected to the corresponding static contact ports of the switching switch K9 and the corresponding moving contact ports of the switching switch K12 respectively, the moving contact ports of the switching switch K8 are connected to the corresponding static contact ports of the switching switch K10 and the corresponding moving contact ports of the switching switch K12 respectively, the moving contact ports of the switching switch K9 are connected to the static contact port of the switching switch K36 and the moving contact port of the switching switch K11 respectively, the moving contact ports of the switching switch K36 are connected to the interfaces J1 and J2, the moving contact ports of the switching switch K10 are connected to the moving contact port of the switching switch K11 and the static contact port of the switching switch K37 respectively, the moving contact ports of the switching switch K37 are connected to the interfaces J6 and J7.

[0038] The static contact port of the switching switch K11 is connected to the input of the first balance converter U1, the output of the first balance converter U1 is connected to the corresponding moving contact port of the switching switch K13, and the static contact port of the switching switch K12 is connected to the corresponding moving contact port of the switching switch K13. The static contact port of the switching switch K13 is connected to the moving contact port of the switching switch K14, the moving contact port of the switching switch K14 is connected to the static contact port of the switching switch K15, one moving contact port of the switching switch K15 is connected to one moving contact port of the switching switch K16 through the first wave trap group U2, the other moving contact port of the switching switch K15 is directly connected to the other moving contact port of the switching switch K16, the static contact port of the switching switch K16 is connected to the static contact port of the switching switch K17, one moving contact port of the switching switch K17 is connected to the interface J3, the other moving contact port is connected to the static contact port of the switching switch K18, one moving contact port of the switching switch K18 is connected to the interface J4, and the other moving contact port is connected to the interface J5.

[0039] In particular, the power calibration test, the IQ signal test, the single-ended dynamic performance test and the differential dynamic performance test of each channel of the AWG can be performed through the AWG switch array 112 respectively, and it should be noted that (1) when only the differential dynamic performance test is performed, the first balance converter U1 is passed through; (2) when the single-ended dynamic performance test and the differential dynamic performance test are performed, the first wave trap group U2 is passed through, and the specific calibration test process is as follows:

[0040] (1) AWG power calibration

[0041] For channel AWG_P0, by switching switch K2, K5, K7, K12, K13, K14, K15, K16, K17, K18, connected to interface J4 and power meter, through the power meter can complete the power calibration test of the channel. The specific switch control and signal flow direction are as follows:

[0042] AWG_P0->K2_s1c1->K5_s1c2->K7_s2c1->K12_s2c1->K13_s1c2->K14_s2c1->K15_s1c1->K16_s2c1->K17_s1c1->K18_s2c1->J4->power meter, complete the power calibration test of AWG_P0 channel.

[0043] For channel AWG_P2, the specific switch control and signal flow direction are as follows: AWG_P2->K2_s2c1->K5_s1c2->K7_s2c1->K12_s2c1->K13_s1c2->K14_s2c1->K15_s1c2->K16_s2c1->K17_s1c1->K18_s2c1->J4->power meter, complete the power calibration test of AWG_P2 channel.

[0044] AWG_P4->K2_s1c2->K5_s2c2->K7_s2c1->K12_s2c1->K13_s1c2->K14_s2c1->K15_s1c2->K16_s2c1->K17_s1c1->K18_s2c1->J4->power meter, complete the power calibration test of AWG_P4 channel.

[0045] AWG_P6->K2_s2c2->K5_s2c2->K7_s2c1->K12_s2c1->K13_s1c2->K14_s2c1->K15_s1c2->K16_s2c1->K17_s1c1->K18_s2c1->J4->power meter, complete the power calibration test of AWG_P6 channel.

[0046] In turn, AWG_P1, AWG_P3, AWG_P5, AWG_P7; AWG_N1, AWG_N3, AWG_N5, AWG_N7; AWG_N0, AWG_N2, AWG_N4, AWG_N6, a total of 16 channels can be completed respectively. Note that the power calibration test only passes through the switching switch, and does not pass through the first balance converter U1 and the first wave filter group U2. The specific switch control and signal flow direction can be obtained by Figure 3 andFigure 2 The distribution of the switches is obtained without any doubt, and will not be elaborated here.

[0047] The above completes the automated power calibration test for all AWG channels. Then, it loops back to the DGT on the FE board via the DGT switch array 114 to perform the DGT power calibration test. Finally, the automated power calibration test for all channels is completed.

[0048] (2) AWG IQ signal test

[0049] Channels AWG_P0, AWG_P2, AWG_P4, and AWG_P6 are assigned to switch K2, and then connected to interface J2 via switches K5, K7, K9, and K36, which in turn connects to the baseband signal analyzer. This link serves as the AWG_I+ path to the baseband signal analyzer's receiving channel DGT_I+, and can be used to test modulated signals such as ACLR and EVM. The baseband signal analyzer consists of a transmitting section (AWG) and a receiving section (DGT). The transmitting section (AWG) has four channels: AWG_I+, AWG_I-, AWG_Q+, and AWG_Q-; the receiving section (DGT) has four channels: DGT_I+, DGT_I-, DGT_Q+, and DGT_Q-. The transmitting AWG_I+ of the test board FE corresponds to the receiving channel DGT_I+ of the baseband signal analyzer. Specific switch control and signal flow can be determined by... Figure 3 and Figure 2 The distribution of the switches is obtained without any doubt, and will not be elaborated here.

[0050] Channels AWG_P1, AWG_P3, AWG_P5, and AWG_P7 are assigned to switch K1, and then connected to interface J1 via switches K5, K7, K9, and K36 to connect to the baseband signal analyzer. This link serves as the AWG_Q+ path to the receiving channel DGT_Q+ of the baseband signal analyzer, and can be used to test modulated signals such as ACLR and EVM.

[0051] Channels AWG_N0, AWG_N2, AWG_N4, and AWG_N6 are assigned to switch K4, and then connected to interface J7 via switches K6, K8, K10, and K37 to connect to the baseband signal analyzer. This link serves as the AWG_I- path to the receiving channel DGT_I- of the baseband signal analyzer, and can be used to test modulated signals such as ACLR and EVM.

[0052] The channels AWG_N1, AWG_N3, AWG_N5 and AWG_N7 are connected to the switch K3, and then through the switches K6, K8, K10 and K37, connected to the interface J6 and the baseband signal analyzer. This link is connected to the receiving channel DGT_Q- of the baseband signal analyzer as the AWG_Q-channel, which can be used to test the modulated signal, such as

[0053] ACLR and EVM, etc.

[0054] Thus, the above can realize the automatic test of the IQ modulated signal of all channels of the AWG. It is noted that the IQ modulated signal test only passes through the switch, and does not pass through the first balance converter U1 and the first wave filter group U2.

[0055] (3) AWG dynamic performance test (single-ended)

[0056] For the channel AWG_P1, through the switches K1, K5, K7, K12, K13, K14, K15, the first wave filter group U2, and the switches K16, K17, connected to the interface J3 and the spectrum analyzer. Through the spectrum analyzer, the single-ended dynamic test of the channel can be completed. The specific switch control and signal flow are as follows:

[0057] AWG_P1->K1_s1c1->K5_s1c1->K7_s2c2->K12_s1c1->K13_s1c2->K14_s2c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, completing the single-ended dynamic performance test of the channel AWG_P1.

[0058] AWG_P3->K1_s2c1->K5_s1c1->K7_s2c2->K12_s1c1->K13_s1c2->K14_s2c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, completing the single-ended dynamic performance test of the channel AWG_P3.

[0059] AWG_P5->K1_s1c2->K5_s2c1->K7_s2c2->K12_s1c1->K13_s1c2->K14_s2c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, completing the single-ended dynamic performance test of the channel AWG_P5.

[0060] AWG_P7->K1_s2c2->K5_s2c1->K7_s2c2->K12_s1c1->K13_s1c2->K14_s2c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, complete the single-ended dynamic performance test of AWG_P7 channel.

[0061] By analogy, AWG_P0, AWG_P2, AWG_P4, AWG_P6; AWG_N1, AWG_N3, AWG_N5, AWG_N7; AWG_N0, AWG_N2, AWG_N4, AWG_N6; a total of 16 channels can be completed in turn. The specific switch control and signal flow can be obtained without doubt by Figure 3 and Figure 2 The switch distribution is not described here.

[0062] The above completes the automatic test of all channels of AWG single-ended dynamic performance, which can realize the automatic test items including THD (total harmonic distortion), IMD3 (third-order intermodulation), NSD (noise power density), SNR (signal-to-noise ratio), SFDR (spurious-free dynamic range) and the like. Note that the AWG single-ended dynamic performance test only passes through the switching switch and the first trap filter group U2, and does not pass through the first balance converter U1.

[0063] (4) AWG dynamic performance test (differential)

[0064] For the differential channel AWG_1:

[0065] AWG_P1 and AWG_N1, AWG_P1 passes through the switching switches K1, K5, K7, K9, K11, and AWG_N1 passes through the switching switches K3, K6, K8, K10, K11, and then passes through the first balance converter U1, the switching switches K13, K14, K15, the first trap filter group U2, the switching switches K16, K17, and is connected to the interface J3 and the spectrum analyzer. The differential dynamic test of the channel can be completed through the spectrum analyzer. The specific switch control and signal flow are as follows:

[0066] AWG_P1->K1_s1c1->K5_s1c1->K7_s1c2->K9_s1c2->K11_s1c1->U1_p;

[0067] AWG_N1->K3_s1c1->K6_s1c1->K8_s1c2->K10_s1c2->K11_s1c2->U1_n.

[0068] Then through the first balanced converter U1 differential to single-ended, after the signal flow to U1->K13_s1c1->K14_s1c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, complete the differential dynamic performance test of AWG_1 channel.

[0069] For differential channel AWG_3:

[0070] AWG_P3->K1_s2c1->K5_s1c1->K7_s1c2->K9_s1c2->K11_s1c1->U1_p;

[0071] AWG_N3->K3_s2c1->K6_s1c1->K8_s1c2->K10_s1c2->K11_s1c2->U1_n.

[0072] Then through the first balanced converter U1 differential to single-ended, after the signal flow to U1->K13_s1c1->K14_s1c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, complete the differential dynamic performance test of AWG_3 channel.

[0073] For differential channel AWG_5:

[0074] AWG_P5->K1_s1c2->K5_s2c1->K7_s1c2->K9_s1c2->K11_s1c1->U1_p;

[0075] AWG_N5->K3_s1c2->K6_s2c1->K8_s1c2->K10_s1c2->K11_s1c2->U1_n.

[0076] Then through the first balanced converter U1 differential to single-ended, after the signal flow to U1->K13_s1c1->K14_s1c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, complete the differential dynamic performance test of AWG_5 channel.

[0077] For differential channel AWG_7:

[0078] AWG_P7->K1_s2c2->K5_s2c1->K7_s1c2->K9_s1c2->K11_s1c1->U1_p;

[0079] AWG_N7->K3_s2c2->K6_s2c1->K8_s1c2->K10_s1c2->K11_s1c2->U1_n.

[0080] Then through the differential to single-ended first balance converter U1 after the signal flow to U1->K13_s1c1->K14_s1c1->K15_s2c1->U2->K16_s1c1->K17_s2c1->J3->spectrum analyzer, complete the differential dynamic performance test of AWG_7 channel.

[0081] In turn, the differential channel AWG_0, AWG_2, AWG_4, AWG_6, a total of 8 differential channels of dynamic performance test can be completed. The specific switch control and signal flow can be obtained without doubt by the switch distribution of Figure 3 And Figure 2 Note that the AWG differential dynamic performance test needs to pass through the switching switch, the first trap group U2 and the first balance converter U1.

[0082] By the above, the automatic test of all channels of AWG differential dynamic performance can be completed, and the automatic test items that can be realized include THD, IMD3, NSD, SNR, SFDR, etc.

[0083] In one embodiment, the DGT switch array 114 can include a second balance converter and two or more switching switches, each switching switch connected between the interconnection interface module 120 and the peripheral interface module 130 in turn, and the second balance converter connected between the switching switches; the second balance converter converts the single-ended signal sent through the peripheral interface module 130 and the corresponding switching switch into a differential signal, and then sends it to the corresponding channel of the DGT through the corresponding switching switch and the interconnection interface module 120. Similarly, the switching switch can be a relay double-parallel single-pole double-throw switch or a relay single-pole double-throw switch. The static contact port and the moving contact port of each single-pole double-throw switch are connected in turn and connected between the interconnection interface module 120 and the peripheral interface module 130, and the control end of each single-pole double-throw switch is connected to the upper computer through the communication unit 140, and according to the received control instruction, the switch is switched to the moving contact port S1 or S2.

[0084] As Figure 4As shown, the DGT switch array 114 includes switching switches K19-K35, and switching switches K38, K39. Switching switches K19-K31, and switching switches K38, K39 are all relay double-parallel single-pole double-throw switches, and switching switches K32-K35 are all relay single-pole double-throw switches. The DGT switch array 114 includes a second balance converter U3, and can further include a second wave trap group U4, and the second balance converter U3 and the second wave trap group U4 are both connected in series between the switching switches. The second balance converter U3 also adopts a balun converter, converts a single-ended signal accessed into a differential signal, and then outputs, and the second balance converter U3 can be used as a shunt. The peripheral interface module 130 further includes interfaces J8-J13, which all adopt Device_SMA radio frequency connectors. The interfaces J8, J9, J12, and J13 are used for connecting a baseband signal analyzer, the interface J10 is used for connecting a vector signal generator, and the interface J11 is used as a reserved peripheral interface, which can be connected to a PMU or other instruments. It can be understood that the PMU test of each channel can be completed by controlling the switching switches of the DGT switch array 114.

[0085] It can be understood that the connection relationship of each device in the DGT switch array 114 is similar to that of the AWG switch array 112, and only one relay single-pole double-throw switch and one Device_SMA radio frequency connector are reduced due to the connection of one peripheral calibration instrument, and the specific connection relationship of the DGT switch array 114 will not be described here.

[0086] Referring to Figure 5 , the power calibration test, the IQ signal test, the single-ended dynamic performance test, and the differential dynamic performance test of each channel of the AWG can be respectively performed through the DGT switch array 114. It needs to be noted that two points, (1) when only the differential dynamic performance test is performed, the first balance converter U3 is passed through; and (2) when the single-ended dynamic performance test and the differential dynamic performance test are performed, the first wave trap group U4 is passed through. The specific calibration test process is as follows:

[0087] (1) DGT power calibration

[0088] For the channel DGT_P1, the switching switch K36 on the AWG side is looped back to the switching switch K38 on the DGT side, and then the switching switches K27, K25, K23, and K19 are passed through, and connected to the channel DGT_P1, so that the power calibration test of the channel can be completed. The specific switch control and signal flow direction are as follows:

[0089] AWG_P1->K1_s1c1->K5_s1c1->K7_s2c2->K9_s2c2->K36_s2c2->inboard wiring (see Figure 5 the blue solid line) loop back to:

[0090] ->K38_s2c2->K27_s2c2->K25_s1c2->K23_s1c1->K19_s1c1->DGT_P1, complete the power calibration test of DGT_P1 channel.

[0091] AWG_P3 -> K1_s2c1 -> K5_s1c1 -> K7_s1c2 -> K9_s2c2 -> K36_s2c2 -> in-board wiring (see Figure 5 the middle blue solid line) loop back to:

[0092] ->K38_s2c2->K27_s2c2->K25_s1c2->K23_s1c1->K19_s2c1->DGT_P3, complete the power calibration test of DGT_P3 channel.

[0093] AWG_P5 -> K1_s1c2 -> K5_s2c1 -> K7_s1c2 -> K9_s2c2 -> K36_s2c2 -> in-board wiring (see Figure 5 the middle blue solid line) loop back to:

[0094] ->K38_s2c2->K27_s2c2->K25_s1c2->K23_s2c1->K19_s1c2->DGT_P5, complete the power calibration test of DGT_P5 channel.

[0095] AWG_P7 -> K1_s2c2 -> K5_s2c1 -> K7_s1c2 -> K9_s2c2 -> K36_s2c2 -> in-board wiring (see Figure 5 the middle blue solid line) loop back to:

[0096] ->K38_s2c2->K27_s2c2->K25_s1c2->K23_s2c1->K19_s2c2->DGT_P7, complete the power calibration test of DGT_P7 channel.

[0097] By analogy, channels DGT_P0, DGT_P2, DGT_P4, DGT_P6 (looped back through Figure 5 the middle orange wiring); DGT_N1, DGT_N3, DGT_N5, DGT_N7 (looped back through Figure 5 the middle purple wiring); DGT_N0, DGT_N2, DGT_N4, DGT_N6 (looped back through Figure 5 the middle brown wiring) can be completed in turn, a total of 16 channels of power calibration. The specific switch control and signal flow direction can be seen from Figure 2 and Figure 4The switch distribution is not doubtly obtained, and thus is not described herein.

[0098] (2) DGT_IQ signal test

[0099] The channels DGT_P0, DGT_P2, DGT_P4 and DGT_P6 are distributed to the switch K20, and then connected to the interface J9 and the baseband signal analyzer through the switches K23, K25, K27 and K38, and this link is connected to the transmitting channel AWG_I+ of the baseband signal analyzer as the DGT_I+ path, which can be used for testing the modulated signal such as ACLR and EVM.

[0100] The channels DGT_P1, DGT_P3, DGT_P5 and DGT_P7 are distributed to the switch K19, and then connected to the interface J8 and the baseband signal analyzer through the switches K23, K25, K27 and K38, and this link is connected to the transmitting channel AWG_Q+ of the baseband signal analyzer as the DGT_Q+ path, which can be used for testing the modulated signal such as ACLR and EVM.

[0101] The channels DGT_N0, DGT_N2, DGT_N4 and DGT_N6 are distributed to the switch K22, and then connected to the interface J13 and the baseband signal analyzer through the switches K24, K26, K28 and K39, and this link is connected to the transmitting channel AWG_I- of the baseband signal analyzer as the DGT_I- path, which can be used for testing the modulated signal such as ACLR and EVM.

[0102] The channels DGT_N1, DGT_N3, DGT_N5 and DGT_N7 are distributed to the double single-pole double-throw switch K21, and then connected to the interface J12 and the baseband signal analyzer through the switches K24, K26, K28 and K39, and this link is connected to the transmitting channel AWG_Q+ of the baseband signal analyzer as the DGT_Q+ path, which can be used for testing the modulated signal such as ACLR and EVM. The specific switch control and signal flow direction can be obtained without doubt by Figure 2 and Figure 4 The switch distribution is not doubtly obtained, and thus is not described herein.

[0103] (3) DGT dynamic performance test (single end)

[0104] For channel DGT_P1, the vector signal generator is connected to interface J10, through switching K35, K34, K33, K32, K31, K30, K25, K23, K19, to DGT_P1, through the vector signal generator can complete the single-ended dynamic test of the channel. Single-ended dynamic test includes SFDR, IMD3, LPF, THD, NSD and SNR test, wherein SFDR, IMD3 and LPF do not pass through the first trap filter group U4, THD, NSD and SNR test need to pass through the first trap filter group U4; The specific switch control and signal flow direction are as follows:

[0105] J10->K35_s2c1->K34_s2c1->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s1c1->K19_s1c1->DGT_P1, complete the single-ended SFDR, IMD3, LPF (low pass filter) and other dynamic performance test of DGT_P1 channel.

[0106] J10->K35_s2c1->K34_s1c1->U4->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s1c1->K19_s1c1->DGT_P1, complete the single-ended THD, NSD, SNR and other dynamic performance test of DGT_P1 channel.

[0107] J10->K35_s2c1->K34_s2c1->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s1c1->K19_s2c1->DGT_P3, complete the single-ended SFDR, IMD3, LPF and other dynamic performance test of DGT_P3 channel.

[0108] J10->K35_s2c1->K34_s1c1->U4->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s1c1->K19_s2c1->DGT_P3, complete the single-ended THD, NSD, SNR and other dynamic performance test of DGT_P3 channel.

[0109] J10->K35_s2c1->K34_s2c1->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s2c1->K19_s1c2->DGT_P5, complete the single-ended SFDR, IMD3, LPF, etc. dynamic performance test of DGT_P5 channel.

[0110] J10->K35_s2c1->K34_s1c1->U4->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s2c1->K19_s1c2->DGT_P5, complete the single-ended THD, NSD, SNR, etc. dynamic performance test of DGT_P5 channel.

[0111] J10->K35_s2c1->K34_s2c1->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s2c1->K19_s2c2->DGT_P7, complete the single-ended SFDR, IMD3, LPF, etc. dynamic performance test of DGT_P7 channel.

[0112] J10->K35_s2c1->K34_s1c1->U4->K33_s1c1->K32_s2c1->K31_s1c2->K30_s1c1->K25_s2c2->K23_s2c1->K19_s2c1->DGT_P7, complete the single-ended THD, NSD, SNR, etc. dynamic performance test of DGT_P7 channel.

[0113] By analogy, the single-ended dynamic performance test of DGT_P0, DGT_P2, DGT_P4, DGT_P6, DGT_N1, DGT_N3, DGT_N5, DGT_N7, DGT_N0, DGT_N2, DGT_N4, DGT_N6, a total of 16 channels can be completed in turn. Figure 2 and Figure 4 The specific switch control and signal flow direction can be obtained without doubt by the switch distribution of

[0114] (4) DGT dynamic performance test (differential)

[0115] For differential channel DGT_1: the vector signal generator is connected to the interface J10, through the switching switch K35, K34; the second wave filter group U4, the switching switch K33, K32, K31, the second balance converter U3, and the switching switch K29; then through the switching switch K27, K25, K23, K19 is connected to DGT_P1; again through the switching switch K28, K26, K24, K21 is connected to DGT_N1; the vector signal generator sends the test signal and can complete the differential dynamic test of the channel. The specific switch control and signal flow direction are as follows:

[0116] As the SFDR dynamic performance test:

[0117] J10->K35_s2c1->K34_s2c1->K33_s1c1->K32_s1c1->K31_s1c1->U3;

[0118] As the THD, NSD, SNR and other dynamic performance tests:

[0119] J10->K35_s2c1->K34_s1c1->U4->K33_s2c1->K32_s1c1->K31_s1c1->U3;

[0120] Then through the single-to-differential second balance converter U3, the signal flow direction is divided into U3_p and U3_n;

[0121] U3_p->K29_s1c1->K27_s1c2->K25_s1c2->K23_s1c1->K19_s1c1->DGT_P1;

[0122] U3_n->K29_s1c2->K28_s1c2->K26_s1c2->K24_s1c1->K21_s1c1->DGT_N1,

[0123] Complete the differential dynamic performance test of DGT_1 channel.

[0124] For differential channel DGT_3:

[0125] U3_p->K29_s1c1->K27_s1c2->K25_s1c2->K23_s1c1->K19_s2c1->DGT_P3;

[0126] U3_n->K29_s1c2->K28_s1c2->K26_s1c2->K24_s1c1->K21_s2c1->DGT_N3, complete the differential dynamic performance test of DGT_3 channel.

[0127] For differential channel DGT_5:

[0128] U3_p->K29_s1c1->K27_s1c2->K25_s1c2->K23_s2c1->K19_s1c2->DGT_P5;

[0129] U3_n->K29_s1c2->K28_s1c2->K26_s1c2->K24_s2c1->K21_s1c2->DGT_N5, completing differential dynamic performance test of DGT_5 channel.

[0130] For differential channel DGT_7:

[0131] U3_p->K29_s1c1->K27_s1c2->K25_s1c2->K23_s2c1->K19_s2c2->DGT_P7;

[0132] U3_n->K29_s1c2->K28_s1c2->K26_s1c2->K24_s2c1->K21_s2c2->DGT_N7, completing differential dynamic performance test of DGT_7 channel.

[0133] By analogy, differential dynamic performance tests of DGT_0, DGT_2, DGT_4, and DGT_6 can be completed respectively. The specific switch control and signal flow direction can be obtained without doubt from the switch distribution of Figure 2 and Figure 4 , which will not be described here.

[0134] By completing the differential dynamic performance automation test of all channels of DGT, the automatic test items that can be realized include THD, IMD3, NSD, SNR, SFDR, LPF, and other dynamic performance tests.

[0135] In one embodiment, a test machine is also provided, including a board card, a peripheral calibration instrument, and the board card automatic calibration test device described above. As shown in Figure 6 , the peripheral calibration instrument can include at least one of a baseband signal analyzer, a power meter, a spectrum analyzer, and a vector signal receiver generator. The test machine can be a digital test machine, and the board card can be a digital-analog hybrid board card. The board card automatic calibration test device performs at least one of power calibration test, IQ signal test, single-ended dynamic performance test, and differential dynamic performance test on the digital-analog hybrid board card.

[0136] Further, the test machine further comprises a host computer connected to the communication unit in the board automatic calibration test device and the board card, and the host computer sends a control instruction to the communication unit according to the relevant information of the board card. The host computer can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices, and the portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, etc. The host computer is responsible for the switching control of the whole test and calibration process, the calculation and storage of compensation values, compensation of compensation differences, etc. The host computer is also connected to the device interface of the test machine to obtain relevant data and send corresponding control instructions to the switching module.

[0137] The board automatic calibration test device and the test machine have the following advantages:

[0138] 1: All interfaces are calibrated through switching by the switching array, which simply and conveniently realizes automatic calibration and improves the calibration efficiency.

[0139] 2: All channels can be traversed through switching by the switching array, which improves the efficiency.

[0140] 3: All peripheral instruments required by the test items can be compatible through the switching array, which improves the efficiency and reduces the risk of damage of the instruments due to high-frequency switching and movement.

[0141] 4: All peripheral interfaces are fixed, and there is no need to frequently replace the interfaces and cables, which reduces the risk of introducing errors and ensures the test precision of the test machine.

[0142] The technical features of the above-described embodiments can be combined arbitrarily, and to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0143] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the utility model patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A board automatic calibration test apparatus, characterized by, The device comprises a switch module, an interconnection interface module, a peripheral interface module and a communication unit, the switch module is connected with the interconnection interface module, the peripheral interface module and the communication unit, the interconnection interface module is connected with a board card, the peripheral interface module is connected with a peripheral calibration instrument, and the communication unit communicates with a host computer; The communication unit receives a control instruction issued by the host computer and transmits the control instruction to the switch module, the switch module switches on and off according to the control instruction, and the peripheral calibration instrument is connected with a corresponding channel of the board card, so that the board card is calibrated by the peripheral calibration instrument.

2. The apparatus of claim 1, wherein, The switch module comprises: An AWG switch array connected with the interconnection interface module, the peripheral interface module and the communication unit, the AWG switch array switches on and off according to the control instruction, and the peripheral calibration instrument is connected with a corresponding channel of an AWG in the board card; A DGT switch array connected with the interconnection interface module, the peripheral interface module and the communication unit, the DGT switch array switches on and off according to the control instruction, and the peripheral calibration instrument is connected with a corresponding channel of a DGT in the board card.

3. The apparatus of claim 2, wherein, The AWG switch array comprises a first balance converter and two or more switch switches, each switch switch connected in sequence is connected between the interconnection interface module and the peripheral interface module, and the first balance converter is connected in series between the switch switches; The first balance converter outputs a corresponding channel of the AWG, converts a differential signal sent through the interconnection interface module and a corresponding switch switch into a single-ended signal, and then transmits the single-ended signal to the peripheral interface module through the corresponding switch switch.

4. The apparatus of claim 2, wherein, The DGT switch array comprises a second balance converter and two or more switch switches, each switch switch connected in sequence is connected between the interconnection interface module and the peripheral interface module, and the second balance converter is connected in series between the switch switches; The second balance converter converts a single-ended signal sent through the peripheral interface module and a corresponding switch switch into a differential signal, and then transmits the differential signal to a corresponding channel of the DGT through the corresponding switch switch and the interconnection interface module.

5. The apparatus of claim 3 or 4, wherein, The switch switch comprises a relay double-parallel single-pole double-throw switch and / or a relay single-pole double-throw switch.

6. The apparatus of any one of claims 1-4, wherein, The interconnection interface module and / or the peripheral interface module comprise an SMA radio frequency connector.

7. A testing machine characterized by, The device comprises a board card, a peripheral calibration instrument and the board card automatic calibration testing device of any one of claims 1-6.

8. The testing machine of claim 7, wherein, The peripheral calibration instrument comprises at least one of a baseband signal analyzer, a power meter, a spectrum analyzer and a vector signal receiver generator.

9. The testing machine of claim 7, wherein, The device further comprises a host computer, the host computer is connected with the board card and the communication unit in the board card automatic calibration testing device, and issues a control instruction to the communication unit according to related information of the board card.

10. The testing machine of claim 9, wherein, The board card is a digital-analog hybrid board card, and the board card automatic calibration testing device performs at least one of power calibration testing, IQ signal testing, single-ended dynamic performance testing and differential dynamic performance testing on the digital-analog hybrid board card.

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