Pixel circuit, array circuit and TFT-LCD display panel
By optimizing the connection structure between transistors and row gate drive lines and column data lines in the pixel circuit of the TFT-LCD panel, row and column signal flipping is achieved, solving the high power consumption problem under the dot flipping method, improving display quality and extending battery life.
Patent Information
- Application Number
- CN202520230838.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2035-02-13
AI Technical Summary
Existing TFT-LCD panels consume too much power when using dot-flipping, resulting in shortened product battery life. Conventional designs can only use row-flipping or column-flipping to reduce power consumption, but this leads to a decrease in display quality.
By uniquely designing the connection structure between the transistors of the sub-pixels in the pixel circuit and the row gate drive lines and column data lines, the flipping of row and column signals is achieved, resulting in a dot flipping effect while maintaining the product's battery life.
While maintaining product battery life, display quality has been improved and power consumption has been reduced.
Smart Images
Figure CN223679801U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to TFT -LCD display panel's point flip technical field, especially in kind pixel circuit, array circuit and TFT -LCD display panel. BACKGROUND
[0002] The polarity of the pixel is mainly flipped in the following four ways: frame flipping (the polarity of the display voltage of adjacent two frames is different), column flipping (the polarity of the display voltage of adjacent two columns is different), row flipping (the polarity of the display voltage of adjacent two rows is different), and point flipping (the polarity of the display voltage of adjacent two pixels is different). Among the above four flipping modes: the point flipping mode can achieve the best picture quality. In the point flipping driving mode, the capacitor coupling effect makes the pixel voltage characteristic more uniform, so the picture display quality is optimal, so high-quality display screens are all point flipping. However, the power consumption of point flipping is also the highest, and the positive and negative charges cancel each other out, which means the consumption of electric energy, and the electric energy is converted into heat energy. Compared with other flipping modes, the power consumption of the point flipping mode is the largest, and the heat dissipation and driving performance of the driving IC are also required to be higher.
[0003] The display of the TFT-LCD panel adopts the point flipping mode, which has the best display effect. However, when the conventional design uses the point flipping mode, the power consumption will increase greatly. The power consumption will affect the product endurance time. For TFT-LCD panel products that require long endurance, most of them can only use row flipping or column flipping to reduce power consumption. UTILITY MODEL CONTENTS
[0004] The existing TFT-LCD panel can only use row flipping or column flipping to reduce power consumption, which leads to a decrease in the display quality of the display panel.
[0005] To solve the above problems, a pixel circuit, an array circuit and a TFT-LCD display panel are provided. The connection structure of the transistor of the sub-pixel in the pixel circuit and the row gate drive line and the column data line is uniquely designed to realize point flipping through row and column signal flipping. The display quality is improved while maintaining the product endurance.
[0006] In a first aspect, a pixel circuit includes:
[0007] Pixel units of adjacent two rows;
[0008] Gate drive lines of adjacent two rows;
[0009] First, second, third and fourth column data lines;
[0010] The pixel unit includes R sub-pixel, G sub-pixel and B sub-pixel;
[0011] At least one of the R sub-pixel, the G sub-pixel and the B sub-pixel is electrically connected with one of the adjacent row gate driving lines through the gate of the transistor;
[0012] The remaining sub-pixels of the R sub-pixel, the G sub-pixel and the B sub-pixel are electrically connected with the other of the adjacent row gate driving lines through the gate of the transistor;
[0013] The transistors of the R sub-pixel, the G sub-pixel and the B sub-pixel are electrically connected with the corresponding first column data line, second column data line, third column data line and fourth column data line respectively.
[0014] In a first possible implementation of the pixel circuit, the G sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel is electrically connected with the previous row gate driving line of the adjacent row gate driving lines through the gate of the transistor, and the R sub-pixel and the B sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel are electrically connected with the next row gate driving line of the adjacent row gate driving lines through the gate of the transistor.
[0015] The transistor of the G sub-pixel is further electrically connected with the second column data line.
[0016] The transistors of the R sub-pixel and the B sub-pixel are further electrically connected with the first column data line and the third column data line respectively.
[0017] In a second possible implementation of the first possible implementation of the pixel circuit, the column data line is used to input negative voltage to the transistor of the connected sub-pixel when the previous row gate driving line is scanned and driven, and input positive voltage to the transistor of the connected sub-pixel when the next row gate driving line is scanned and driven.
[0018] In a third possible implementation of the pixel circuit, the G sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel of the adjacent two rows of pixel units is electrically connected with the same row gate driving line through the gate of the transistor, and the R sub-pixel and the B sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel of the adjacent two rows of pixel units are electrically connected with the same row gate driving line through the gate of the transistor.
[0019] The transistor of the G sub-pixel of the previous row is further electrically connected with the second column data line, and the transistor of the G sub-pixel of the next row is further electrically connected with the third column data line.
[0020] The transistors of the R sub-pixel and the B sub-pixel of the previous row are further electrically connected with the first column data line and the third column data line respectively, and the transistors of the R sub-pixel and the B sub-pixel of the next row are further electrically connected with the second column data line and the fourth column data line respectively.
[0021] In combination with the third possible implementation manner of the present application, in the fourth possible implementation manner, the first column of data lines and the third column of data lines are used to input positive voltage to the transistor of the connected sub-pixel when the row gate driving line is scanned and driven, and the second column of data lines and the fourth column of data lines are used to input negative voltage to the transistor of the connected sub-pixel when the row gate driving line is scanned and driven.
[0022] In the second aspect, an array circuit comprises the pixel circuit of the first aspect.
[0023] In the third aspect, a TFT-LCD display panel comprises the array circuit of the second aspect.
[0024] The pixel circuit, the array circuit and the TFT-LCD display panel of the present application are implemented by uniquely designing the connection structure of the transistor of the sub-pixel, the row gate driving line and the column data line in the pixel circuit, so that the point inversion can be realized by the inversion of the row and column signals, the display quality is improved while the product endurance is maintained. BRIEF DESCRIPTION OF DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0026] Figure 1 is a circuit connection schematic diagram of a pixel circuit in the prior art;
[0027] Figure 2 is a circuit connection schematic diagram of a pixel circuit in the embodiment 1 of the present application;
[0028] Figure 3 is a circuit connection schematic diagram of a pixel circuit in the embodiment 2 of the present application. DETAILED DESCRIPTION
[0029] The technical solutions in the present application will be described clearly and completely in combination with the drawings in the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. The use herein of the terms "and / or" includes a set of one or more associated listed items.
[0031] It is to be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or indirectly on or connected to the other element by way of one or more other elements.
[0032] It is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like as used herein are intended to refer to the orientation or position of the apparatus or element shown in the drawings as viewed in the drawings, and are merely used for convenience in describing the present application and simplifying the description, and are not intended to indicate or imply that the apparatus or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application.
[0033] In addition, the terms "first", "second", "third", etc. are used herein only to describe various conditions, and cannot be construed as indicating or implying relative importance or an implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "plurality" is two or more, unless otherwise specifically defined.
[0034] The existing TFT-LCD panel, in order to reduce power consumption, can only adopt the row inversion or column inversion mode, resulting in the display quality of the display panel being reduced, such as Figure 1 , Figure 1 is a circuit connection schematic diagram of a pixel circuit in the prior art.
[0035] In view of the above problems, a pixel circuit and a TFT-LCD display panel are provided.
[0036] In a first aspect, a pixel circuit includes two adjacent rows of pixel units, two adjacent rows of gate driving lines, a first column of data lines S1, a second column of data lines S2, a third column of data lines S3, and a fourth column of data lines S4. The pixel units include R sub-pixels, G sub-pixels, and B sub-pixels. At least one of the R sub-pixels, the G sub-pixels, and the B sub-pixels is electrically connected to one of the adjacent rows of gate driving lines through a gate of a transistor. The remaining sub-pixels of the R sub-pixels, the G sub-pixels, and the B sub-pixels are electrically connected to the other of the adjacent rows of gate driving lines through a gate of a transistor. The transistors of the R sub-pixels, the G sub-pixels, and the B sub-pixels are electrically connected to the first column of data lines S1, the second column of data lines S2, and the third column of data lines S3, respectively. The connection structure of the transistors of the sub-pixels in the pixel circuit to the rows of gate driving lines and the columns of data lines is uniquely designed, so that the display quality is improved while maintaining the product endurance by point inversion through the inversion of the row and column signals.
[0037] In the embodiments of the present application, when the transistor is electrically connected to the column of data lines, the source of the transistor is electrically connected to the column of data lines; when the transistor is electrically connected to the gate driving line, the gate of the transistor is electrically connected to the gate driving line; and when the transistor is electrically connected to the sub-pixel, the drain of the transistor is electrically connected to the corresponding sub-pixel.
[0038] First embodiment
[0039] As Figure 2 , Figure 2 is a circuit connection schematic diagram of a pixel circuit in the first embodiment of the present application. The G sub-pixel of the R sub-pixel, the G sub-pixel, and the B sub-pixel is electrically connected to the previous row of gate driving lines (G0) through the gate of the transistor. The R sub-pixel and the B sub-pixel of the R sub-pixel, the G sub-pixel, and the B sub-pixel are electrically connected to the next row of gate driving lines (G1) through the gate of the transistor. The transistor of the G sub-pixel is further electrically connected to the second column of data lines S2. The transistors of the R sub-pixel and the B sub-pixel are further electrically connected to the first column of data lines S1 and the third column of data lines S3, respectively.
[0040] In the array circuit, the transistors of the sub-pixels in the pixel units are sequentially connected to the gate driving lines G3, G4, …, Gn and the data lines (S1, S2, S3, S4, …, Sn) through the same connection structure.
[0041] In the embodiment, the column of data lines is used to input a negative voltage to the transistor of the connected sub-pixel when the previous row of gate driving lines is scanned and driven, and to input a positive voltage to the transistor of the connected sub-pixel when the next row of gate driving lines is scanned and driven.
[0042] In the embodiment, the column data line is kept synchronous with the row gate driving line, and data signals are provided in turn according to the signal mode of positive pressure-negative pressure-positive pressure-negative pressure...
[0043] As Figure 2 The same row signal and column signal driving as the conventional signal is adopted, when G0 is opened, S1, S2 and S3 provide negative pressure, at this time, only S2 has a connection triode, so only G0 and S2 collocate the pixel to realize negative pressure, when G1 is opened, S1, S2 and S3 provide positive pressure, at this time, G1 and S1, S3 collocate the pixel to have a connection triode, so positive pressure is displayed, and the like. Figure 2 It can be known that when the same row flip driving signal is provided, the actual point flip display in the pixel is realized.
[0044] Second embodiment
[0045] As Figure 3 , Figure 3 is a circuit connection schematic diagram of a pixel circuit in the second embodiment in the present application. The G sub-pixels in the R sub-pixels, the G sub-pixels and the B sub-pixels of the pixel units of the adjacent two rows are electrically connected with the same row gate driving line through the gate of the transistor, and the R sub-pixels and the B sub-pixels in the R sub-pixels, the G sub-pixels and the B sub-pixels of the pixel units of the adjacent two rows are electrically connected with the same row gate driving line through the gate of the transistor;
[0046] The transistor of the G sub-pixel of the previous row is further electrically connected with the second column data line S2, and the transistor of the G sub-pixel of the next row is further electrically connected with the third column data line S3;
[0047] The transistors of the R sub-pixel and the B sub-pixel of the previous row are further electrically connected with the first column data line S1 and the third column data line S3 respectively, and the transistors of the R sub-pixel and the B sub-pixel of the next row are further electrically connected with the second column data line S2 and the fourth column data line S4 respectively.
[0048] In the array circuit, the transistors of the sub-pixels in the pixel unit are connected with the gate driving lines G3, G4, …, Gn and the data lines (S1, S2, S3, S4, …, Sn) in turn according to the same connection structure.
[0049] In the embodiment, the first column data line S1 and the third column data line S3 are used to input positive pressure to the connected transistors of the sub-pixels when the row gate driving line is scanned and driven, and the second column data line S2 and the fourth column data line S4 are used to input negative pressure to the connected transistors of the sub-pixels when the row gate driving line is scanned and driven.
[0050] In the embodiment, when the row gate drive line is scanned in sequence, the odd column data line and the even column data line input positive pressure and negative pressure in sequence, when G0 is opened, S1 and S3 provide positive pressure, S2 provides negative pressure, at this time, only S2 has a connection transistor, therefore only G0 and S2 collocate the pixel to realize negative pressure, when G1 is opened, S1 and S3 provide positive pressure, S2 and S4 provide negative pressure, at this time, the pixel collocated by G1 and S1 and S3 has a connection transistor, therefore positive pressure is displayed, the pixel collocated by G1 and S2 and S4 has a connection transistor, negative pressure is displayed, and the like is sequentially carried out. Figure 2 Compared with the prior art, the column data line (S1, S2, S3 and S4) does not need to switch positive pressure and negative pressure every row, power consumption is further reduced, and dot inversion display can still be carried out.
[0051] In a second aspect, an array circuit comprises the pixel circuit of the first aspect.
[0052] In a third aspect, a TFT-LCD display panel comprises the array circuit of the second aspect.
[0053] The pixel circuit, the array circuit and the TFT-LCD display panel of the utility model realize dot inversion through the inversion of row and column signals by the unique design of the connection structure of the transistor of the sub-pixel in the pixel circuit and the row gate drive line and the column data line, improve the display quality while keeping the product endurance.
[0054] The above is only the preferred embodiment of the utility model, and does not limit the utility model, and any modification, equivalent replacement, improvement and the like made within the spirit and principle of the utility model should be included in the protection scope of the utility model.
Claims
1. A pixel circuit, characterized by comprising: The pixel circuit comprises: adjacent two rows of pixel units; adjacent two rows of gate driving lines; a first column data line, a second column data line, a third column data line and a fourth column data line; the pixel unit comprises an R sub-pixel, a G sub-pixel and a B sub-pixel; at least one of the R sub-pixel, the G sub-pixel and the B sub-pixel is electrically connected to one of the adjacent row gate driving lines through the gate of a transistor; the remaining sub-pixels of the R sub-pixel, the G sub-pixel and the B sub-pixel are electrically connected to the other of the adjacent row gate driving lines through the gate of a transistor; the transistors of the R sub-pixel, the G sub-pixel and the B sub-pixel are respectively electrically connected to the corresponding first column data line, second column data line, third column data line and fourth column data line.
2. The pixel circuit of claim 1, wherein, the G sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel is electrically connected to the previous row gate driving line of the adjacent row gate driving lines through the gate of a transistor, and the R sub-pixel and the B sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel are electrically connected to the next row gate driving line of the adjacent row gate driving lines through the gate of a transistor; the transistor of the G sub-pixel is further electrically connected to the second column data line; the transistors of the R sub-pixel and the B sub-pixel are respectively electrically connected to the first column data line and the third column data line.
3. The pixel circuit of claim 2, wherein, the column data line is used to input negative voltage to the transistor of the connected sub-pixel when the previous row gate driving line is scanned and driven, and input positive voltage to the transistor of the connected sub-pixel when the next row gate driving line is scanned and driven.
4. The pixel circuit of claim 1, wherein, the G sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel of the adjacent two rows of pixel units is electrically connected to the same row gate driving line through the gate of a transistor, and the R sub-pixel and the B sub-pixel of the R sub-pixel, the G sub-pixel and the B sub-pixel of the adjacent two rows of pixel units are electrically connected to the same row gate driving line through the gate of a transistor; the transistor of the G sub-pixel of the previous row is further electrically connected to the second column data line, and the transistor of the G sub-pixel of the next row is further electrically connected to the third column data line; the transistors of the R sub-pixel and the B sub-pixel of the previous row are respectively electrically connected to the first column data line and the third column data line, and the transistors of the R sub-pixel and the B sub-pixel of the next row are respectively electrically connected to the second column data line and the fourth column data line.
5. The pixel circuit of claim 4, wherein, the first column data line and the third column data line are used to input positive voltage to the transistor of the connected sub-pixel when the row gate driving line is scanned and driven, and the second column data line and the fourth column data line are used to input negative voltage to the transistor of the connected sub-pixel when the row gate driving line is scanned and driven.
6. An array circuit, comprising: The pixel circuit comprises the pixel circuit of any one of claims 1-5. 7.A TFT-LCD display panel, characterized in that, The array circuit comprises the array circuit of claim 6.