Chip structure and mass spectrometer

Abstract

The embodiment of the utility model belongs to the technical field of mass spectrometers, and relates to a chip structure and a mass spectrometer. The chip structure comprises a chip substrate which is used for bearing a substrate to be detected; and the conductive layer covers the lower surface of the chip substrate. The conductive layer covers the lower surface of the chip substrate, so that after the chip substrate is placed on the bracket, the abutting part of the bracket abuts against the conductive layer. After the bracket is powered up, the conductive layer is electrified, the electrified conductive layer can generate a uniform electric field, and the initial positions of electric field lines of the electric field are the same, so that after a plurality of substrates to be detected are placed on the upper surface of the chip substrate, the substrates to be detected can be positioned on the same equipotential plane, and the detection accuracy of the substrates to be detected is ensured; the high repeatability caused by the fact that the to-be-detected matrix is located on different equipotential planes is avoided, and the ionization degree of the to-be-detected matrix can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mass spectrometry instruments, and more particularly to a chip structure and a mass spectrometry instrument. BACKGROUND

[0002] The mass spectrometry instrument of the prior art has low mass number detection accuracy. Taking a matrix assisted laser desorption ionization time-of-flight mass spectrometer as an example, its main operating principle is as follows: a sample containing a to-be-detected matrix is irradiated by a laser to ionize the to-be-detected matrix and charge it. Then, through the action of an electric field, the ionized charged ions pass through a time-of-flight mass analyzer and finally reach a detector. By analyzing the flight time difference between the ions, ions of different mass numbers can be distinguished, thereby achieving the purpose of detecting the mass number. According to the detection operating principle, the uniformity of the electric field distribution will affect the final detected mass number and the ionization degree of the to-be-detected matrix.

[0003] When using the matrix assisted laser desorption ionization time-of-flight mass spectrometer, a chip preform and a to-be-detected matrix need to be packaged as a finished product, and then the packaged chip is ionized so that the to-be-detected matrix inside is ionized. Before ionization, the chip is placed inside a chip holder, and a certain gap between the bottom of the chip and the inner wall of the chip holder is needed to place the remaining devices. Therefore, the inner bottom wall of the chip holder needs to be provided with an abutment portion to support the chip. When the matrix assisted laser desorption ionization time-of-flight mass spectrometer is used for nucleic acid detection, the chip used is an insulating material, such as a silicon-based chip.

[0004] Please refer to Figure 1 At this time, the inner bottom wall of the chip holder is usually lower than the upper surface of the abutment portion, and there can also be a height difference between the inner bottom walls of the chip holder, so that the electric field strength formed by the final chip structure is not uniform everywhere, that is, the initial position of the electric field line formed on the abutment portion is higher, and the initial position of the electric field line on the inner bottom wall of the chip holder is lower than that of the abutment portion, and the to-be-detected matrix on the chip cannot be located on the same equipotential surface in the electric field.

[0005] In summary, the existing chip structure has an uneven electric field for the to-be-detected matrix inside during detection, which cannot be located on the same equipotential surface, thereby resulting in high detection result quality repeatability, low ionization degree, and low accuracy. INNOVATION CONTENT

[0006] To solve the above technical problems, the embodiments of the present application adopt the following solutions:

[0007] A chip structure, comprising:

[0008] a chip substrate for carrying a to-be-detected matrix;

[0009] The conductive layer covers a lower surface of the chip substrate.

[0010] Further, the chip structure further comprises a bracket, the bracket is provided with a receiving groove and an abutting portion located in the receiving groove, the chip substrate is located in the receiving groove, and the conductive layer abuts against the abutting portion.

[0011] Further, the receiving groove comprises a first sub-receiving groove and a second sub-receiving groove, and the abutting portion is located between the first sub-receiving groove and the second sub-receiving groove, so as to separate the first sub-receiving groove and the second sub-receiving groove.

[0012] Further, the conductive layer comprises a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer covers a lower surface of the chip substrate, and the second sub-conductive layer covers a side wall of the chip substrate and abuts against a side wall of the receiving groove.

[0013] Further, the chip structure further comprises a first magnetic attraction member and a second magnetic attraction member, the first magnetic attraction member is connected to a bottom of the chip substrate or the conductive layer, the second magnetic attraction member is arranged in the receiving groove, and the first magnetic attraction member and the second magnetic attraction member are oppositely arranged along a direction from the chip substrate to the receiving groove.

[0014] Further, the conductive layer has a resistance of 5-10 ohms.

[0015] Further, the chip structure further comprises a hydrophobic layer and a hydrophilic layer arranged in sequence, and a projection area of the hydrophilic layer on the chip substrate is smaller than a projection area of the hydrophobic layer on the chip substrate.

[0016] Further, the hydrophobic layer has a thickness of 200-1000 nm; and / or,

[0017] the hydrophilic layer has a thickness of 200-1000 nm, and / or,

[0018] the conductive layer has a thickness of 100-300 nm.

[0019] Further, the hydrophilic layer comprises a plurality of sub-hydrophilic layers, and the plurality of sub-hydrophilic layers are distributed on the hydrophobic layer at equal intervals.

[0020] wherein, the sub-hydrophilic layer has a diameter of 200-500 μm; and / or,

[0021] a spacing between adjacent sub-hydrophilic layers is 2-10 mm.

[0022] Correspondingly, the application further provides a mass spectrometer, which comprises the chip structure according to any one of the above embodiments.

[0023] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0024] Since the conductive layer covers the lower surface of the chip substrate, when the chip substrate is placed on the bracket, the abutting portion of the bracket will abut against the conductive layer. When the bracket is powered on, the conductive layer will also be electrified, and the electrified conductive layer will generate a uniform electric field, and the electric field lines of the electric field have the same initial position, so that after the upper surface of the chip substrate is placed with a plurality of to-be-detected substrates, each to-be-detected substrate can be located on the same equipotential surface, thereby ensuring the detection accuracy of the to-be-detected substrates and avoiding high repeatability caused by the to-be-detected substrates being located on different equipotential surfaces. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the schemes in the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0026] Figure 1 is a sectional view of the chip structure of the prior art;

[0027] Figure 2 is a structural schematic diagram of the chip of the embodiments of the present application;

[0028] Figure 3 is a sectional view of the chip structure of the embodiments of the present application;

[0029] Figure 4 is another structural schematic diagram of the chip structure of the embodiments of the present application.

[0030] Reference signs:

[0031] Chip structure 10, chip substrate 100, bracket 200, abutting portion 210, accommodating groove 220, conductive layer 300, hydrophobic layer 400, hydrophilic layer 500. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0033] In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing surface direction in the drawings, unless otherwise specified. In addition, in the description of the present application, the term "comprising" means "including but not limited to". The terms first, second, third, etc. are only used as labels and do not impose numerical requirements or establish an order.

[0034] In the present application, the association relationship of the associated objects is described by "and / or", which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. Wherein A and B can be singular or plural.

[0035] In the present application, "at least one" means one or more, and "multiple" means two or more. "At least one", "at least one of the following" or the like means any combination of these items, including any combination of single item or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c" can represent a, b, c, a-b (i.e. a and b), a-c, b-c, or a-b-c, wherein a, b, and c can be single or multiple.

[0036] Various embodiments of the present application can exist in the form of a range; it should be understood that the description in the form of a range is only for the convenience and brevity, and should not be understood as a hard limit on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. In addition, whenever a numerical range is indicated in this document, it refers to any cited number (fraction or integer) within the indicated range.

[0037] Please refer to Figure 2 and Figure 3 , Figure 3 In the present application, the Z direction is the up-down direction, and the present application provides a chip structure 10, which comprises:

[0038] A chip substrate 100, the chip substrate 100 is used to carry a to-be-detected substrate;

[0039] A conductive layer 300, the conductive layer 300 covers the lower surface of the chip substrate 100.

[0040] In the embodiment, the conductive layer 300 covers the lower surface of the chip substrate 100, so when the chip substrate 100 is placed on the bracket 200, the abutting portion 210 of the bracket 200 will abut against the conductive layer 300. When the bracket 200 is powered on, the conductive layer 300 will also be charged, and the charged conductive layer 300 will generate a uniform electric field as shown in FIG. 9, and the electric field lines of the electric field have the same initial position, so when the upper surface of the chip substrate 100 is placed on a plurality of to-be-detected substrates, each to-be-detected substrate can still be located on the same equipotential surface, thereby ensuring the detection accuracy of the to-be-detected substrates and avoiding high repeatability caused by the to-be-detected substrates being located on different equipotential surfaces. Figure 3

[0041] Further, referring to Figure 1 and Figure 2 , the chip structure 10 further comprises a bracket 200, the bracket 200 is provided with a containing groove 220 and an abutting portion 210 located in the containing groove 220, the chip substrate 100 is located in the containing groove 220, and the conductive layer 300 abuts against the abutting portion 210.

[0042] In the embodiment, the bracket 200 can accommodate and fix the chip substrate 100, so as to avoid the chip substrate 100 from shaking and deviating from the preset position, thereby improving the detection accuracy of the to-be-detected substrates.

[0043] Further, referring to Figure 2 and Figure 3 , the containing groove 220 comprises a first sub-containing groove and a second sub-containing groove, and the abutting portion 210 is located between the first sub-containing groove and the second sub-containing groove and used for separating the first sub-containing groove and the second sub-containing groove.

[0044] In the embodiment, the first containing groove and the second containing groove can accommodate devices with different heights inside the bracket 200, so as to facilitate the chip structure 10 to carry modules with different functions, such as carrying magnets or conductive devices with different heights, and the abutting portion 210 located between the first sub-containing groove and the second sub-containing groove can make the chip substrate 100 bear force uniformly and avoid tilting towards the first sub-containing groove or the second sub-containing groove. It should be understood that when the devices placed in the first sub-containing groove and the second sub-containing groove do not affect each other, the abutting portion 210 can be provided as a plurality of protruding structures, such as columnar structures, which are distributed side by side and at intervals. Compared with the continuous structure of the abutting portion 210, the abutting portion 210 with a plurality of columnar structures can reduce the contact area of the abutting portion 210 and the conductive layer 300, thereby avoiding that the contact area of the abutting portion 210 and the conductive layer 300 is too large to affect the electric field and the equipotential surface.

[0045] Further, referring to Figure 2 and Figure 3 ​The conductive layer 300 further comprises a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer covers the lower surface of the chip substrate 100, and the second sub-conductive layer covers the sidewall of the chip substrate 100 and abuts against the sidewall of the accommodating groove 220.

[0046] In the embodiment, after the second sub-conductive layer covers the sidewall of the chip substrate 100, the second sub-conductive layer can fix the chip substrate 100 to a certain extent, and the bracket 200 can deliver the current to the conductive layer 300 through the sidewall of the accommodating groove 220, thereby improving the efficiency of the bracket 200 in delivering the current to the conductive layer 300. It should be understood that the conductive layer 300 can further comprise a third sub-conductive layer, and the third sub-conductive layer covers the upper surface of the chip substrate. When the chip structure 10 comprises the hydrophobic layer 400 and the hydrophilic layer 500, the hydrophobic layer is arranged on the upper surface of the third sub-conductive layer.

[0047] Further, referring to Figure 2 and Figure 3 , the chip structure 10 further comprises a first magnetic attraction member and a second magnetic attraction member, the first magnetic attraction member is connected to the bottom of the chip substrate 100 or the conductive layer 300, the second magnetic attraction member is arranged in the accommodating groove 220, and the first magnetic attraction member and the second magnetic attraction member are oppositely arranged along the direction from the chip substrate 100 to the accommodating groove 220.

[0048] In the embodiment, the chip structure 10 can be fixed by the magnetic attraction between the first magnetic attraction member and the second magnetic attraction member, so as to fix the chip substrate 100 with the conductive layer 300 and the bracket 200, and avoid the chip substrate 100 from shaking compared with the bracket 200, thereby causing the detection substrate on the chip substrate 100 to be separated from the ionization position. Compared with the connection mode of using buckles, the connection mode of the embodiment does not need to be assembled, and the small-amplitude self-adaptive position automatic adjustment can be completed by the magnetic attraction between the first magnetic attraction member and the second magnetic attraction member. In summary, the chip structure 10 of the embodiment has high stability, is convenient to assemble, and has high production efficiency.

[0049] Further, referring to Figure 2 and Figure 3 , the resistance of the conductive layer 300 is 5-10 ohms; and / or,

[0050] The material of the chip substrate 100 comprises at least one of silicon-based glass, polyether ether ketone, polytetrafluoroethylene, and ceramic composite material; and / or,

[0051] The material of the conductive layer 300 comprises at least one of indium tin oxide, graphene, conductive metal, and carbon nanotube.

[0052] In the embodiment, the resistance range of the conductive layer 300 can make the conductive layer 300 have better conductive performance. After the bracket 200 is powered on, the current can flow more smoothly in the conductive layer 300, so as to quickly and stably establish an electric field. In this way, the substrate to be detected on the upper surface of the chip substrate 100 can be quickly placed on the equipotential surface determined by the electric field, so as to provide a stable electrical environment for detection and improve the response speed and efficiency of detection. The material of the conductive substrate can resist the erosion of various chemical reagents, is suitable for complex sample processing and analysis environment, ensures that the chip will not be damaged in the long-term use process, has good insulation performance, can effectively isolate the conductive layer 300, and ensures the stability of the electrical performance of the chip substrate 100. The material of the conductive layer 300 has high electron mobility and conductivity, can quickly conduct current, and realizes efficient electric field control; at the same time, it has high strength, high toughness and good flexibility, can withstand certain external force and deformation, and is suitable for various complex operation environments.

[0053] Further, referring to Figures 2 to 4 , the chip structure 10 further comprises a hydrophobic layer 400 and a hydrophilic layer 500 which are sequentially stacked, and the projection area of the hydrophilic layer 500 on the chip substrate 100 is smaller than the projection area of the hydrophobic layer 400 on the chip substrate 100.

[0054] In the embodiment, because the projection area of the hydrophilic layer 500 on the chip substrate 100 is smaller than the projection area of the hydrophobic layer 400, when the substrate to be detected enters the hydrophilic layer 500, it is adsorbed to the hydrophilic layer 500 and is blocked by the hydrophobic layer 400 around the hydrophilic layer 500, so as to limit the substrate to be detected in the area where the hydrophilic layer 500 is located. The hydrophobic layer 400 can also effectively prevent cross contamination between different substrates to be detected. When multiple substrates to be detected exist on the chip substrate 100 at the same time, the hydrophobic layer 400 can act as a physical barrier to prevent mutual diffusion and mixing between the substrates to be detected, in cooperation with the adsorption effect of the hydrophilic layer 500. In this way, each substrate to be detected can be independently detected without being disturbed by other samples, so as to ensure the reliability of the detection result.

[0055] Further, referring to Figure 2 and Figure 3 , the thickness of the hydrophobic layer 400 is 200nm-1000nm; and / or,

[0056] the thickness of the hydrophilic layer 500 is 200nm-1000nm, and / or,

[0057] the thickness of the conductive layer 300 is 100nm-300nm; and / or,

[0058] The material of the hydrophobic layer 400 includes at least one of silica, cellulose and its derivatives, and polyvinyl alcohol; and / or,

[0059] The material of the hydrophobic layer 400 includes at least one of polydimethylsiloxane, fluorine-containing polymer, and polystyrene.

[0060] In this embodiment, the thickness of the hydrophobic layer 400 can ensure that it has sufficient barrier capability for the to-be-detected matrix. It can effectively prevent the to-be-detected matrix from diffusing to the non-designated area, and at the same time, it will not occupy too much space due to being too thick, affecting the overall structural compactness of the chip. The thickness of the hydrophilic layer 500 can ensure that the hydrophilic layer 500 has sufficient adsorption capacity. It can firmly adsorb the to-be-detected matrix and prevent it from accidentally falling off during the detection process, ensuring the stability and reliability of the detection. The thickness of the conductive layer 300 can save material costs while ensuring good conductivity, that is, it can avoid wasting materials due to being too thick while meeting the current transmission requirements of the conductive layer 300 and ensuring the stable establishment of the electric field. The material of the hydrophobic layer 400 can improve the adsorption and enrichment efficiency of the sample, thereby improving the sensitivity of mass spectrometric detection. For example, by selecting a hydrophobic material with specific surface properties, the adsorption capacity for the to-be-detected matrix can be enhanced, allowing more sample molecules to be concentrated in the detection area and improving the strength of the detection signal. The material of the hydrophilic layer 500 has good biocompatibility and is suitable for the analysis of biological samples. For example, a hydrophobic layer 400 containing these materials can be used to process biological samples such as proteins, reducing non-specific adsorption of biological molecules such as proteins and improving the accuracy of detection.

[0061] Further, referring to Figures 2 to 4 , the hydrophilic layer 500 includes a plurality of sub-hydrophilic layers, and the plurality of sub-hydrophilic layers are distributed equidistantly on the hydrophobic layer 400;

[0062] wherein the diameter of the sub-hydrophilic layer is 200 μm-500 μm; and / or,

[0063] The spacing between adjacent sub-hydrophilic layers is 2 mm-10 mm.

[0064] In this embodiment, the equidistant distribution of the plurality of sub-hydrophilic layers can achieve simultaneous processing and detection of a plurality of to-be-detected matrices. In the limited area of the chip substrate 100, the spacing between the sub-hydrophilic layers of this embodiment allows each sub-hydrophilic layer to be independent of each other, allowing the hydrophilic layer 500 to simultaneously adsorb multiple or different to-be-detected matrices for detection, thereby improving the detection efficiency. The diameter of the sub-hydrophilic layer (200 μm-500 μm) can ensure that each sub-hydrophilic layer can effectively adsorb an appropriate amount of to-be-detected matrix. Neither will it be insufficient due to a too small diameter, affecting the sensitivity of the detection; nor will it cause too much adsorption of the matrix due to a too large diameter, affecting the accuracy of the detection.

[0065] It should be understood that when the matrix assisted laser desorption ionization time-of-flight mass spectrometer is used for microorganism identification, the material of the chip substrate can be a stainless steel sheet. The stainless steel is a conductive material and the surface is flat. When high voltage is applied to the mass spectrometer, the starting point of the electrostatic field is the stainless steel sheet. Therefore, the potential of the sample points at different positions on the stainless steel sheet is the same, and there is no influence on the mass repeatability of different sample points caused by uneven electric field. However, when the matrix assisted laser desorption ionization time-of-flight mass spectrometer is used for nucleic acid detection, the material of the chip substrate needs to be a non-conductive silicon-based glass. Therefore, when the chip substrate is placed in the bracket, the mass number repeatability of the measurement is high and the accuracy is poor.

[0066] In view of the problem that the matrix assisted laser desorption ionization time-of-flight mass spectrometer has high repeatability and poor accuracy when used for nucleic acid detection, a stainless steel target plate can be used instead of a silicon chip target plate, or a software algorithm can be used to correct the mass number of different sample points. However, the above two methods have certain problems: first, the chip substrate for nucleic acid mass spectrometry is designed for single use to avoid cross contamination. If a stainless steel target plate is used as a chip substrate, it will become a non-single-use chip, and it is not convenient to pre-embed the sample matrix on the chip substrate, which ultimately leads to high production cost and low production efficiency of the chip structure; second, in the software algorithm correction scheme, it only works when there are known mass numbers in the mass spectrum. When the peaks in the mass spectrum are unknown mass numbers, the software algorithm cannot accurately identify the true mass number of each peak, so it cannot accurately correct the error.

[0067] In summary, neither the stainless steel target plate nor the software algorithm correction can perfectly solve the problem of mass repeatability of different sample points on the chip substrate.

[0068] To solve the above problems, the present application also provides a mass spectrometer, which comprises the chip structure according to any one of the above embodiments.

[0069] In the present embodiment, since the mass spectrometer comprises the chip structure according to any one of the above embodiments, the initial positions of the electric field lines of the electrostatic field generated by the conductive layer are consistent, and each to-be-detected matrix on the chip substrate is located on the same equipotential surface. Therefore, the problem of high mass repeatability of each to-be-detected matrix can be avoided.

[0070] The chip structure of the present application will be described below by way of examples.

[0071] Embodiment

[0072] In the present embodiment, the chip with the above chip structure is prepared by the following method:

[0073] Step one, divide a piece of 8-inch silicon-based glass mother version into chip base with size of 30*20mm.

[0074] Step two, use magnetron sputtering vacuum coating technology to coat ito on the lower surface of the chip base, the thickness of ito film is 185nm, and the resistance value is 6-8Ω.

[0075] Step three, coat a layer of hydrophobic layer on the upper surface of the chip base after ito film coating.

[0076] Step four, after coating the hydrophobic coating, use mask tool to shield the chip except the sample point, and coat a hydrophilic layer on the sample point area.

[0077] Step five, use sample point equipment to pre-embed the detection matrix on the sample point, and package the finished chip after drying.

[0078] Comparative example

[0079] The comparative example and the embodiment are basically the same, the difference is that step three is omitted, and a layer of hydrophobic coating is directly coated on the chip and the ground.

[0080] The finished chip of the embodiment and the finished chip of the prior art silicon chip of the comparative example are used as a component of mass spectrometer, and the data of the mass repeatability and ionization efficiency (represented by peak intensity) of the two are obtained. The data is as follows:

[0081]

[0082] According to the table, in the case of three different characteristic peaks, the reduction of repeatability of the embodiment is greater than that of the comparative example, and the smaller the characteristic peak, the greater the reduction. It shows that the chip structure of the embodiment can effectively reduce the mass repeatability. At the same time, with the increase of the characteristic peak (the increase of the mass number of ions), the increase of the peak intensity of the embodiment compared with the comparative example also increases, which shows that the chip structure of the embodiment can improve the ionization efficiency of the mass spectrometer.

[0083] Obviously, the above-described embodiments are only some embodiments but not all embodiments of the present application, and the preferred embodiments of the present application are shown in the drawings, but do not limit the patent scope of the present application. The present application can be implemented in many different forms, and conversely, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing specific embodiments or equivalently replace some technical features thereof without departing from the principles and purposes of the present application. The scope of the patent protection of the present application is defined by the claims and their equivalents.

[0084] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, combinations, replacements and variations can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip structure, characterized by The chip structure comprises: a chip substrate for carrying a substrate to be detected; a conductive layer covering a lower surface of the chip substrate; The chip structure further comprises a bracket provided with a receiving groove and an abutting portion located in the receiving groove, the chip substrate is located in the receiving groove, and the conductive layer abuts against the abutting portion. The conductive layer further comprises a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer covers the lower surface of the chip substrate, and the second sub-conductive layer covers the sidewall of the chip substrate and abuts against the sidewall of the receiving groove.

2. The chip structure of claim 1, wherein, The receiving groove comprises a first sub-receiving groove and a second sub-receiving groove, and the abutting portion is located between the first sub-receiving groove and the second sub-receiving groove for separating the first sub-receiving groove and the second sub-receiving groove.

3. The chip structure of claim 1, wherein, The chip structure further comprises a first magnetic attraction member connected to the bottom of the chip substrate or the conductive layer, and a second magnetic attraction member arranged in the receiving groove, the first magnetic attraction member and the second magnetic attraction member are oppositely arranged in the direction from the chip substrate to the receiving groove.

4. The chip structure of claim 1, wherein, The resistance of the conductive layer is 5-10 ohms.

5. The chip structure of claim 1, wherein, The chip structure further comprises a hydrophobic layer and a hydrophilic layer arranged in sequence, and the projection area of the hydrophilic layer on the chip substrate is smaller than the projection area of the hydrophobic layer on the chip substrate.

6. The chip structure of claim 5, wherein, The thickness of the hydrophobic layer is 200-1000 nm; and / or, The thickness of the hydrophilic layer is 200-1000 nm, and / or, The thickness of the conductive layer is 100-300 nm.

7. The chip structure of claim 5, wherein, The hydrophilic layer comprises a plurality of sub-hydrophilic layers, and the plurality of sub-hydrophilic layers are distributed on the hydrophobic layer at equal intervals; The diameter of the sub-hydrophilic layer is 200-500 μm; and / or, The spacing between adjacent sub-hydrophilic layers is 2-10 mm.

8. A mass spectrometry instrument, comprising: The mass spectrometer comprises the chip structure according to any one of claims 1-7.

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