Circuit structure for improving DMS out-of-band rejection performance, filter and duplexer

Abstract

The utility model discloses a circuit structure for improving DMS out-of-band rejection performance, a filter and a duplexer. The circuit structure comprises a DMS structure, a capacitor connected with the DMS structure in parallel and an inductor connected with the DMS structure in series. The DMS structure comprises at least three interdigital transducers, a first reflecting grating and a second reflecting grating, wherein the first reflecting grating and the second reflecting grating are located on the two sides of the interdigital transducers. The suppression effect of a near stop band can be greatly improved under the condition that a transition band keeps enough steepness, and the performance of the filter is improved.

Description

Technical Field

[0001] This utility model belongs to the field of radio frequency filter technology, specifically relating to a circuit structure, filter and duplexer for improving the out-of-band suppression performance of DMS. Background Technology

[0002] Surface acoustic wave (SAW) filters are widely used in the field of communication as bandpass filters. Structurally, they include ladder structure, DMS structure, and hybrid structure that combines the two. However, existing technologies lack optimization for SAW filters using hybrid structures, resulting in insufficient steepness of the transition band in adjacent frequency bands, which affects the out-of-band suppression performance of SAW filters.

[0003] To address the issue of insufficient transition band steepness, patent application CN202311702298.6 (prior reference document) discloses a surface acoustic wave (SAW) filter circuit, filter, and duplexer with a steep transition band. This design optimizes SAW filters employing a hybrid structure, effectively improving the steepness of the transition band and enabling the SAW filter to achieve higher out-of-band suppression performance. Specifically, as... Figure 1 As shown, although the steepness of its transition zone has increased, the near-stopping bands on both sides of the passband have not achieved good suppression; for example... Figure 2 As shown, although it achieves better suppression near the blocking band, it sacrifices some of the steepness of the transition band. Utility Model Content

[0004] To address the aforementioned problems, this invention provides a circuit structure, filter, and duplexer for improving the out-of-band suppression performance of the DMS (Distributed Mode Suppression). It can significantly enhance near-stopband suppression while maintaining a sufficiently steep transition band, thereby improving filter performance.

[0005] The technical solution adopted in this utility model is as follows:

[0006] In the first aspect, this application discloses a circuit structure for improving the out-of-band rejection performance of DMS, comprising: a DMS structure, a capacitor connected in parallel with the DMS structure, and an inductor connected in series with the DMS structure;

[0007] The DMS structure includes at least three interdigital transducers and a first reflective grating and a second reflective grating located on both sides of the interdigital transducers.

[0008] As an optional technical scheme, each of the interdigital transducers comprises a first bus bar, a first interdigital electrode connected with the first bus bar, a second bus bar and a second interdigital electrode connected with the second bus bar, and the first interdigital electrode and the second interdigital electrode are staggered between the first bus bar and the second bus bar.

[0009] As an optional technical scheme, the DMS structure comprises three interdigital transducers, namely a first interdigital transducer, a second interdigital transducer and a third interdigital transducer; the first bus bar of the first interdigital transducer, the first bus bar of the second interdigital transducer and the first bus bar of the third interdigital transducer are connected and then connected with one end of the inductor, and the other end of the inductor is grounded; the second bus bar of the second interdigital transducer is connected with an input terminal Input, and the second bus bar of the first interdigital transducer and the second bus bar of the third interdigital transducer are connected and then connected with an output terminal Output; and the capacitor is connected between the input terminal Input and the output terminal Output.

[0010] As an optional technical scheme, the DMS structure further comprises a fourth interdigital transducer, the second bus bar of the fourth interdigital transducer is connected with the second bus bar of the second interdigital transducer, and the first bus bar of the fourth interdigital transducer is connected with the first bus bar of the second interdigital transducer.

[0011] As an optional technical scheme, the DMS structure further comprises a fifth interdigital transducer, the first bus bar of the fifth interdigital transducer is connected with the first bus bar of the third interdigital transducer, and the second bus bar of the fifth interdigital transducer is connected with the second bus bar of the third interdigital transducer.

[0012] In a second aspect, the application further discloses a filter comprising the circuit structure according to the first aspect.

[0013] In a third aspect, the application further discloses a diplexer comprising the filter according to the second aspect.

[0014] The application has the following beneficial effects: in the application, the inductor is connected in series on the DMS structure, and the capacitor is connected in parallel on the DMS structure, so that the transition band can be greatly suppressed while maintaining sufficient steepness, and the performance of the filter is improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A simulation result schematic diagram of a comparison file.

[0016] Figure 2 Another simulation result schematic diagram of a comparison file.

[0017] Figure 3 The figure is a schematic diagram of the circuit structure for improving the out-of-band rejection performance of the DMS of the embodiment.

[0018] Figure 4 The figure is a schematic diagram of the structure of the interdigital transducer of the embodiment.

[0019] Figure 5 The figure is a schematic diagram of the DMS circuit structure with three interdigital transducers of the embodiment.

[0020] Figure 6 The figure is a schematic diagram of the DMS circuit structure with four interdigital transducers of the embodiment.

[0021] Figure 7 The figure is a schematic diagram of the DMS circuit structure with five interdigital transducers of the embodiment.

[0022] Figure 8 The figure is a schematic diagram of the performance simulation result of the DMS circuit structure. Figure 5 The figure is a schematic diagram of the performance simulation result of the DMS circuit structure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme of the embodiments of the utility model will be described clearly and completely below in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. The components of the embodiments of the utility model described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of the claimed utility model, but only represents selected embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the utility model.

[0024] EMBODIMENT

[0025] As shown in the figure, the embodiment discloses a circuit structure for improving the out-of-band rejection performance of the DMS, comprising: a DMS structure, a capacitor C connected in parallel with the DMS structure and an inductor L connected in series with the DMS structure. Figure 3

[0026] As shown in the figure, Figure 5 , Figure 6 and Figure 7 , the DMS structure comprises at least three interdigital transducers and first and second reflective gratings 6 and 7 located on both sides of the interdigital transducers.

[0027] As an optional implementation, as shown in the figure, Figure 4 ​As shown, each of the interdigital transducers includes a first busbar a, a first interdigital electrode b connected to the first busbar a, a second busbar c, and a second interdigital electrode d connected to the second busbar c. The first interdigital electrode b and the second interdigital electrode d are alternately distributed between the first busbar a and the second busbar c.

[0028] As an optional implementation method, such as Figure 5 As shown, the DMS structure includes three interdigital transducers, namely a first interdigital transducer 1, a second interdigital transducer 2, and a third interdigital transducer 3. The first busbar of the first interdigital transducer 1, the first busbar of the second interdigital transducer 2, and the first busbar of the third interdigital transducer 3 are connected and then connected to one end of the inductor L, and the other end of the inductor L is grounded. The second busbar of the second interdigital transducer 2 is connected to the input terminal Input, and the second busbar of the first interdigital transducer 1 and the second busbar of the third interdigital transducer 3 are connected and then connected to the output terminal Output. The capacitor C is connected between the input terminal Input and the output terminal Output.

[0029] As an optional implementation method, such as Figure 6 As shown, the DMS structure also includes a fourth interdigital transducer 4, the second busbar of the fourth interdigital transducer 4 is connected to the second busbar of the second interdigital transducer 2, and the first busbar of the fourth interdigital transducer 4 is connected to the first busbar of the second interdigital transducer 2.

[0030] As an optional implementation method, such as Figure 7 As shown, the DMS structure also includes a fifth interdigital transducer 5, the first busbar of the fifth interdigital transducer 5 is connected to the first busbar of the third interdigital transducer 3, and the second busbar of the fifth interdigital transducer 5 is connected to the second busbar of the third interdigital transducer 3.

[0031] like Figure 8 As shown, is Figure 5 The diagram shows the simulation results of the circuit structure's performance parameters. The solid line represents the simulation results when capacitor C is 0.15pF and inductor L is 0.3nH; the dashed line represents the simulation results when capacitor C is 0pF and inductor L is 0nH (i.e., the existing DMS structure without capacitors and inductors). As can be seen from the diagram, the circuit structure of this embodiment achieves significant near-stopband suppression without sacrificing kurtosis. On the contrary, kurtosis is simultaneously improved to a certain extent, allowing for further enhancement of the filter's performance.

[0032] In another embodiment, this application also discloses a filter, including the circuit structure described in the above embodiments.

[0033] In another embodiment, the application also discloses a diplexer comprising the filter as described in the above embodiment.

[0034] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application, and any technical solution falling within the defined scope of the claims of the present application falls within the protection scope of the present application.

Claims

1. A circuit structure for improving the out-of-band rejection performance of a DMS, characterized by The circuit structure comprises: a DMS structure, a capacitor connected in parallel with the DMS structure, and an inductor connected in series with the DMS structure; wherein the DMS structure comprises at least three interdigital transducers and first and second reflective gratings located on both sides of the interdigital transducers.

2. The circuit structure for improving the out-of-band rejection performance of a DMS according to claim 1, characterized in that: Each of the interdigital transducers comprises a first bus bar, first interdigital electrodes connected to the first bus bar, a second bus bar, and second interdigital electrodes connected to the second bus bar, the first and second interdigital electrodes being staggered between the first and second bus bars.

3. The circuit structure for improving the out-of-band rejection performance of a DMS according to claim 2, characterized in that: The DMS structure comprises three interdigital transducers, namely a first interdigital transducer, a second interdigital transducer, and a third interdigital transducer; the first bus bar of the first interdigital transducer, the first bus bar of the second interdigital transducer, and the first bus bar of the third interdigital transducer are connected to one end of the inductor, and the other end of the inductor is grounded; the second bus bar of the second interdigital transducer is connected to an input terminal Input, and the second bus bar of the first interdigital transducer and the second bus bar of the third interdigital transducer are connected to an output terminal Output; and the capacitor is connected between the input terminal Input and the output terminal Output.

4. The circuit structure for improving the out-of-band rejection performance of a DMS according to claim 3, characterized in that: The DMS structure further comprises a fourth interdigital transducer, the second bus bar of the fourth interdigital transducer being connected to the second bus bar of the second interdigital transducer, and the first bus bar of the fourth interdigital transducer being connected to the first bus bar of the second interdigital transducer.

5. The circuit structure for improving the out-of-band rejection performance of a DMS according to claim 4, characterized in that: The DMS structure further comprises a fifth interdigital transducer, the first bus bar of the fifth interdigital transducer being connected to the first bus bar of the third interdigital transducer, and the second bus bar of the fifth interdigital transducer being connected to the second bus bar of the third interdigital transducer.

6. A filter characterized by: The circuit structure comprises the circuit structure according to any one of claims 1-5.

7. A diplexer characterized by: The filter comprises the filter according to claim 6.

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