Dual-track D-type power amplifier control circuit

Abstract

The utility model discloses a dual-track class-D power amplifier control circuit, which relates to the technical field of circuit design, and utilizes triodes to increase the active control of an MCU (Microprogrammed Control Unit) on an SDZ (Software Definition Zone) and an FAULTZ, and meanwhile, due to mutual exclusion of signals of MUTE and SDZ pins, the triodes are additionally arranged in the middle to change the level, a pull-up power supply of the MUTE pins and a GVDD (Graphics Voltage Drain Drain Drain) output by a chip are used; the GVDD can delay falling, and the silence function can be maintained; at the moment, the D-type power amplifier chip is in a standby state, and only extremely low static power consumption exists, so that unnecessary power consumption is reduced, and puffing during initialization is avoided.

Description

TECHNICAL FIELD

[0001] The utility model relates to circuit design technical field especially is related to a double sound track class D power amplifier control circuit. BACKGROUND

[0002] The current double sound track class D power amplifier control circuit as shown in the figure: the SDZ pin and the FAULTZ pin of the class D power amplifier chip are connected with pull-up resistance to the power supply, and the METU pin is controlled by MCU through a triode; the SDZ pin is translated as an audio amplifier switch, the FAULTZ pin is translated as a general fault report, and the METU pin is translated as a mute function. Fig. 1-2 When the SDZ pin is detected as a high level, the horn end has an output; the FAULTZ pin is an output pin, and when a fault is detected, a low level is output; the MUTE pin detects a high level, and is quickly disabled.

[0003] In the prior art, the SDZ pin pull-up is always in an open state, and only when a fault or power failure is detected, the FAULTZ output low level, and the audio amplifier switch is closed;

[0004] Therefore, this will cause the function to run without audio output, resulting in unnecessary consumption; at the same time, during power-on and power-off, a pffft sound problem will occur.

[0005] The background description provided herein is for the purpose of generally presenting the context of the disclosure. The subject matter of the background section is not prior art to the present application unless specifically indicated to be prior art and unless otherwise specifically indicated to be prior art to the present application, the contents of this section are not to be interpreted as an admission that the present application is not entitled to antedate such subject matter. SUMMARY

[0006] In view of the above technical problems in the related art, the utility model provides a double sound track class D power amplifier control circuit.

[0007] In the first aspect, the utility model provides a double sound track class D power amplifier control circuit, which comprises a class D power amplifier chip and a control circuit; the class D power amplifier chip has an SDZ pin and a METU pin;

[0008] The control circuit comprises an input end, an output end, two triodes and six resistors, which are a first input end, a first output end, a first triode Q5, a second triode Q6, a first resistor R72, a second resistor R238, a third resistor R224, a fourth resistor R237, a fifth resistor R239 and a sixth resistor R216; the first input end is connected with a first high level enable end; the first output end is connected with the SDZ pin of the class D power amplifier chip;

[0009] The B pole of the first triode Q5 is connected with the first input end through the first resistor R72; the C pole of the first triode Q5 is connected with the first power supply end through the third resistor R224; the E pole of the first triode Q5 is connected with the ground DGND;

[0010] The B pole of the second triode Q6 is connected with the C pole of the first triode through the fourth resistor R237; the B pole of the second triode Q6 is connected with the second power supply end through the sixth resistor R216; the B pole of the second triode Q6 is connected with the B pole of the first triode through the second resistor R238 after being interconnected with the E pole of the second triode Q6 through the fifth resistor; the C pole of the second triode Q6 is also connected with the first output end;

[0011] Specifically, when the audio playing task is initiated, the first input end is high level enabled, the CE pole of the first triode Q5 is turned on, so that the second triode Q6 is in the off mode, at this time, the SDZ pin is pulled high, and the switch of the audio amplifier is in the open state;

[0012] When the audio playing task is stopped, the first input end is low level, the CE pole of the first triode Q5 is turned off, so that the second triode Q6 is in the on mode, at this time, the SDZ pin is pulled low, and the switch of the audio amplifier is in the closed state; the class-D power amplifier chip is in standby state, only a small static power consumption is consumed.

[0013] Specifically, the first high level enable end is output by the CPU_AUD_PACTRL pin of the MCU.

[0014] Specifically, the first power supply end is a 5V power supply; the second power supply end is a 24V power supply.

[0015] Specifically, the control circuit further comprises a second input end, a second output end, a third triode Q7, a seventh resistor R240, an eighth resistor R241 and a ninth resistor R242, and the second output end is connected with the METU pin of the class-D power amplifier chip.

[0016] The B pole of the third triode Q7 is connected with the second input end through the seventh resistor R240; the B pole of the third triode Q7 is connected with the ground DGND after being interconnected with the E pole of the third triode Q7 through the eighth resistor R241; the C pole of the third triode Q7 is connected with the second output end and is also connected with GVDD through the ninth resistor R242; the second input end is connected with the second high level enable end; the second output end is connected with the METU pin of the class-D power amplifier chip; wherein the second input end is connected with the second high level enable end or the second input end is connected with the C pole of the second triode Q6.

[0017] Specifically, when the audio playing task is initiated, the second input end is high level enabled, the B electrode of the third transistor Q7 is at high level, the CE electrode of the third transistor Q7 is turned on, the MUTE pin is pulled low, and the mute function is closed.

[0018] When the audio playing task is stopped, the second input end is low level, the B electrode of the third transistor Q7 is pulled low, the CE electrode of the third transistor Q7 is turned off, the MUTE pin is pulled high, and the mute function is opened.

[0019] Specifically, the second high level enabled end is output by the MUTE_CTRL pin of the MCU.

[0020] Specifically, the first transistor Q5, the second transistor Q6 and the third transistor Q7 are NPN type transistors.

[0021] Specifically, the type of the class D power amplifier chip is AW83118TSR.

[0022] Specifically, the first resistor R72 has a resistance of 1kΩ, the second resistor R238 has a resistance of 10kΩ, the third resistor R224 has a resistance of 10kΩ, the fourth resistor R237 has a resistance of 1kΩ, the fifth resistor R239 has a resistance of 10kΩ, the sixth resistor R216 has a resistance of 100kΩ, the seventh resistor R240 has a resistance of 100kΩ, the eighth resistor R241 has a resistance of 10kΩ, and the ninth resistor R242 has a resistance of 10kΩ.

[0023] The utility model discloses a three-electrode tube is used to increase the active control of MCU to SDZ and FAULTZ, and because the signal of MUTE and SDZ pin is mutually exclusive, so three-electrode tube is added in the middle to change the level, the pull-up power supply of MUTE pin, uses the GVDD of chip output, because the power supply is broken, GVDD will delay drop, can maintain mute function, at this time, the class D power amplifier chip is in standby state, only very small static power consumption is consumed, reduces unnecessary power consumption.

[0024] Further, the control of MCU to SDZ uses two transistors, mainly considering the level state of the selected pin output when the MCU is initialized, to avoid the appearance of pufu sound when initializing.

[0025] Further, the utility model can also control the SDZ and MUTE pins of the power amplifier chip through two IO ports, and the two control paths do not interfere with each other, effectively reducing the power loss of the power amplifier chip when not working, effectively solving the problem of power-on and power-off "pufu", and also avoiding the situation that the power amplifier chip can still be controlled when any one of the two control paths fails. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0027] Fig. 1 The prior art two-channel D-class power amplifier control circuit schematic diagram provided for the embodiments of the present application;

[0028] Fig. 2 The prior art two-channel D-class power amplifier chip provided for the embodiments of the present application;

[0029] Fig. 3 The two-channel D-class power amplifier control circuit schematic diagram provided for the embodiments of the present application;

[0030] Fig. 4 The D-class power amplifier chip of the two-channel D-class power amplifier control circuit provided for the embodiments of the present application;

[0031] Fig. 5 The two-channel D-class power amplifier control circuit schematic diagram provided for another embodiment of the present application; wherein Fig. 5 (a) is the control circuit of SDZ, Fig. 5 (b) is the control circuit of MUTE. DETAILED DESCRIPTION

[0032] The present application can be explained in detail through the following embodiments, and the purpose of the present application is to protect all technical improvements within the scope of the present application. In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. are only corresponding to the drawings of the present application, and are for the convenience of describing the present application and simplifying the description, and are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0033] In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0034] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood to indicate or imply relative importance or imply the number of indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0035] In order to make the technical problems, technical solutions and advantages of the present application clearer, the following will be described in detail in conjunction with the drawings and specific embodiments.

[0036] Embodiment one

[0037] Reference Fig. 3-4 The embodiment provides a kind of double-channel class-D power amplifier control circuit, it includes class-D power amplifier chip and control circuit;

[0038] Reference Fig. 4 , the class-D power amplifier chip has SDZ pin and METU pin;The class-D power amplifier chip also has AMP+ pin and AMP- pin, for connecting loudspeaker end.

[0039] The class-D power amplifier chip model is AW83118TSR.

[0040] Reference Fig. 3 , the control circuit includes an input end, two output ends, three triodes and nine resistors, is first input end, first output end, second output end, first triode Q5, second triode Q6, third triode Q7, first resistance R72, second resistance R238, third resistance R224, fourth resistance R237, fifth resistance R239, sixth resistance R216, seventh resistance R240, eighth resistance R241 And ninth resistance R242;The first input end is connected with first high level enable end;The first output end is connected with the SDZ pin of class-D power amplifier chip, and the second output end is connected with the METU pin of class-D power amplifier chip;

[0041] The first high level enable end is output by the CPU_AUD_PACTRL pin of MCU;

[0042] It can be understood that triode includes three electrodes, B pole (base), E pole (emitter) and C pole (collector).

[0043] The B pole of first triode Q5 is connected with first input end by first resistance R72;The C pole of first triode Q5 is connected with first power supply end by third resistance R224;The E pole of first triode Q5 is connected with ground DGND;

[0044] The first power supply end is a 5V power supply;

[0045] The B electrode of the second triode Q6 is connected with the C electrode of the first triode through the fourth resistor R237; the B electrode of the second triode Q6 is connected with the second power supply end through the sixth resistor R216; the B electrode of the second triode Q6 is connected with the B electrode of the first triode through the second resistor R238 after being interconnected with the E electrode of the second triode Q6 through the fifth resistor; the C electrode of the second triode Q6 is also connected with the first output end;

[0046] The second power supply end is a 24V power supply;

[0047] The B electrode of the third triode Q7 is connected with the C electrode of the second triode Q6 through the seventh resistor R240; the B electrode of the third triode Q7 is connected with the ground DGND after being interconnected with the E electrode of the third triode Q7 through the eighth resistor R241; the C electrode of the third triode Q7 is connected with the second output end and also connected with the GVDD through the ninth resistor R242;

[0048] When the audio playing task is initiated, the CPU_AUD_PACTRL pin outputs a high level to enable, the CE electrode of the first triode Q5 is turned on, so that the second triode Q6 is in the off mode, at this time, the SDZ pin is pulled high, and the switch of the audio amplifier is in the open state; at the same time, the B electrode of the third triode Q7 is in a high level, so that the CE electrode of the third triode Q7 is turned on, the MUTE pin is pulled low, and the mute function is closed; the audio input to the class-D power amplifier chip can be normally output after amplification processing.

[0049] When the audio playing task is stopped, the CPU_AUD_PACTRL pin outputs a low level, the CE electrode of the first triode Q5 is turned off, so that the second triode Q6 is in the on mode, at this time, the SDZ pin is pulled low, and the switch of the audio amplifier is in the closed state; at the same time, the B electrode of the third triode Q7 is pulled low, so that the CE electrode of the third triode Q7 is turned off, the MUTE pin is pulled high, and the mute function is opened; the class-D power amplifier chip is in a standby state, only a very small static power consumption is consumed.

[0050] The first triode Q5, the second triode Q6 and the third triode Q7 are NPN type triodes.

[0051] In the embodiment, the model of the first triode Q5, the second triode Q6 and the third triode Q7 is MMBT8050D.

[0052] The resistance values and types of the first resistor R72, the second resistor R238, the third resistor R224, the fourth resistor R237, the fifth resistor R239, the sixth resistor R216, the seventh resistor R240, the eighth resistor R241 and the ninth resistor R242 are determined according to specific circumstances.

[0053] In the embodiment, the first resistor R72 has a resistance of 1 kΩ, the second resistor R238 has a resistance of 10 kΩ, the third resistor R224 has a resistance of 10 kΩ, the fourth resistor R237 has a resistance of 1 kΩ, the fifth resistor R239 has a resistance of 10 kΩ, the sixth resistor R216 has a resistance of 100 kΩ, the seventh resistor R240 has a resistance of 100 kΩ, the eighth resistor R241 has a resistance of 10 kΩ, and the ninth resistor R242 has a resistance of 10 kΩ.

[0054] In the embodiment, a transistor is used to increase the active control of the MCU on the SDZ and the FAULTZ, and a transistor is additionally used to change the level of the MUTE pin because the signals of the MUTE and the SDZ pins are mutually exclusive, and the pull-up power supply of the MUTE pin uses the GVDD output by the chip. After the power supply is disconnected, the GVDD will be delayed to drop, and the mute function can be maintained. At this time, the class-D power amplifier chip is in a standby state, only a small amount of static power consumption is consumed, and unnecessary power consumption is reduced.

[0055] Further, two transistors are used for the control of the MCU on the SDZ, mainly considering the level state of the selected pin output during the initialization of the MCU to avoid the occurrence of the pufu sound during the initialization. If the selected pin output is a high level during the initialization of the MCU, one transistor can be used.

[0056] Embodiment two

[0057] Reference Fig. 4-5 The embodiment provides a dual-channel class-D power amplifier control circuit which comprises a class-D power amplifier chip and a control circuit.

[0058] Reference Fig. 4 The class-D power amplifier chip has an SDZ pin and a MUTE pin. The class-D power amplifier chip also has an AMP+ pin and an AMP- pin which are used to connect a loudspeaker.

[0059] The model of the class-D power amplifier chip is AW83118TSR.

[0060] Reference Fig. 5 The control circuit comprises two input ends, two output ends, three transistors and nine resistors, namely a first input end, a second input end, a first output end, a second output end, a first transistor Q5, a second transistor Q6, a third transistor Q7, a first resistor R72, a second resistor R238, a third resistor R224, a fourth resistor R237, a fifth resistor R239, a sixth resistor R216, a seventh resistor R240, an eighth resistor R241 and a ninth resistor R242. The first input end is connected with a first high-level enable end. The first output end is connected with the SDZ pin of the class-D power amplifier chip, and the second output end is connected with the MUTE pin of the class-D power amplifier chip.

[0061] The first high level enable end is output by a CPU_AUD_PACTRL pin of an MCU;

[0062] It can be understood that the triode includes three electrodes, namely a B electrode (base), an E electrode (emitter) and a C electrode (collector).

[0063] The B electrode of the first triode Q5 is connected with the first input end through a first resistor R72; the C electrode of the first triode Q5 is connected with the first power supply end through a third resistor R224; and the E electrode of the first triode Q5 is connected with the ground DGND.

[0064] The first power supply end is a 5V power supply;

[0065] The B electrode of the second triode Q6 is connected with the C electrode of the first triode through a fourth resistor R237; the B electrode of the second triode Q6 is connected with the second power supply end through a sixth resistor R216; the B electrode of the second triode Q6 is connected with the B electrode of the first triode through a second resistor R238 after being interconnected with the E electrode of the second triode Q6 through a fifth resistor; and the C electrode of the second triode Q6 is also connected with the first output end;

[0066] The second power supply end is a 24V power supply;

[0067] The B electrode of the third triode Q7 is connected with the second input end through a seventh resistor R240; the B electrode of the third triode Q7 is connected with the ground DGND after being interconnected with the E electrode of the third triode Q7 through an eighth resistor R241; the C electrode of the third triode Q7 is connected with the second output end and also connected with GVDD through a ninth resistor R242; and the second input end is connected with the second high level enable end;

[0068] The second high level enable end is output by a MUTE_CTRL pin of the MCU;

[0069] When the audio playing task is initiated, the CPU_AUD_PACTRL pin outputs a high level enable, the CE electrode of the first triode Q5 is turned on, the second triode Q6 is in an off mode, the SDZ pin is pulled high at this time, the switch of the audio amplifier is in an open state; meanwhile, the MUTE_CTRL pin outputs a high level enable, the B electrode of the third triode Q7 is in a high level, the CE electrode of the third triode Q7 is turned on, the MUTE pin is pulled low, and the mute function is closed; the audio input to the class-D power amplifier chip can be normally output after being amplified.

[0070] When the audio playing task is stopped, the CPU_AUD_PACTRL pin outputs a low level, the CE electrode of the first triode Q5 is turned off, so that the second triode Q6 is in the conduction mode, at this time, the SDZ pin is pulled low, the switch of the audio amplifier is in the closed state; at the same time, the MUTE_CTRL pin outputs a low level, the B electrode of the third triode Q7 is pulled low, so that the CE electrode of the third triode Q7 is turned off, the MUTE pin is pulled high, and the mute function is turned on; the class-D power amplifier chip is in a standby state, and only a small static power consumption is consumed.

[0071] The first triode Q5, the second triode Q6 and the third triode Q7 are NPN type triodes.

[0072] In the embodiment, the model of the first triode Q5, the second triode Q6 and the third triode Q7 is MMBT8050D.

[0073] The resistance values and types of the first resistor R72, the second resistor R238, the third resistor R224, the fourth resistor R237, the fifth resistor R239, the sixth resistor R216, the seventh resistor R240, the eighth resistor R241 and the ninth resistor R242 are determined according to specific conditions.

[0074] In the embodiment, the resistance value of the first resistor R72 is 1 kΩ, the resistance value of the second resistor R238 is 10 kΩ, the resistance value of the third resistor R224 is 10 kΩ, the resistance value of the fourth resistor R237 is 1 kΩ, the resistance value of the fifth resistor R239 is 10 kΩ, the resistance value of the sixth resistor R216 is 100 kΩ, the resistance value of the seventh resistor R240 is 100 kΩ, the resistance value of the eighth resistor R241 is 10 kΩ, and the resistance value of the ninth resistor R242 is 10 kΩ.

[0075] In the embodiment, two NPN triodes are used to increase the active control of the MCU on the SDZ and the FAULTZ, and one NPN triode is used to control the MUTE pin, the pull-up power supply of the MUTE pin uses the GVDD output by the chip, because the power supply is turned off, the GVDD will be delayed to drop, and the mute function can be maintained; at this time, the class-D power amplifier chip is in a standby state, and only a small static power consumption is consumed, thereby reducing unnecessary power consumption.

[0076] Further, two triodes are used for the control of the MCU on the SDZ, mainly considering the level state of the selected pin output by the MCU during initialization, so as to avoid the occurrence of the pufu sound during initialization; if the selected pin output of the MCU is high level during initialization, one triode can be used.

[0077] Further, the example uses two IO ports to control the SDZ and MUTE pins of the power amplifier chip, the two control paths do not interfere with each other, effectively reducing the power loss of the power amplifier chip when not working, effectively solving the power-on and power-off "PUPU" problem, and avoiding the situation that any one of the two control paths fails, and still being able to control the power amplifier chip.

[0078] The part not described in detail of the utility model is the prior art, and for those skilled in the art, apparently, the utility model is not limited to the details of the above exemplary embodiments, and the utility model can be realized in other specific forms without departing from the spirit or basic characteristics of the utility model; therefore, no matter from which point, the embodiments should be regarded as exemplary and non-restrictive, and all changes falling within the meaning and range of equivalent elements are included in the utility model.

Claims

1. A two-channel class-D power amplifier control circuit, characterized by It includes a class D power amplifier chip and a control circuit; The class D power amplifier chip has an SDZ pin and a METU pin; The control circuit includes an input end, an output end, two transistors and six resistors, which are a first input end, a first output end, a first transistor Q5, a second transistor Q6, a first resistor R72, a second resistor R238, a third resistor R224, a fourth resistor R237, a fifth resistor R239 and a sixth resistor R216; the first input end is connected with a first high-level enable end; the first output end is connected with the SDZ pin of the class D power amplifier chip; The B pole of the first transistor Q5 is connected with the first input end through the first resistor R72; the C pole of the first transistor Q5 is connected with a first power supply end through the third resistor R224; the E pole of the first transistor Q5 is connected with the ground DGND; The B pole of the second transistor Q6 is connected with the C pole of the first transistor through the fourth resistor R237; the B pole of the second transistor Q6 is connected with the second power supply end through the sixth resistor R216; the B pole of the second transistor Q6 is connected with the B pole of the first transistor through the fifth resistor and the E pole of the second transistor Q6 after interconnection, and then connected with the first transistor through the second resistor R238; the C pole of the second transistor Q6 is also connected with the first output end.

2. The dual-channel class D power amplifier control circuit according to claim 1, wherein when an audio playing task is initiated, the first input end is high-level enabled, the CE pole of the first transistor Q5 is turned on, the second transistor Q6 is in an off mode, the SDZ pin is pulled high, and the switch of the audio amplifier is in an open state; when the audio playing task is stopped, the first input end is low-level, the CE pole of the first transistor Q5 is turned off, the second transistor Q6 is in an on mode, the SDZ pin is pulled low, the switch of the audio amplifier is in a closed state, and the class D power amplifier chip is in a standby state, only a small static power consumption is consumed.

3. The two-channel class-D power amplifier control circuit of claim 1, wherein, The first high-level enable end is output by the CPU_AUD_PACTRL pin of an MCU.

4. The two-channel class-D power amplifier control circuit of claim 1, wherein, The first power supply end is a 5V power supply, and the second power supply end is a 24V power supply.

5. The dual-channel class D power amplifier control circuit according to claim 1, wherein the control circuit further includes a second input end, a second output end, a third transistor Q7, a seventh resistor R240, an eighth resistor R241 and a ninth resistor R242, and the second output end is connected with the METU pin of the class D power amplifier chip; the B pole of the third transistor Q7 is connected with the second input end through the seventh resistor R240; the B pole of the third transistor Q7 is connected with the E pole of the third transistor Q7 through the eighth resistor R241 after interconnection, and then connected with the ground DGND; the C pole of the third transistor Q7 is connected with the second output end and also connected with GVDD through the ninth resistor R242; the second output end is connected with the METU pin of the class D power amplifier chip; wherein the second input end is connected with a second high-level enable end or the second input end is connected with the C pole of the second transistor Q6.

6. The dual-channel class D power amplifier control circuit according to claim 5, wherein When the audio playing task is initiated, the second input end is high level enabled, the B electrode of the third transistor Q7 is high level, the CE electrode of the third transistor Q7 is turned on, the MUTE pin is pulled low, and the mute function is closed; When the audio playing task is stopped, the second input end is low level, the B electrode of the third transistor Q7 is pulled low, the CE electrode of the third transistor Q7 is turned off, the MUTE pin is pulled high, and the mute function is opened.

7. The two-channel class-D power amplifier control circuit of claim 5, wherein, The second high level enabled end is output by the MUTE_CTRL pin of the MCU.

8. The two-channel class-D power amplifier control circuit of claim 1 or 5, wherein, The first transistor Q5, the second transistor Q6 and the third transistor Q7 are NPN type transistors.

9. The two-channel class-D power amplifier control circuit of claim 1, wherein, The type of the class D power amplifier chip is AW83118TSR.

10. The two-channel class-D power amplifier control circuit of claim 1 or 5, wherein, The first resistor R72 has a resistance of 1 kΩ, the second resistor R238 has a resistance of 10 kΩ, the third resistor R224 has a resistance of 10 kΩ, the fourth resistor R237 has a resistance of 1 kΩ, the fifth resistor R239 has a resistance of 10 kΩ, the sixth resistor R216 has a resistance of 100 kΩ, the seventh resistor R240 has a resistance of 100 kΩ, the eighth resistor R241 has a resistance of 10 kΩ, and the ninth resistor R242 has a resistance of 10 kΩ.

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