Layout structure of CMOS analog switch chip and CMOS analog switch

Abstract

The utility model provides a layout structure of a CMOS analog switch chip and a CMOS analog switch. The layout structure comprises a transmission channel layout area arranged in the middle of the chip, and a control layout area, a logic layout area, an input layout area and an output layout area which surround the transmission channel layout area. The control layout area is used for receiving a control signal; the logic layout area is used for shaping the control signal so as to provide the shaped control signal; the input layout area comprises a first input layout area and a second input layout area; and the transmission channel layout area is configured to connect or disconnect the input layout area and the output layout area based on the shaped control signal. The layout of the chip is optimized, ports (bonding pads) are arranged on the periphery of the chip, the number of the input layout areas is two so as to adapt to different packaging bonding finger positions, and the transmission channel layout area is arranged in the center area of the layout so as to be connected with the input layout areas, the output layout area and the logic layout area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of CMOS integrated circuits, in particular to a layout structure of a CMOS analog switch chip and a CMOS analog switch. BACKGROUND

[0002] An analog switch mainly functions to connect or disconnect a signal. Due to low power consumption, fast speed, no mechanical contact, small size, long service life and other characteristics, the analog switch has been widely used in electronic devices.

[0003] A CMOS analog switch is an analog switch based on complementary metal oxide semiconductor technology, which can achieve high off impedance and low on impedance. Most existing CMOS analog switches adopt a dual in-line package (DIP), but as electronic devices become smaller, and the application scenarios of CMOS analog switches become more and more extensive, the packaging forms of CMOS analog switches become more and more diversified. In order to meet the requirements of different packaging forms, it is usually necessary to develop chips with corresponding layout structures, resulting in a longer development cycle and higher development cost of CMOS analog switches.

[0004] Therefore, developing a CMOS analog switch that meets the requirements of multiple packaging forms while ensuring functionality and reliability is the focus of current industry research and development. CONTENT OF THE INVENTION

[0005] To solve the above problems existing in the prior art, the first aspect of the present application provides a layout structure of a CMOS analog switch chip, which comprises a transmission channel layout area arranged in the middle of the chip, and a control layout area, an output layout area, a logic layout area, an input layout area, a power supply layout area and a ground layout area surrounding the transmission channel layout area; wherein:

[0006] The transmission channel layout area has a first side and a third side opposite along a first direction, and a second side and a fourth side opposite along a second direction; the control layout area is located at the junction of the first side and the fourth side; the output layout area is located at the junction of the second side and the third side;

[0007] The input layout area comprises a first input layout area and a second input layout area electrically connected to each other, wherein the first input layout area is located at the second side and the second input layout area is located at the third side;

[0008] The power supply layout area comprises a first power supply layout area and a second power supply layout area electrically connected to each other, wherein the first power supply layout area is located at the junction of the first side and the second side, and the second power supply layout area is located at the fourth side;

[0009] The ground layout area comprises a first ground layout area and a second ground layout area which are electrically connected to each other, wherein the first ground layout area is located at the first side, and the second ground layout area is located at the intersection of the third side and the fourth side;

[0010] The control layout area is configured to receive a control signal; the logic layout area is configured to shape the control signal to provide a shaped control signal; and the transmission channel layout area is configured to connect or disconnect the input layout area and the output layout area based on the shaped control signal.

[0011] In the foregoing scheme, the layout of the chip is optimized, the ports (pads) are arranged at the four sides of the chip, and two input layout areas are provided to adapt to different package bonding finger positions. The transmission channel layout area is arranged in the central region of the layout to be connected to the input layout area, the output layout area and the logic layout area.

[0012] In the scheme, the ground layout area and the power layout area are both provided as two, so that the chip can be installed in different directions according to the package model during packaging to adapt to different package bonding finger position layouts, avoid crossing of bonding wires, and the signal transmission path of the chip circuit is transmitted along the diagonal direction of the chip, and the signal path is smooth.

[0013] Optionally, the logic layout area comprises a first logic layout area and a second logic layout area which are electrically connected to the control layout area; wherein the first logic layout area is located at the fourth side, and the second logic layout area is located at the second side.

[0014] Optionally, the first logic layout area is located between the control layout area and the second power layout area; and the second logic layout area is located between the first input layout area and the first power layout area.

[0015] Optionally, the control layout area is provided with a control signal pad; and a plurality of inverters are cascaded in the first logic layout area and the second logic layout area, and the input ends of the plurality of inverters are electrically connected to the control signal pad.

[0016] Optionally, the transmission channel layout area is provided with a transmission channel circuit, the transmission channel circuit comprises an NMOS tube and a PMOS tube; one of the first logic layout area and the second logic layout area is configured to control the opening or closing of the NMOS tube, and the other is configured to control the opening or closing of the PMOS tube.

[0017] In the foregoing scheme, by providing two logic layout areas, two inverter chains are formed to shape the control signal respectively, and the shaped signals are used to control the opening or closing of the NMOS tube and the PMOS tube in the transmission channel circuit (i.e. control the opening or closing of the transmission channel), which can reduce the delay time of signal transmission and improve the signal shaping effect.

[0018] Compared with the scheme of using a single logical layout area, the NMOS transistor and the PMOS transistor are respectively controlled by two inverter chains, the width-length ratio of each stage of inverters in the two inverter chains can be adjusted according to the driving capability of the front-stage inverter and the required load capability, so that the optimal inter-stage ratio is achieved to drive the NMOS transistor or the PMOS transistor to be turned on or turned off. Therefore, the delay time can be reduced.

[0019] Optionally, the input layout area is provided with an input pad, the input pad is electrically connected with the input end of the transmission channel circuit; the output layout area is provided with an output pad, the output pad is electrically connected with the output end of the transmission channel circuit.

[0020] Optionally, the CMOS analog switch further comprises a plurality of electrostatic protection layout areas, the electrostatic protection layout areas are optionally adjacent to the control layout area, the input layout area, the output layout area, the power supply layout area, and the ground layout area; and the electrostatic protection layout areas are provided with electrostatic protection structures.

[0021] In the second aspect of the present application, a CMOS analog switch is provided, which comprises a packaging shell and a CMOS analog switch chip packaged in the packaging shell, wherein the CMOS analog switch chip adopts the layout structure according to the technical scheme of the first aspect or any of the optional schemes thereof;

[0022] The pads on the control layout area, the first input layout area, the output layout area, the first ground layout area, and the second power supply layout area are respectively electrically connected with corresponding bonding fingers of the packaging shell, and the second side and the fourth side of the layout structure face the bonding fingers of the packaging shell.

[0023] Alternatively,

[0024] The pads on the control layout area, the second input layout area, the output layout area, the second ground layout area, and the first power supply layout area are respectively electrically connected with corresponding bonding fingers of the packaging shell, and the first side and the third side of the layout structure face the bonding fingers of the packaging shell.

[0025] In the third aspect of the present application, a CMOS analog switch is provided, which comprises a plastic package, a lead frame, and a CMOS analog switch chip, wherein the CMOS analog switch chip adopts the layout structure according to the technical scheme of the first aspect or any of the optional schemes thereof;

[0026] The lead frame comprises a base island and a plurality of pins located at the periphery of the base island, the CMOS analog switch chip is mounted on the base island, and the pads on the control layout area, the first input layout area, the output layout area, the first ground layout area, and the second power supply layout area are respectively electrically connected with corresponding pins; the base island and the CMOS analog switch chip are located in the plastic package, and part of the pins are located in the plastic package and the other part of the pins are located outside the plastic package.

[0027] In summary, the layout of the aforementioned chip can optimize the position and quantity of each layout area in the chip layout, so that the chip can meet the needs of various packaging forms, and avoid the cross winding of bonding wires in the formed CMOS analog switch product, so that the internal electrical signal flows smoothly, thereby ensuring that the product performance meets the requirements. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be described below.

[0029] Figure 1 is a schematic diagram of the CMOS analog switch chip layout structure provided by the embodiments of the present application;

[0030] Figure 2 An embodiment of the connection mode of the chip and the bonding finger in the CMOS analog switch is shown, and in this example, the package is an 8-line ceramic flat package (CSOP);

[0031] Figure 3 An embodiment of the connection mode of the chip and the bonding finger in the CMOS analog switch is shown, and in this example, the package is a 5-line ceramic small outline package (CSOT 23-5);

[0032] Figure 4 An embodiment of the CMOS analog switch chip flip mounting provided by the embodiments is shown;

[0033] Figure 5 The CMOS analog switch chip mounting and its connection mode with the bonding finger when the plastic package SOT23-5 line package is shown.

[0034] Annotations in the figure:

[0035] 100: control layout area;

[0036] 201: first logic layout area, 202: second logic layout area;

[0037] 300: transmission channel layout area;

[0038] 401: first input layout area, 402: second input layout area;

[0039] 500: output layout area;

[0040] 601: first ground layout area, 602: second ground layout area;

[0041] 701: first power layout area, 701: second power layout area;

[0042] 801 to 806: first to eighth electrostatic protection layout regions, respectively;

[0043] 1 to 8: first to eighth bonding fingers, respectively. DETAILED DESCRIPTION

[0044] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout.

[0045] In the specification of the present application, when one component / module / unit is referred to as being relative to other components / modules / units, such as "connected to" other components / modules / units, the one component / module / unit can be directly connected or coupled to other components / modules / units, or there can also be an intervening third component / module / unit; in addition, in the embodiments of the present application, "connection" mainly refers to electrical connection, and "abutment" and "adjacent" refer to two layout regions abutting each other, or two layout regions being directly adjacent to each other and spaced apart by a predetermined distance without including a third layout region therebetween.

[0046] In the prior art, CMOS analog switch chips are mostly in dual in-line package (DIP), and as their application range is becoming more and more extensive, more requirements for their packaging forms are proposed, such as the increasing demand for products in surface mount package forms such as CSOP (Ceramic Small Outline Package) and SOT (Small Outline Transistor) in recent years, and there are problems such as longer development cycle and higher development cost in developing chips suitable for new packaging forms. In view of this, the embodiments of the present application optimize the layout structure of the existing CMOS analog switch chip in order to be suitable for various packaging forms. Specifically, the embodiments of the present application provide a layout structure of a single-channel single-pole single-throw (SPST) analog switch chip, and more specifically, a layout structure of a silicon gate CMOS analog switch chip.

[0047] Figure 1 A schematic diagram of the chip layout structure provided by the embodiments of the present application is shown as follows: Figure 1 As shown in the figure, the layout structure of the chip includes a transmission channel layout region 300 located at the middle position of the layout, and a plurality of other layout regions surrounding the transmission channel layout region 300.

[0048] In this embodiment, the layout area surrounding the transmission channel layout area 300 includes at least: a control layout area 100, a logic layout area, an input layout area, an output layout area 500, a power supply layout area, and a ground layout area. The control layout area 100 is used to receive control signals; the logic layout area is used to shape the control signals to provide shaped control signals; and the transmission channel layout area 300 is used to connect or disconnect the input layout area and the output layout area 500 based on the shaped control signals.

[0049] Considering that the transmission channel layout area 300 is electrically connected to the input layout area, logic layout area, and output layout area 500 respectively, this embodiment sets the transmission channel layout area 300 in the middle area of ​​the layout, and sets the other layout areas electrically connected to it in the edge area of ​​the layout.

[0050] To facilitate the explanation of the positional relationship of the various layouts surrounding the transmission channel layout area 300, this application refers to the various edge regions surrounding the transmission channel layout area 300 as the first side, the second side, the third side, and the fourth side, respectively.

[0051] For example, such as Figure 1 As shown, the chip layout structure is rectangular overall, and the transmission channel layout area 300 is also rectangular. For the four edge regions corresponding to the four sides of the transmission channel layout area 300, the two regions opposite each other along the first direction are respectively denoted as the first side and the third side, and the two regions opposite each other along the second direction are respectively denoted as the second side and the fourth side. Usually, the aforementioned first direction and second direction are orthogonal to each other.

[0052] In another formulation, the aforementioned first to fourth sides are arranged in a clockwise or counterclockwise order around the transmission channel layout area 300.

[0053] Typical, such as Figure 1 As shown, the right side of the transmission channel layout area 300 is designated as the first side, and the left side opposite to the first side along the first direction is designated as the third side; the upper side of the transmission channel layout area 300 is designated as the second side, and the lower side opposite to the second side along the second direction is designated as the fourth side, that is, the first side to the fourth side are arranged in a counterclockwise order.

[0054] The control layout area 100 and the output layout area 500 are set diagonally opposite each other. For example, the control layout area 100 is located at the boundary between the first and fourth sides, i.e. Figure 1 The middle transmission channel layout area 300 is located at the lower right corner; the output layout area 500 is located at the boundary between the second and third sides, i.e. Figure 1 The location is in the upper left corner of the 300 area of ​​the transmission channel layout.

[0055] As aforementioned, the control layout region 100 is configured to receive the control signal, and is provided with a control signal pad (PAD). It is arranged at the edge region of the layout, especially at the corner of the layout, which is conducive to the control signal from the outside.

[0056] The logic layout region is configured to shape the control signal to output the shaped control signal. In a typical embodiment, the logic layout region is provided with a logic circuit structure composed of a plurality of cascaded inverters, i.e. an inverter chain. Figure 1 As shown, the logic layout region includes a first logic layout region 201 and a second logic layout region 202, wherein the first logic layout region 201 is located at the fourth side of the transmission channel layout region 300, and the second logic layout region 202 is located at the second side of the transmission channel layout region 300, i.e. the first logic layout region 201 and the second logic layout region 202 are located at both sides of the transmission channel layout region 300 along the second direction; preferably, they are arranged close to the first side to facilitate electrical connection to the control signal pad in the control layout region 100.

[0057] As described above, a plurality of cascaded inverters are arranged in each of the two logic layout regions, i.e. the first logic layout region 201 and the second logic layout region 202, wherein the input ends of the first-stage inverters are electrically connected to the control signal pad in the control layout region 100, such as through metal wiring, to enable the inverter chain to receive the control signal and shape the control signal.

[0058] The transmission channel layout region 300 is provided with a transmission channel circuit for analog switch transmission level signal, which functions to connect or disconnect the input layout region and the output layout region 500 based on the shaped control signal. The transmission channel circuit has an input end, an output end and a control end, wherein the control end is electrically connected to the output end of the inverter chain to receive the shaped control signal; the input end is electrically connected to the input pad of the input layout region, and the output end is electrically connected to the output pad in the output layout region 500.

[0059] The transmission channel circuit specifically includes NMOS and PMOS. The first logic layout region 201 and the second logic layout region 202 are respectively configured to control the opening or closing of the NMOS and the PMOS. For example, the first logic layout region 201 is configured to control the opening or closing of the NMOS, and the second logic layout region 202 is configured to control the opening or closing of the PMOS.

[0060] Compared with using a single logical layout area, the layout structure provided by the embodiment includes two logical layout areas, and the NMOS transistor and the PMOS transistor are respectively controlled by two inverter chains. In the specific implementation process, the width-length ratio of each inverter in the two inverter chains can be adjusted according to the driving capability of the front-stage inverter and the required load capability, so that the optimal inter-stage ratio is achieved, thereby driving the NMOS transistor or the PMOS transistor to be turned on or turned off, and finally the effect of reducing the delay time is achieved.

[0061] As shown in Figure 1 , the number of input layout areas in the embodiment is two, which are defined as a first input layout area 401 and a second input layout area 402. The sizes of the two input layout areas can be consistent, and they are electrically connected to each other through metal wiring.

[0062] The first input layout area 401 and the second input layout area 402 are respectively located on the two sides of the output layout area 500, for example, the first input layout area 401 is located on the second side of the transmission channel layout area 300, and the second input layout area 402 is located on the third side of the transmission channel layout area 300. The first input layout area 401 and the second input layout area 402 are both provided with an input pad (PAD), or an S-port PAD. The input pad serves as the input end of the analog switch transmission.

[0063] The output layout area 500 is provided with an output pad (PAD), or a D-port PAD. The output pad serves as the output end of the analog switch transmission. In Figure 1 the layout structure shown in the figure, the output layout area 500 is located at the upper left position of the layout, that is, the output layout area 500 is separated from the control layout area 100 by the transmission channel layout area 300; the output layout area 500 is located between the two input layout areas.

[0064] As shown in Figure 1 , the above layout structure further includes a power layout area and a ground layout area necessary for chip operation. In order to adapt to the layout of the bonding finger of different packaging types, the ground layout area and the power layout area are both two, and they are both arranged around the transmission channel layout area 300. Specifically, the ground layout area includes a first ground layout area 601 and a second ground layout area 602; the power layout area includes a first power layout area 701 and a second power layout area 702. Among them, the first ground layout area 601 and the second ground layout area 602 are electrically connected through metal wiring; the first power layout area 701 and the second power layout area 702 are electrically connected through metal wiring.

[0065] In a typical embodiment, as shown in Figure 1As shown, the first grounding layout area 601 is located in the middle right side of the layout, and the second grounding layout area 602 is located in the lower left corner of the chip. In other words, the first grounding layout area 601 is located on the first side of the transmission channel layout area 300, and the second grounding layout area 602 is located at the junction of the third and fourth sides of the transmission channel layout area 300. The second grounding layout area 602 and the first power supply layout area 701 are arranged diagonally opposite each other, and the two are separated by the transmission channel layout area 300.

[0066] In a typical embodiment, such as Figure 1 As shown, the first power supply layout area 701 is located at the upper right corner of the chip, and the second power supply layout area 702 is located at the lower center of the chip. In other words, the first power supply layout area 701 is located at the junction of the first and second sides of the transmission channel layout area 300, and is diagonally positioned opposite the second ground layout area 602; the second power supply layout area 702 is located on the fourth side of the transmission channel layout area 300.

[0067] Compared to existing technologies, the aforementioned embodiments optimize the chip layout structure. The input and output layout areas, as well as the power and ground layout areas, are located around the perimeter of the chip. Furthermore, the layout is arranged according to different package bonding positions, with two input, two power, and two ground layout areas each, and their positions are rationally arranged. The transmission channel layout area is located at the center of the chip to facilitate its connection with other layout areas. Through this layout, the chip can meet the requirements of various packaging forms, such as DIP, CSOP, and SOT.

[0068] In particular, in the preferred embodiment, by setting two logic layout areas, which can be respectively connected to the control layout area 100, the control signals are shaped. The shaped signals are used to control the NMOS and PMOS transistors in the transmission channel layout area to turn on or off (transmission channel turn on or off), which can reduce the signal transmission delay time and improve the signal shaping effect.

[0069] In a preferred embodiment, multiple electrostatic discharge (ESD) protection areas are also included. These ESD protection areas are provided with ESD protection structures, such as ESD protection diode structures, which can be respectively disposed next to each ESD protection area having an input port (pad), an output port, and a power supply and grounding area. Before external ESD stress enters the internal circuit through each port, it can be discharged through the ESD protection structure to protect the internal circuit from ESD damage.

[0070] In an embodiment, such as Figure 1 As shown, the electrostatic protection layout area is optionally adjacent to the control layout area 100, the input layout area, the output layout area 500, the first grounding layout area 601, the second grounding layout area 602, the first power supply layout area 701, and the second power supply layout area 702.

[0071] In a typical embodiment, the whole layout structure includes 6 static protection layout regions in total, wherein the first static protection layout region 801 is arranged between the control layout region 100 and the first ground layout region 601, the second static protection layout region 802 is arranged between the first power layout region 701 and the first ground layout region 601; the third static protection layout region 803 is arranged between the first input layout region 401 and the output layout region 500, the fourth static protection layout region 804 is arranged between the output layout region 500 and the second input layout region 402; the fifth static protection layout region 805 is arranged between the second ground layout region 602 and the second input layout region 402, and the sixth static protection layout region 806 is arranged between the second ground layout region 602 and the second power layout region 702.

[0072] Based on the CMOS analog switch chip adopting the aforementioned layout structure, the present application further provides various embodiments of CMOS analog switch products, each of which includes a CMOS analog switch chip and a packaging structure, wherein the CMOS analog switch chip adopts the layout structure recorded in the aforementioned embodiments. The bonding fingers in the chip and the packaging structure are preferably connected by metal bonding wires.

[0073] In fact, the functions and arrangement sequence of the external lead-out terminals (such as pins, also known as leads) of electronic components and integrated circuits including the analog switch products in the embodiments of the present application are generally determined according to the functions of external circuits, i.e. the functions and arrangement sequence of the external lead-out terminals need to meet general rules. Under the premise that the arrangement of the external lead-out terminals has been determined, the corresponding pads (PADs) on the chip and the bonding fingers are connected, thereby ensuring that the products meet the requirements of different packaging forms for the arrangement sequence and functions of the lead-out terminals.

[0074] In addition, it should be noted that in the following embodiments of the CMOS analog switch products, the CMOS analog switch chip is preferably a bare chip, i.e. a die, or a die.

[0075] First embodiment

[0076] The ceramic flat package CSOP belongs to a surface mount package form, and the package shell therein can be a metal ceramic shell commonly used in ceramic flat packages, which can specifically include a ceramic base, a metal cover plate, and a built-in adapter wafer. The ceramic base is the main body of the package shell and mainly plays a mechanical support role. The material thereof is alumina ceramic, and the content of alumina is preferably not less than 90%. The ceramic base includes a chip bonding area, a bonding area, and a sealing ring, wherein the chip bonding area is used for mounting a chip; the bonding area, the built-in adapter wafer, and the external lead (also referred to as an external lead wire) are interconnection paths of the chip and an external circuit; and the ceramic base is sealingly connected with the metal cover plate through the sealing ring thereof.

[0077] The CMOS analog switch product provided in the embodiment has an 8-line ceramic flat package (CSOP) package form, and a CMOS analog switch chip is mounted in a chip bonding area of a ceramic base. As shown in Figure 2 , the second side and the fourth side in the layout of the CMOS analog switch chip are respectively directed to the bonding fingers on the two sides in the ceramic base. The pads on the control layout area 100, the first input layout area 401, the output layout area 500, the first ground layout area 601, and the second power layout area 702 are respectively electrically connected with the corresponding bonding areas (bonding fingers) through metal bonding wires.

[0078] Second Embodiment

[0079] The CMOS analog switch product provided in the embodiment adopts a 5-line ceramic small outline surface mount package (CSOT 23-5). As shown in Figure 3 , a CMOS analog switch chip is mounted in a ceramic package shell, and the first side and the third side in the layout of the CMOS analog switch chip are respectively directed to the bonding fingers on the two sides in the ceramic base. The pads on the control layout area 100, the second input layout area 402, the output layout area 500, the second ground layout area 602, and the first power layout area 701 are respectively electrically connected with the corresponding bonding fingers. In the embodiment, the functions of the bonding fingers corresponding to the pins are as shown in Table 1.

[0080] Table 1: Functions of the bonding fingers (pins) in the 5-line ceramic small outline surface mount package

[0081]

[0082] Third Embodiment

[0083] The CMOS analog switch product provided in the embodiment adopts a plastic package SOT23-5 line package. The product includes a CMOS analog switch chip, a plastic package body, and a lead frame. The lead frame includes a base island and a plurality of pins located at the periphery of the base island, and the CMOS analog switch chip is mounted on the base island. As shown in Figure 4 , the chip is flipped along the dashed line and the direction of the arrow in the figure, and the flipped chip is as shown in Figure 5As shown in the figure, the pads on the control layout area 100, the first input layout area 401, the output layout area 500, the first ground layout area 601 and the second power layout area 702 are respectively electrically connected with the pins corresponding to the metal bonding wires. In this embodiment, the pin reverse molding process is adopted to process the CMOS analog switch product consistent with the conventional pin arrangement.

[0084] The above merely provides part of the specific embodiments of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the embodiments of the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A layout structure of a CMOS analog switch chip, characterized by, The chip includes a transmission channel layout area (300) arranged in the middle of the layout, and a control layout area (100), an output layout area (500), a logic layout area, an input layout area, a power layout area and a ground layout area surrounding the transmission channel layout area (300); wherein: The transmission channel layout area (300) has a first side and a third side opposite in a first direction, and a second side and a fourth side opposite in a second direction; the control layout area (100) is located at the junction of the first side and the fourth side; the output layout area (500) is located at the junction of the second side and the third side; The input layout area includes a first input layout area (401) and a second input layout area (402) electrically connected to each other, wherein the first input layout area (401) is located at the second side, and the second input layout area (402) is located at the third side; The power layout area includes a first power layout area (701) and a second power layout area (702) electrically connected to each other, wherein the first power layout area (701) is located at the junction of the first side and the second side, and the second power layout area (702) is located at the fourth side; The ground layout area includes a first ground layout area (601) and a second ground layout area (602) electrically connected to each other, wherein the first ground layout area (601) is located at the first side, and the second ground layout area (602) is located at the junction of the third side and the fourth side; The control layout area (100) is used for receiving a control signal; the logic layout area is used for shaping the control signal to provide a shaped control signal; and the transmission channel layout area (300) is configured to make the input layout area and the output layout area (500) communicate or disconnect based on the shaped control signal.

2. The layout structure of claim 1, wherein, The logic layout area includes a first logic layout area (201) and a second logic layout area (202) electrically connected to the control layout area (100) respectively, wherein the first logic layout area (201) is located at the fourth side, and the second logic layout area (202) is located at the second side.

3. The layout structure of claim 2, wherein, The first logic layout area (201) is located between the control layout area (100) and the second power layout area (702); and the second logic layout area (202) is located between the first input layout area (401) and the first power layout area (701).

4. The layout structure of claim 2, wherein, The control layout area (100) is provided with a control signal pad; The first logic layout area (201) and the second logic layout area (202) are each provided with a plurality of inverters in cascade, and the inputs of the plurality of inverters are electrically connected to the control signal pad.

5. The layout structure of claim 2, wherein, The transmission channel layout area (300) is provided with a transmission channel circuit, the transmission channel circuit includes an NMOS tube and a PMOS tube; one of the first logic layout area (201) and the second logic layout area (202) is used for controlling the opening or closing of the NMOS tube, and the other is used for controlling the opening or closing of the PMOS tube.

6. The layout structure of claim 5, wherein, The input layout region is provided with an input pad, which is electrically connected with an input end of the transmission channel circuit; the output layout region (500) is provided with an output pad, which is electrically connected with an output end of the transmission channel circuit.

7. The layout structure according to any one of claims 1 to 6, wherein, A plurality of electrostatic protection layout regions are further included, which are optionally adjacent to the control layout region (100), the input layout region, the output layout region (500), the power supply layout region, and the ground layout region; and an electrostatic protection structure is arranged in the electrostatic protection layout region.

8. A CMOS analog switch characterized by, The CMOS analog switch chip is packaged in the packaging shell, and the CMOS analog switch chip adopts the layout structure according to any one of claims 1 to 7. The pads on the control layout region (100), the first input layout region (401), the output layout region (500), the first ground layout region (601), and the second power supply layout region (702) are respectively electrically connected with corresponding bonding fingers of the packaging shell, and the second side and the fourth side of the layout structure face the bonding fingers of the packaging shell. Or, The pads on the control layout region (100), the second input layout region (402), the output layout region (500), the second ground layout region (602), and the first power supply layout region (701) are respectively electrically connected with corresponding bonding fingers of the packaging shell, and the first side and the third side of the layout structure face the bonding fingers of the packaging shell.

9. A CMOS analog switch characterized by, The CMOS analog switch chip is packaged in the packaging shell, and the CMOS analog switch chip adopts the layout structure according to any one of claims 1 to 7. The lead frame includes a base island and a plurality of pins located at the periphery of the base island, the CMOS analog switch chip is mounted on the base island, and the pads on the control layout region (100), the first input layout region (401), the output layout region (500), the first ground layout region (601), and the second power supply layout region (702) are respectively electrically connected with corresponding pins. The base island and the CMOS analog switch chip are located in the plastic package, and a part of the pins are located in the plastic package, and the other part of the pins are located outside the plastic package.

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