Anti-interference adjustable signal device based on DDS chip

Abstract

An anti-interference adjustable signal device based on DDS chips comprises a main control chip, a DDS chip I and a plurality of DDS chips II, the main control chip is connected with the DDS chip I through an FMC, the main control chip is connected with each DDS chip II through an SPI external interface, and the main control chip is connected with each DDS chip II through an SPI external interface. One end, far away from the main control chip, of the DDS chip II is connected with a low-pass filter through an operational amplifier, the main control chip is connected with a display through an IIC (inter-integrated circuit) interface, the main control chip is connected with an operational key through an I / O (input / output) interface, and a recovery module is further arranged on the upstream of the DDS chip I and used for receiving input signals. Through the mutual cooperation of the main control chip, the DDS chip 1 and the DDS chip 2, any waveform signal can be generated, and the EMC experimental signal testing device is high in signal output frequency stability and precision, rapid in response, low in cost, small in power consumption and easy to operate, and can be applied to the occasion of EMC experimental signal testing.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic technology and electronic instrument field, concretely is a kind of anti-interference adjustable signal device based on DDS chip. BACKGROUND

[0002] Traditional signal generator is generally based on analog technology. It first generates a certain frequency sine signal, and then processes the sine signal to output other waveform signals (for example, square wave signals can be output by comparator, and triangular wave signals can be generated by integrating square wave signals). The key of this technology is how to generate a sine signal of a specific frequency. Early signal generators mostly used resonance method, and later appeared signal generators using phase-locked frequency synthesis technology. However, traditional signal generators based on analog technology can only generate a limited number of regular waveforms such as sine wave, square wave and triangular wave. If complex waveforms are needed, the complexity and design difficulty of the circuit are greatly increased. As an essential excitation source of electronic measurement system, signal source determines the evaluation of the measurement system to a great extent, and is therefore often called the "ruler" of the electronic measurement system. Traditional signal sources are easily disturbed by external electromagnetic signals when outputting voltage and current. Now, signal sources are required to shield external electromagnetic signal interference, be directly used for input of measured equipment in EMC experiments, and have small size, high reliability, flexible operation, easy use and computer control. SUMMARY

[0003] The utility model aims at providing a kind of anti-interference adjustable signal device based on DDS chip to solve the problems raised in the above background technology.

[0004] To achieve the above object, the utility model provides the following technical scheme:

[0005] An anti-interference adjustable signal device based on DDS chip, comprising a main control chip, one DDS chip one and several DDS chip twos, the main control chip and the DDS chip one are connected through FMC, the main control chip and each DDS chip two are connected through SPI external interface, the end of the DDS chip two away from the main control chip is connected with a low-pass filter through an operational amplifier, the main control chip is connected with a display through IIC interface, the main control chip is connected with an operation key through I / O interface, an upstream of the DDS chip one is further provided with a back sampling module, and the back sampling module is used for receiving input signals.

[0006] In a possible implementation, an anti-interference module is further provided downstream of the low-pass filter.

[0007] In a possible implementation, the master control chip is connected with a communication module, the communication module is connected with a host computer, and the communication module is used for signal transmission between the master control chip and the host computer.

[0008] In a possible implementation, the DDS chip two is an AD9851 DDS chip, and the master control chip module comprises an STM32F103 ARM control chip and an FPGA chip.

[0009] In a possible implementation, the FPGA chip comprises a phase accumulator and a waveform table storage module which are sequentially and unidirectionally connected.

[0010] In a possible implementation, the low-pass filter comprises two 470nH inductors and one 820nH inductor, the two 470nH inductors are connected in series, and the 820nH inductor is located in the middle of the two 470nH inductors.

[0011] In a possible implementation, the operational amplifier comprises an operational amplifier control chip and an amplifier, the operational amplifier control chip is connected in series with the positive electrode of the amplifier, the operational amplifier control chip is connected in parallel with a voltage dividing resistor, and the voltage dividing resistor is connected in series with the negative electrode of the amplifier.

[0012] In a possible implementation, the back-drawing module comprises a filter and a shield, and the filter is used for filtering input current signals or voltage signals.

[0013] In a possible implementation, the master control chip is connected with a power supply, and the voltage of the power supply is 220V.

[0014] Compared with the prior art, the utility model has the following advantages:

[0015] Through mutual cooperation of the master control chip, the DDS chip one and the DDS chip two, arbitrary waveform signals can be generated, and the signal output frequency stability is high, the precision is high, the response is fast, the cost is low, the power consumption is small and the operation is easy, and the utility model can be applied to the occasion of EMC experimental signal testing. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is the overall structure schematic view of the utility model;

[0017] Figure 2 It is the circuit diagram of the low-pass filter of the utility model;

[0018] Figure 3 It is the circuit diagram of the operational amplifier of the utility model. DETAILED DESCRIPTION

[0019] In order to further illustrate the technical means and effects taken by the utility model to achieve the predetermined utility model purposes, the specific embodiments, structures, features and effects according to the utility model are described in detail as follows in combination with the drawings and preferred embodiments.

[0020] As shown in Figure 1 A kind of anti-interference adjustable signal device based on DDS chip, including main control chip 1, one DDS chip one 2 and several DDS chip two 3, the main control chip 1 is connected with the DDS chip one 2 by FMC, the main control chip 1 is connected with each described DDS chip two 3 by SPI external interface, the end of the DDS chip two 3 away from the main control chip 1 is connected with low pass filter 5 by operational amplifier 4, the main control chip 1 is connected with display 8 by IIC interface, the main control chip 1 is connected with operating key 9 by I / O interface, upstream of the DDS chip one 2 is also equipped with back sampling module 6, and the back sampling module 6 is used to receive input signal.Wherein, the downstream of the low pass filter 5 is also equipped with anti-interference module 7.

[0021] The main control chip 1 is connected with communication module 10, the communication module 10 is connected with host computer, and the communication module 10 is used for signal transmission between the main control chip 1 and host computer 11.The back sampling module 6 includes filter and shield, and the filter is used to filter input current signal or voltage signal.Low pass filter effectively filters out the noise of DDS chip two 3 output signal by filtering processing to input signal, and outputs to anti-interference module 7, and finally outputs after signal processing by anti-interference module 7.The main control chip 1 is connected with power supply, and the voltage of the power supply 12 is 220V.Power supply 12 is used to power each module and chip in the device.

[0022] In the utility model, the DDS chip one 2 and DDS chip two 3 can adopt AD9851 DDS chip, and the main control chip 1 module includes STM32F103 ARM control chip and FPGA chip.

[0023] Wherein, the FPGA chip contains phase accumulator and waveform table storage module connected in sequence in one direction.

[0024] The DDS chip two 3 output module is controlled by the master control module, and can output sine wave, triangular wave, square wave and other arbitrary waveforms, the anti-interference module 7 is used for receiving the output of the DDS signal output module and making the output variable ratio and isolating the interference source, the communication module 10 is used for communicating the processing module with the host computer 11 of the upper control end, the display 8 and the operation key 9 are used for displaying and adjusting the signal output, the low-pass filter comprises a four-order low-pass filter, and the back sampling module 6 can collect the output voltage and current and compare the output signal with the master control module.

[0025] The master control chip 1 of the utility model can adopt four or six channels for signal transmission, and can support two-way or three-way voltage and current conversion.

[0026] As shown in Figure 2 The low-pass filter comprises two 470nH inductors and an 820nH inductor, the 470nH inductors and the 820nH inductor are connected in series, and the 820nH inductor is located in the middle of the two 470nH inductors. The series connection of two different inductors can more effectively remove high-frequency noise, so that the signal conversion is more stable.

[0027] As shown in Figure 3 The operational amplifier 4 comprises an operational amplifier control chip and an amplifier, the operational amplifier control chip is connected in series with the positive electrode of the amplifier, the operational amplifier control chip is connected in parallel with a voltage dividing resistor, and the voltage dividing resistor is connected in series with the negative electrode of the amplifier. Through the operational amplifier composed of the above operational amplifier circuit, the converted signal can be effectively amplified, and the signal stability is ensured.

[0028] In the utility model, any kind of communication module on the market can be adopted for the communication module, and the type of the communication module is not particularly limited. The communication module only needs to realize data transmission between the host computer and the master control chip.

[0029] The utility model carries out signal output mainly includes the following key steps:

[0030] 1, the generation of initial waveform: the device first receives the information of the sent waveform, and carries out preliminary processing through the master control chip and the DDS chip two, ensures the operability of the output waveform;

[0031] 2, isolate external electromagnetic signal: the output waveform of the DDS chip two is filtered and isolated after the low-pass filter and the anti-interference module, and the stable output value is ensured;

[0032] 3, output signal back sampling: using the collected voltage and current, the DDS chip one compares the voltage and current with the given output, and if there is an error signal source, it can be self-adjusted.

[0033] In the description of the utility model, need understanding is, the orientation or positional relation indicated by the terms "coaxial", "bottom", "one end", "top", "middle", "the other end", "upper", "one side", "top", "inner", "front", "central", "both ends", "left and right", "front and back" and the like is based on the orientation or positional relation shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore can not be understood as limiting the utility model.

[0034] In the utility model, unless another explicit provision and limitation, the terms "installation", "arrangement", "connection", "fixation", "screw connection" and the like should be understood broadly, for example, can be fixed connection, also can be detachable connection, or be integrated;Can be mechanical connection, also can be electrical connection;Can be directly connected, also can be indirectly connected through intermediate medium, can be the communication or mutual action relation of two elements inside two elements, unless another explicit limitation, for the ordinary skill in the art, can understand the specific meaning of the above terms in the utility model according to the specific circumstances.

[0035] The above is only the preferred embodiment of the utility model, and does not limit the utility model in any form, although the utility model has disclosed as above with preferred embodiment, however, is not used to limit the utility model, any person skilled in the art, without departing from the technical scheme range of the utility model, can make a little more change or modification for equivalent embodiment of equivalent change using the technical content disclosed above, but as long as not departing from the technical scheme content of the utility model, according to the technical essence of the utility model, any indirect modification, equivalent change and modification of the above embodiment are still within the range of the technical scheme of the utility model.

Claims

1. A DDS chip-based anti-interference adjustable signal device, characterized in that, The application relates to a signal generator, which comprises a main control chip (1), one DDS chip I (2) and a plurality of DDS chip II (3), the main control chip (1) is connected with the DDS chip I (2) through an FMC, the main control chip (1) is connected with each DDS chip II (3) through an SPI external interface, one end of the DDS chip II (3) away from the main control chip (1) is connected with a low-pass filter (5) through an operational amplifier (4), the main control chip (1) is connected with a display (8) through an IIC interface, the main control chip (1) is connected with an operation key (9) through an I / O interface, the upstream of the DDS chip I (2) is further provided with a back sampling module (6), and the back sampling module (6) is used for receiving an input signal.

2. The DDS chip-based anti-interference adjustable signal device according to claim 1, characterized in that, The low-pass filter (5) is further provided with an anti-interference module (7) downstream.

3. The DDS chip-based anti-jamming adjustable signal device according to claim 1, characterized in that, The main control chip (1) is connected with a communication module (10), the communication module (10) is connected with an upper computer (11), and the communication module (10) is used for signal transmission between the main control chip (1) and the upper computer (11).

4. The DDS chip-based anti-jamming adjustable signal device according to claim 1, characterized in that, The DDS chip II (3) is an AD9851 DDS chip, and the main control chip (1) module comprises an STM32F103 ARM control chip and an FPGA chip.

5. The DDS chip-based anti-jamming adjustable signal device according to claim 4, characterized in that, The FPGA chip comprises a phase accumulator and a waveform table storage module which are sequentially and unidirectionally connected.

6. The DDS chip-based anti-jamming adjustable signal device according to claim 1, characterized in that, The low-pass filter (5) comprises two 470nH inductors and one 820nH inductor, the 470nH inductors and the 820nH inductor are connected in series, and the 820nH inductor is located in the middle of the two 470nH inductors.

7. The DDS chip-based anti-jamming adjustable signal device according to claim 1, characterized in that, The operational amplifier (4) comprises an operational amplifier control chip and an amplifier, the operational amplifier control chip is connected with the positive pole of the amplifier in series, the operational amplifier control chip is connected with a voltage dividing resistor in parallel, and the voltage dividing resistor is connected with the negative pole of the amplifier in series.

8. The DDS chip-based anti-jamming adjustable signal device according to claim 1, characterized in that, The back sampling module (6) comprises a filter and a shield, and the filter is used for filtering input current signals or voltage signals.

9. The DDS chip-based anti-jamming adjustable signal device according to claim 1, characterized in that, The main control chip (1) is connected with a power supply (12), and the voltage of the power supply (12) is 220V.

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