Cell region of semiconductor device and semiconductor device

Abstract

The utility model provides a unit area of a semiconductor device, the semiconductor device and a manufacturing method of the semiconductor device. The apparatus includes: a first cell region stacked on a second cell region; each of the first and second active regions includes a first active region over a second active region; in the first layer of metallization above the first active region, the Mfirst power grid segment has a first reference voltage, and the Mfirst wiring segment is correspondingly aligned with the Mfirst wiring track; and in a first layer of metallization under the second active region, the BMfirst grid segment has a second reference voltage, and the BMfirst wiring segment is correspondingly aligned with the BMfirst wiring trace. The Mfirst wiring segments are aligned in the first and second cell regions, respectively, with a first number (Q1) and a second number (Q2) of Mfirst wiring traces, where Q2lt; q1. The BMfirst wiring segments are aligned in the first and second cell regions corresponding to the third and fourth numbers of BMfirst wiring traces, where Q4lt; and Q3.

Description

TECHNICAL FIELD

[0001] The utility model relates to a unit area of semiconductor device and semiconductor device. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry fabricates a variety of analog and digital devices to solve problems in many different fields. Development of semiconductor process technology nodes has gradually reduced feature sizes and tightened pitches, thereby gradually increasing transistor densities. ICs are becoming smaller and smaller. SUMMARY

[0003] The utility model provides a unit area of semiconductor device, unit area includes: first active region on second active region, first active region has first type dopant, second active region has second type dopant different with first type dopant, in metallized first layer (M first layer) on first active region: M first electric network section, be configured for first reference voltage, and M first wiring section is aligned with first quantity of M first wiring track, and in metallized first layer (BM first layer) under second active region: BM first electric network section, be configured for second reference voltage different with first reference voltage, and BM first wiring section is aligned with second quantity of BM first wiring track, second quantity is less than first quantity.

[0004] In some embodiments, the utility model provides a semiconductor device, include: first unit area, stack on second unit area, first unit area and second unit area each include: first active region with first type dopant and second active region with second type dopant different with first type dopant, in metallized first layer (M first layer) on first active region: M first electric network section, have first reference voltage, and M first wiring section is aligned with M first wiring track correspondingly, and in metallized first layer (BM first layer) under second active region: BM first electric network section, have second reference voltage different with first reference voltage, and BM first wiring section is aligned with BM first wiring track correspondingly, some in M first wiring section in first unit area and second unit area are aligned with first quantity and second quantity of M first wiring track correspondingly, second quantity is less than first quantity, and some in BM first wiring section in first unit area and second unit area are aligned with third quantity and fourth quantity of BM first wiring track correspondingly, fourth quantity is less than third quantity.

[0005] In some embodiments, the utility model provides a kind of method of forming semiconductor device, the method includes: forming active region, active region includes upper active region on corresponding lower active region, the upper active region has first type dopant, the lower active region has second type dopant different from the first type dopant, the active region includes: first upper active region corresponding to first lower active region, the first upper active region represents first unit area with the first lower active region;And second upper active region corresponding to second lower active region, the second upper active region represents second unit area with the second lower active region;And form first conductor in the first layer (M_ first layer) of metallization on corresponding the upper active region, the first conductor includes: first M_ first power grid segment and second M_ first power grid segment, on corresponding the first unit area and the second unit area and be configured for first reference voltage;First M_ first wiring segment is located on the first unit area, with the first quantity of M_ first wiring track is correspondingly aligned, and be configured for corresponding wiring signal;And second M_ first wiring segment is located on the second unit area, with the second quantity of the M_ first wiring track is correspondingly aligned, and be configured for corresponding wiring signal, the second quantity is less than the first quantity;And second conductor is formed in the first layer (BM_ first layer) of metallization under corresponding the lower active region, the second conductor includes: first BM_ first power grid segment and second BM_ first power grid segment, under corresponding the first unit area and the second unit area, and be configured for second reference voltage different from the first reference voltage;First BM_ first wiring segment is located under the first unit area, with the third quantity of BM_ first wiring track is correspondingly aligned, and be configured for corresponding wiring signal;And second BM_ first wiring segment is located under the second unit area, with the fourth quantity of the BM_ first wiring track is correspondingly aligned, and be configured for corresponding wiring signal, the fourth quantity is less than the third quantity.

[0006] To make the above features and advantages of the utility model more obvious and easy to understand, the following specific examples are described in detail below with the help of the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] One or more embodiments are illustrated by way of example in the drawings and are not limited to what is described in the specification. Unless otherwise disclosed, the drawings are not drawn to scale.

[0008] FIG. 1A is the layout diagram of the device according to some embodiments.

[0009] FIG. 1Bis a side view of a device according to some embodiments.

[0010] FIGS. 1C-1E is a corresponding floorplan of a corresponding device according to some embodiments.

[0011] FIGS. 2A-2B is a corresponding cross-sectional view of a device according to some embodiments.

[0012] FIG. 2C is a three-quarter perspective view of a device according to some embodiments.

[0013] FIG. 2D is a cross-sectional view of a device according to some embodiments.

[0014] FIGS. 3A-3B and FIGS. 4A-4B is a corresponding floorplan of a corresponding device according to some embodiments.

[0015] FIGS. 4C-4D is a corresponding floorplan and layout of a device according to some embodiments.

[0016] FIGS. 5A-5B is a corresponding circuit diagram according to some embodiments.

[0017] FIGS. 5C-5F is a corresponding floorplan of a corresponding device according to some embodiments.

[0018] FIG. 6 and FIGS. 7A-7B is a flowchart of a corresponding manufacturing method of a memory device according to some embodiments.

[0019] FIG. 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0020] FIG. 9 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith according to some embodiments. DETAILED DESCRIPTION

[0021] The following embodiments of the present application disclose many different embodiments or examples for implementing different features of the subject matter. The following description of examples of components, materials, values, steps, operations, arrangements, or the like is to simplify the present application embodiments. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like can be contemplated. For example, in the following description, forming a first feature on or over a second feature includes embodiments in which the first and second features are formed in direct contact, and also includes embodiments in which an additional feature is formed between the first and second features, such that the first and second features are in indirect contact. In addition, the present application embodiments repeat reference numerals and / or letters in various examples and / or throughout the specification. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0022] In addition, for the purpose of convenience and brevity, spatially relative terms, such as "below", "under", "lower", "above", "upper" and the like, can be used herein for describing a relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device is otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In some embodiments, the term "standard cell structure" refers to a standardized building block included in various libraries of standard cell structures. In some embodiments, various standard cell structures selected from their libraries are used as components in layout diagrams representing circuits.

[0023] In some embodiments, a device includes: a first cell region stacked on a second cell region; each of the first and second cell regions includes a first active region over a second active region, the first active region has a first type of dopant, the second active region has a second type of dopant different from the first type of dopant; in a first layer of metallization (M_first layer) over the first active region, a M_first power grid (PG) segment has a first reference voltage and a M_first routing segment is correspondingly aligned with a M_first routing trace; while in a first layer of back metallization (BM_first layer) under the second active region, a BM_first PG segment has a second reference voltage different from the first reference voltage, and a BM_first routing segment is correspondingly aligned with a BM_first routing trace. The M_first routing segment is correspondingly aligned with a first (Q1) and a second (Q2) number of the M_first routing traces in the first and second cell regions, where Q2 < Q1. The BM_first routing segment is correspondingly aligned with a third (Q3) and a fourth (Q4) number of the BM_first routing traces in the first and second cell regions, where Q4 < Q3.

[0024] The second other method alleviates the problem of the first other method suffering from a lack of M0_rte routing resources. The second other method alleviates this problem by using extreme ultraviolet (EUV) lithography to form M0_rte and BM_rte segments that are taller than the higher M0_rte and BM_rte segments formed from 193i lithography according to the first other method. As part of developing one or more existing embodiments, the present inventor: recognized in empirical data that the cell area produced using the second other method is less efficient in using the backside BM_first routing segments (discussed below); recognized that if the frontside M_first routing segments were supplemented with more efficient use of the backside BM_first routing segments, then less of the BM_first routing segments would be needed to alleviate the second lack of M_first routing resources, which would otherwise be consumed according to the second other method; recognized that the BM_first routing segments with higher height could be reintroduced because less of the BM_first routing segments would be needed due to the more efficient use of the BM_first routing segments; recognized that the reintroduced BM_first routing segments with higher height could be produced using 193i lithography, which would reduce the number of EUV lithography masks needed according to the second other method; recognized that reducing the number of EUV lithography masks used would reduce costs compared to the second other method; and recognized that the lower cost cell area with the taller BM_first routing segments produced through the use of 193i lithography masks (i.e., produced through the use of fewer EUV lithography masks) would still produce a cell area that alleviates the second lack of M_first routing resources at least as effectively as the second other method.

[0025] Thus, at least some of the present embodiments: use backside BM_first routing segments to supplement frontside M_first routing segments, alleviate the second lack of M_first routing resources despite being more efficient compared to the second other method despite using fewer BM_first routing segments compared to the second other method; use BM_first routing segments with higher height compared to the second other method in view of the fact that fewer BM_first routing segments are needed due to the more efficient use of the BM_first routing segments; use 193i lithography to produce the BM_first routing segments with higher height, which reduces the number of EUV lithography masks that would otherwise be needed compared to the second other method; reduce costs compared to the second other method because fewer EUV lithography masks are used compared to the number of EUV masks used by the second other method; and alleviate at least one or more problems at least as effectively as the second other method despite the lower cost cell area using BM_first routing segments with higher height compared to the second other method.

[0026] In some embodiments, for a first cell region, the third number of aligned BM_first wiring traces is less than the first number of aligned M_first wiring traces. In some embodiments, for a second cell region, the fourth number of aligned BM_first wiring traces is less than the second number of aligned M_first wiring traces.

[0027] In some embodiments, the unit region (of the device) includes: a first active region above a second active region; in a metallized first layer (M_first layer) above the first active region, an M_first grid (PG) segment is configured for a first reference voltage, and an M_first wiring segment is aligned with a first number of M_first wiring traces; in a metallized first layer (BM_first layer) below the second active region, a BM_first PG segment is configured for a second reference voltage, the second reference voltage being different from the first reference voltage, and a BM_first wiring segment is aligned with a second number of BM_first wiring traces, the second number being less than the first number.

[0028] FIG. 1A This is a layout diagram of device 100A according to some embodiments. FIG. 1B This is a side view of the device 100A according to some embodiments.

[0029] FIG. 1A A layout diagram represents a device, such as a semiconductor device. The structures within a device are represented by patterns (also called shapes) in the layout diagram. To simplify the discussion, FIG. 1A Components in the layout diagram (and other layout diagrams disclosed herein) will be referred to as structures rather than patterns. For example, in FIG. 1A Pattern 126(1) in the diagram represents the M0 wiring segment. In the following discussion, component 126(1) is referred to as M0 wiring segment 126(1) rather than M0 wiring pattern 126(1).

[0030] exist FIG. 1A In the layout diagrams disclosed herein, an orthogonal Cartesian coordinate system is assumed, where a first direction is parallel to the X-axis, a second direction is parallel to the Y-axis, and a third direction is parallel to the Z-axis. The layout diagram itself is a top view. The shapes in the layout diagram are two-dimensional relative to, for example, the X-axis and Y-axis, while the device represented is three-dimensional. Therefore, the shapes in such layout diagrams are described as having a width relative to the X-axis and a height relative to the Y-axis. Relative to the Z-axis, the front side of the device represented in the layout diagram is stacked on the back side of the device. In some embodiments, the first to third third directions correspond to directions other than the X-axis, Y-axis, and Z-axis.

[0031] In general, the devices are organized as a stack of layers with respect to the Z-axis, where a layer is located in a corresponding structure, i.e., belongs to a corresponding structure. More specifically, each shape in the layout represents a component in a corresponding layer of a corresponding device. Also, in general, the layout represents the relative depth, i.e., position along the Z-axis, of a shape and a corresponding layer by superimposing a second shape on a first shape such that the second shape at least partially overlaps the first shape. For some structures, the stack is along the Z-axis in the layout; however, to simplify the illustration, the order of the stack along the Z-axis is distorted in some respects with respect to the corresponding devices. Examples of the order of the stack being distorted to simplify the illustration include FIGS. 3A-3B , FIG. 4B , FIG. 4D , FIG. 5B and FIG. 5D .

[0032] In FIG. 1A , the section line IIA-IIA’ and the section line IIB-IIB’ both extend parallel to the Y-axis. The section line IIA-IIA’ corresponds to a cross-sectional view of FIG. 2A . The section line IIB-IIB’ corresponds to a cross-sectional view of FIG. 2B .

[0033] The amount of detail represented by a layout varies. In some cases, selected layers in a layout are combined / simplified into a single layer, e.g., for simplicity. Alternatively, and / or additionally, in some cases, all layers of a non-corresponding semiconductor component are represented, i.e., selected layers in a layout are omitted, e.g., for simplicity of illustration. Alternatively, and / or additionally, in some cases, all components of a given depicted layer of a non-corresponding semiconductor component are represented, i.e., selected components of a given depicted layer of a layout are omitted, e.g., for simplicity of illustration. FIG. 1B and other layouts disclosed herein are examples of layouts in which selected layers and / or selected components of a given layer depicted have been omitted. In some embodiments, FIG. 1B the layout of

[0034] The device 100A is an example of a complementary field-effect transistor (CFET) architecture FIGS. 2A-2C . To simplify the representation of layers in the CFET architecture, FIG. 1A the layout of FIGS. 2A-2B). Region 118 represents a first layer of metallization (M_first layer) above the CFET feature layer 120. Region 122 represents a first layer of metallization (BM_first layer) below the CFET feature layer 120. In some embodiments, the term BM_first layer is understood as "buried M_first layer".

[0035] FIG. 1B A simple summary representation of the relative relationship of the M_first layer 118, the CFET layer 120, and the BM_first layer 122 with respect to the Z-axis is provided. In FIG. 1B , the M_first layer 118 is stacked above the CFET layer 120, and the CFET layer 120 is stacked on the BM_first layer 122.

[0036] In FIG. 1B , a reference line 123 extending parallel to the X-axis substantially bisects the CFET layer 120 of the apparatus 100A with respect to the Y-axis. The region above the reference line 123 is referred to as a front side 139F_1B. The region below the reference line 123 is referred to as a back side (or rear side) 139R_1B.

[0037] Returning to the discussion of FIG. 1A , and more generally for the present utility model embodiments, assume the numbering convention as follows: the M_first layer 118 of the front side 139F_1B is layer zero, i.e., the M_first layer 118 is referred to as the MET0 layer; the first layer of interconnect above the MET0 layer is referred to as the VIA0 layer (not shown); the BM_first layer 122 of the back side 139R_1B is referred to as the BMET0 layer; the first layer of interconnect below the BMET0 layer is referred to as the BVIA0 layer (not shown). In some embodiments, according to the numbering convention of the respective process node at which the apparatus is manufactured, the first layer is layer one, i.e., the first layer of metallization is MET1, the first layer of interconnect above the MET1 layer is referred to as the VIA1 layer, the first layer of metallization below the ARN 112(1) is referred to as the BMET1 layer, and the first layer of interconnect below the BMET0 layer is referred to as the BVIA1 layer.

[0038] Device 100A includes cell regions 102(1) and 110(1). Each of cell regions 102(1) and 110(1) has a width relative to the X-axis and a height relative to the Y-axis, respectively. Cell region 102(1) has a height h_102(1) that is greater than a height h_110(1) of cell region 110(1). Relative to the Y-axis, cell region 102(1) is taller than cell region 110(1), and cell region 110(1) is shorter than cell region 102(1). Thus, in some embodiments, cell region 102(1) is described as a tall cell region, and cell region 110(1) is described as a short cell region. In such embodiments, tall cell region 102(1) is described as being in a tall row 184, and short cell region 110(1) is described as being in a short row 186, where each of rows 184 and 186 extends parallel to the X-axis.

[0039] Cell region 102(1) includes: a portion 104 in M_first layer 118; a portion 106 in CFET layer 120; and a portion 108 in BM_first layer 122. Cell region 110(1) includes: a portion 112 in M_first layer 118; a portion 114 in CFET layer 120; and a portion 116 in BM_first layer 122.

[0040] Portion 106 of cell region 102(1) includes an active region (AR) stack 131 and a CMG / CBMG shape 133(1). In some embodiments, CMG is an abbreviation for cut-MG, where MG is an abbreviation for metal-to-gate FIG. 2B ). In some embodiments, CBMG is an abbreviation for cut-BMG, where BMG is an abbreviation for buried-metal-to-gate FIG. 2B ). Each of AR stack 131 and CMG / CBMG shape 133(1) has a width relative to the X-axis and a height relative to the Y-axis, respectively.

[0041] Portion 114 of cell region 110(1) includes an AR stack 132 and a CMG / CBMG shape 133(2). Each of AR stack 132 and CMG / CBMG shape 133(2) has a width relative to the X-axis and a height relative to the Y-axis, respectively. AR stack 131 has a height that is greater than a height of AR stack 132.

[0042] AR stack 131 includes a front-side active region ARD 1240(2) FIGS. 2A-2B), and a back-side active region ARD2 242(2) having a second type of dopant different from the first type of dopant. In some embodiments, the active region ARD2 is composed of a stack of one or more nanosheets. In some embodiments, the active region ARD1 is composed of a stack of one or more nanosheets. In some embodiments, the first type of dopant is a P-type dopant for positive-channel metal-oxide semiconductor (PMOS) transistor technology, and the second type of dopant is an N-type dopant for negative-channel metal-oxide semiconductor (NMOS) transistor technology. In some embodiments, the first type of dopant is an N-type dopant, and the second type of dopant is a P-type dopant.

[0043] exist FIG. 1A In the above, AR stack 131 has a height h_stk_131. AR stack 132 has a height h_stk_132. The height of AR stack 132 is less than the height of AR stack 131, making h_stk_132... <h_stk_131。

[0044] A portion 104 of unit region 102(1) includes M0 segments 124(1), 126(1), 126(2), and 126(3) in the M_first layer 118 extending parallel to the X-axis. A portion 112 of unit region 110(1) includes M0 segments 124(2), 126(4), and 126(5) in the M_first layer 118 extending parallel to the X-axis.

[0045] Segments M0 124(1) and 124(2) are portions of the corresponding track in the power grid (PG) of device 100A, and are referred to as M0_PG segments 124(1) and 124(2), which are configured to carry / conduct a first reference voltage Vref1 suitable for a first type of dopant. In some embodiments where the first type of dopant is a P-type dopant, the first reference voltage Vref1 is VSS. In some embodiments where the first type of dopant is an N-type dopant, the first reference voltage Vref1 is VDD.

[0046] M0 segments 126(1)-126(5) are wiring segments that form part of the signal path and are therefore configured to carry / conduct the corresponding wiring signals of the circuits implemented by units 102(1) and 110(1). Examples of wiring signals include input / output (I / O) signals, data signals, control signals, or the like. M0 segments 126(1)-126(5) are referred to as M0_rte segments 126(1)-126(5).

[0047] The MET0 layer 118 is organized according to a first grid that includes reference lines (a-tracks) a1-a5 that extend parallel to the X-axis. The M0 segments 126(1)-126(5) are aligned with the corresponding a-tracks a1-a5. In some embodiments, the M0_PG segments 124(1)-124(2) are aligned with additional instances of a-tracks (not shown). In some embodiments, the M0_PG segments 124(1)-124(2) are aligned with reference lines other than a-tracks.

[0048] The M0_rte segments of the cell 102(1) are aligned with a number of a-tracks, Σ(M0_rte_102(1)), where FIG. 1A Assume that Σ(M0_rte_102(1)) = 3. That is, the M0_rte segments 126(1)-126(3) are aligned with the a-tracks a1-a3. The M0_rte segments of the cell 110(1) are aligned with a number of a-tracks, Σ(M0_rte_110(1)), where FIG. 1A Assume that Σ(M0_rte_110(1)) = 2. That is, the M0_rte segments 126(4)-126(5) are aligned with the a-tracks a4-a5.

[0049] In some embodiments, the cell 102(1) and / or the cell 110(1) include a different number of M0_rte segments. In some embodiments, the M0_rte segments of the cell 102(1) are aligned with a different number of a-tracks. In some embodiments, the M0_rte segments of the cell 110(1) are aligned with a different number of a-tracks.

[0050] The portion 108 of the cell 102(1) includes the BM0 segments 128(1), 130(1), and 130(2) in the BM_first layer 122 that extends parallel to the X-axis. The portion 116 of the cell 110(1) includes the BM0 segments 128(2) and 130(3) in the BM_first layer 122 that extends parallel to the X-axis.

[0051] The BM0 segments 128(1) and 128(2) are portions of corresponding tracks in the power grid of the apparatus 100A and are referred to as BM0_PG segments 128(1) and 128(2) that are configured to carry / conduct a second reference voltage Vref2 that is different from the first reference voltage Vref1, which is suitable for a second type of dopant. In some embodiments in which the second type of dopant is N-type dopant, the second reference voltage Vref2 is VDD. In some embodiments in which the first dopant is P-type dopant, the second reference voltage Vref2 is VSS.

[0052] BM0 segments 130(1)-130(3) are wire segments that form part of a signal path, and are thus configured to carry / conduct respective I / O, data, or control signals for circuitry implemented by the respective cells 102(1) and 110(1). BM0 segments 130(1)-130(3) are referred to as BM0 rte segments 130(1)-130(3).

[0053] BMET0 layer 122 is organized according to a second grid, where the second grid includes beta reference lines (beta tracks) β1-β3 that extend parallel to the X axis. BM0 segments 130(1)-130(2) are aligned with beta tracks β1-β2. In some embodiments, BM0 PG segments 128(1)-128(2) are aligned with additional instances of beta tracks (not shown). In some embodiments, BM0 PG segments 128(1)-128(2) are aligned with reference lines other than beta tracks.

[0054] BM0 rte segments of cell 102(1) are aligned with a number of beta tracks Σ(BM0 rte 102(1)), where FIG. 1A Assume Σ(BM0 rte 102(1)) = 2. That is, BM0 rte segments 130(1)-130(2) are aligned with beta tracks β1-β2. For cell region 102(1), the number of aligned beta tracks is less than the number of aligned alpha tracks, such that Σ(BM0 rte 102(1)) < Σ(M0 rte 102(1)). BM0 rte segments of cell 110(1) are aligned with a number of beta tracks Σ(BM0 rte 110(1)), where FIG. 1A Assume Σ(BM0 rte 110(1)) = 1. That is, BM0 rte segment 130(3) is aligned with beta track β3. For cell region 110(1), the number of aligned beta tracks is less than the number of aligned alpha tracks, such that Σ(BM0 rte 110(1)) < Σ(M0 rte 110(1)).

[0055] In some embodiments, where each of cells 102(1) and 110(1) is an example of a more general cell, the number of aligned beta tracks in the general cell is less than the number of aligned alpha tracks in the general cell, such that Σ(grnrl BM0 rte 110(1)) < Σ(gnrl M0 rte 110(1)).

[0056] In some embodiments, the unit 102(1) and / or the unit 110(1) contain different numbers of BM0_rte segments. In some embodiments, the BM0_rte segments of the unit 102(1) are aligned with different numbers of beta tracks. In some embodiments, the BM0_rte segments of the unit 110(1) are aligned with different numbers of beta tracks.

[0057] In FIG. 1A regard to the MET0 layer 118, each of the M0_rte segments 126(1)-126(5) has a height h_M0_rte. The M0_rte segments 126(1)-126(5) have a pitch p_M0_rte with respect to the Y axis. Each of the M0_PG segments 124(1)-124(2) has a height h_M0_PG. Each of the M0_rte segments 126(1)-126(5) is separated from an adjacent M0_rte segment by a gap having a height h_gap_M0_rte, such that h_gap_M0_rte = p_M0_rte - h_M0_rte. In some embodiments, each of the M0_rte segments 126(1)-126(5) is separated from an adjacent M0_PG segment by a gap having a height h_gap_M0_rte.

[0058] In regard to the BMET0 layer 122, each of the BM0_rte segments 130(1)-130(3) has a height h_BM0_rte. The BM0_rte segments 130(1)-130(3) have a pitch p_BM0_rte with respect to the Y axis. Each of the BM0_PG segments 128(1)-128(2) has a height h_BM0_PG. Each of the BM0_rte segments 130(1)-130(3) is separated from an adjacent BM0_rte segment by a gap having a height h_gap_BM0_rte, such that h_gap_BM0_rte = p_BM0_rte - h_BM0_rte. In some embodiments, each of the BM0_rte segments 130(1)-130(3) is separated from an adjacent BM0_PG segment by a gap having a height h_gap_BM0_rte.

[0059] With respect to the Y axis: the alpha tracks have a pitch P_α, where P_α = p_M0_rte; the beta tracks have a pitch P_β, where P_β = p_BM0_rte.

[0060] Unit 102(1) has a height h_102(1). Unit 110(1) has a height h_110(1). In some embodiments, each of units 102(1) and 110(1) is an example of a more general unit that has a height h_gnrl_cell = h_BM0_PG + (k * h_BM0_rte) + ((k + 1) * h_gap_BM0_rte), where k is a positive integer.

[0061] Regarding unit 102(1), k = 2, such that unit 102(1) has a height h_102(1) = h_BM0_PG + (2 * h_BM0_rte) + ((2 + 1) * h_gap_BM0_rte). In some embodiments, the height of unit 102(1) ranges from (≈95nm) ≤ h_102(1) ≤ (≈125nm).

[0062] Regarding unit 110(1), k = 1, such that unit 110(1) has a height h_110(1) = h_BM0_PG + h_BM0_rte + ((1 + 1) * h_gap_BM0_rte). In some embodiments, the height of unit 110(1) ranges from (≈65nm) ≤ h_110(1) ≤ (≈87nm).

[0063] In FIG. 1A it, the BM0_rte segment is higher than the M0_rte segment, such that h_M0_rte < h_BM0_rte. The pitch of the BM0_rte segment is greater than the pitch of the M0_rte segment, such that p_M0_rte < p_BM0_rte. The gap height between adjacent BM0_rte segments is greater than the gap height between adjacent M0_rte segments, such that the height h_gap_M0_rte < h_gap_BM0_rte. In some embodiments, the BM0_PG segment is approximately the same height as the M0_PG segment, thus h_BM0_PG ≈ h_M0_PG. In some embodiments, the BM0_PG segment is shorter than the M0_PG segment, such that h_BM0_PG < h_M0_PG.

[0064] For a first given cell region, it has a CFET architecture and is oriented similarly to the coordinate-orthogonal Cartesian coordinate system assumed by the present embodiment, and in the context of forming M0 rte and BM rte segments using 193 nm immersion (193i) photolithography (also known as deep UV photolithography), a reduction in height (relative to the Y-axis) of the first given cell region results in fewer M0 rte segments being available, which results in a first lack of M0 rte routing resources, a first problem. A first other approach alleviates the first lack of M0 rte routing resources by supplementing the front-side M0 rte segments with back-side BM0 rte segments. Although supplementing the front-side M0 rte segments with back-side BM0 rte segments alleviates the first lack of M0 rte routing resources, it also results in a reduction in height (relative to the Y-axis) of the first given cell region again resulting in fewer M0 rte segments being available, which results in a second lack of M0 rte routing resources, a second problem.

[0065] A second other approach alleviates the second lack of M0 rte routing resources by forming the M0 rte and BM rte segments using extreme ultraviolet (EUV) photolithography instead of 193i photolithography. EUV photolithography is more advanced than 193i photolithography, e.g., in terms of resolution, so the M0 rte and BM rte segments generated by EUV photolithography are (among other things) smaller in height relative to the Y-axis than those generated by 193i photolithography. However, EUV photolithography is not only more advanced than 193i photolithography, EUV photolithography is also more expensive than 193i photolithography.

[0066] As part of developing one or more of the present embodiments, the present inventor: recognized that, in empirical data, at least about 23% of the cell area produced according to the second other method was underutilized with respect to the use of BM0_rte segments, e.g., where a BM0_rte segment aligned with a single beta track, it was sufficient to use two BM0_rte segments aligned with the beta track; recognized that if the backside BM0_rte segments were more efficiently utilized to supplement the frontside M0_rte segments, then fewer BM0_rte segments would be sufficient to alleviate the second deficiency of M0_rte routing resources for at least about 23% of the cell area in the empirical data based on the second other method; recognized that BM0_rte segments with higher heights could be reintroduced because, due to the more efficient utilization of the BM0_rte segments, fewer BM0_rte segments would be needed; recognized that the reintroduced BM0_rte segments with higher heights could be produced using 193i lithography, which would reduce the number of EUV lithography masks needed according to the second other method; recognized that reducing the number of EUV lithography masks used would reduce costs compared to the second other method; and recognized that a lower cost cell area with higher BM0_rte segments produced by using 193i lithography masks, i.e., produced by using fewer EUV lithography masks, would produce a cell area that alleviates the second deficiency of M0_rte routing resources at least as effectively as the second other method.

[0067] Thus, at least some of the present embodiments: supplement the frontside M0_rte segments with backside BM0_rte segments, alleviate the second deficiency of M0_rte routing resources despite being more efficient compared to the second other method, despite using fewer BM0_rte segments compared to the second other method; use BM0_rte segments with higher heights compared to the second other method in view of the fewer BM0_rte segments needed due to the more efficient utilization of the BM0_rte segments; produce the BM0_rte segments with higher heights using 193i lithography, which reduces the number of EUV lithography masks otherwise needed compared to the second other method; reduce costs compared to the second other method because fewer EUV lithography masks are used compared to the number of EUV masks used by the second other method; and alleviate the second deficiency of M0_rte routing resources at least as effectively as the second other method despite the lower cost cell area using BM0_rte segments with higher heights.

[0068] For a second given cell region corresponding to cell region 102(1) or cell region 110(1) according to a second other approach (SOA), the second given SOA cell has two alpha tracks aligned with SOA_M0_rte segments and two beta tracks aligned with SOA_BM0_rte segments.

[0069] Although cell 102(1) also has three beta tracks aligned with BM0_rte segments, cell 102(1) is different in that cell 102(1) has more alpha tracks aligned with M0_rte segments, i.e., three alpha tracks. Although cell 110(1) also has two alpha tracks aligned with M0_rte segments, cell 110(1) is different in that cell 110(1) has fewer beta tracks aligned with BM0_rte segments, i.e., one beta track. According to the second other approach (SOA), the corresponding AR stack of the second given cell region has a height h_SOA_stk that is shorter than the AR stack 131 of cell 102(1) and taller than the AR stack 132 of cell 110(1) such that h_stk_132 < h_SOA_stk < h_stk_131.

[0070] In some embodiments, to produce an instance of cell region 102(1) or an instance of cell region 110(1) by photolithography, one EUV mask is needed to produce BM0_rte segments and four 193i masks are needed to produce BM1_rte segments. For a second given cell region corresponding to cell region 102(1) or cell region 110(1) according to the second other approach (SOA), three EUV masks are used to produce BM0_rte segments and two EUV masks are used to produce BM1_rte segments. Thus, at least some embodiments have the benefit of reducing the number of masks needed by about 80% compared to the second other approach, e.g., reducing the number of EUV masks used from five to one, which reduces cost.

[0071] Regarding FIG. 1AIn some embodiments of the general cell, the pitch of the M0_rte segments is in the range of (≈20nm)≤p_M0_rte≤(≈23nm). In some embodiments of the general cell, the height of the BM0_PG segments is in the range of (≈20nm)≤h_BM0_PG≤(≈30nm). In some embodiments of the general cell, the height of the BM0_rte segments is in the range of (≈15nm)≤h_BM0_rte≤(≈19nm). In some embodiments of the general cell, the pitch of the BM0_rte segments is in the range of (≈30nm)≤p_BM0_rte≤(≈38nm). In some embodiments of the general cell, the gap height of adjacent BM0_rte segments is in the range of (≈15nm)≤h_gap_BM0_rte≤(≈19nm). In some embodiments of the general cell, the pitch p_BM1_rte of the BM1 routing segments (not shown) in the BMET1 layer is in the range of (≈74nm)≤p_BM1_rte≤(≈80nm).

[0072] For a corresponding second given cell region according to the SOA with the cell region 102(1) or the cell region 110(1), the corresponding cell region has: the pitch p_SOA_M0_rte of the SOA_M0_rte segments is in the range of (≈20nm)≤p_SOA_M0_rte≤(≈23nm); the pitch p_SOA_BM0_rte of the SOA_BM0_rte segments is in the range of (≈20nm)≤p_SOA_BM0_rte≤(≈23nm); the pitch p_SOA_BM1_rte of the SOA_BM1_rte segments is in the range of (≈42nm)≤p_SOA_BM1_rte≤(≈48nm).

[0073] In some embodiments, the front side pitch p_M0_rte of the general cell is in the same range as the front side pitch p_SOA_M0_rte of the second given cell region according to the second other method, while the back side pitches BM0_rte and BM1_rte of the general cell are correspondingly larger than the values of the back side pitches SOA_BM0_rte and SOA_BM1_rte of the second given cell region according to the second other method. The larger back side pitches of the general cell of some embodiments facilitate the use of 193i lithography masks instead of some EUV lithography masks used according to the second other method, which has the advantage of reducing the cost of the general cell compared to the cost of the second given cell region according to the second other method.

[0074] FIGS. 1C-1E is a corresponding layout diagram of the corresponding devices 100C to 100E according to some embodiments.

[0075] In FIGS. 1C-1EIn particular, the broken line 136 is represented as follows: the instances of row 184 and row 186 (not all of which are labeled with reference numerals) extend left and right along the X axis; the column 290 extends up and down along the Y axis.

[0076] In FIG. 1C particular, the device 100C includes the tall cell regions 102(2)-102(5) and the short cell regions 110(2)-110(5) arranged in the column 290 extending parallel to the Y axis. The tall cell region 102(2) is stacked on the short cell region 110(2) with respect to the Y axis and the tall and short cell regions together represent the stacked pair 188(1).

[0077] The tall cell regions 102(2)-102(5) are respectively stacked on the short cell regions 110(2)-110(5) and respectively represent the stacked pairs 188(1)-188(4). The stacked pairs 188(1)-188(4) in the column 290 are adjacent such that there is no instance of another cell region between any two of the stacked pairs 188(1)-188(4).

[0078] In FIG. 1D particular, the device 100D differs from the device 100C of FIG. 1C as follows. In addition to the tall cell region 102(3) and the short cell region 110(3) of the stacked pair 188(2), the device 100D includes the tall cell regions 102(6)-102(9) and the short cell regions 110(6)-110(8) arranged in the column 290 instead of the tall cell regions 102(2) and 102(4)-102(5) and the short cell regions 110(2) and 110(4)-110(5),

[0079] The tall cell regions 102(6) and 102(9) are stacked on the short cell regions 110(6) and 110(8) and respectively represent the stacked pairs 188(5)-188(6). The tall cell region 102(7) is stacked between the stacked pairs 188(5) and 188(2). The tall cell region 102(8) is stacked between the stacked pairs 188(2) and 188(6).

[0080] In FIG. 1E particular, the device 100E differs from the device 100C of FIG. 1C as follows. In addition to the tall cell region 102(3) and the short cell region 110(3) of the stacked pair 188(2), the device 100E includes the tall cell region 102(10) and the short cell regions 110(9)-110(13) arranged in the column 290 instead of the tall cell regions 102(2) and 102(4)-102(5) and the short cell regions 110(2) and 110(4)-110(5),

[0081] Stacked below the tall cell region (not shown) is a short cell region 110(9), which together represents a stack pair 188(7). Stacked on the short cell region 110(12) is a tall cell region 102(10), which together represents a stack pair 188(8).

[0082] Stacked between the stack pair 188(7) and 188(2) is a short cell region 110(10). Stacked between the stack pair 188(2) and 188(8) is a short cell region 110(11). Stacked between the stack pair 188(8) and another stack pair (not shown) is a short cell region 110(13).

[0083] FIGS. 2A-2B are corresponding cross-sections 200A-200B of a device having a CFET architecture, according to some embodiments. Corresponding to FIGS. 2A-2B the cross-sections 200A-200B of the CFET device of FIG. 1A is an example of the device 100A.

[0084] FIG. 2C is a three-quarter perspective view 200C of a device having a CFET architecture, according to some embodiments. FIG. 2C The CFET device 200C of FIGS. 2A-2B is a simplified version of the CFET device of the cross-sections 200A-200B.

[0085] FIG. 2A corresponds to FIG. 1A section IIA-IIA' of FIG. 2B corresponds to FIG. 1A section IIB-IIB' of FIGS. 2A-2C In

[0086] The device 200A to the device 200B follow a similar numbering scheme as the layout of FIG. 1A Although some components correspond, some components also differ. To help identify the components that correspond but differ, the numbering convention uses 2-series numbers for the cross-sections 200A-200B, while FIG. 1A uses 1-series numbers. For example, FIGS. 2A-2B the M0 rte segment 226(5) in each of FIG. 1A corresponds to the M0 rte segment 126(5) in FIGS. 2A-2B For brevity, the discussion will focus more on the differences between FIG. 1A and

[0087] ​Each of the devices 200A-B: has a front side 239F and a back side 239R; and includes a CFET component layer 220 stacked on a BMET0 layer 222 and a MET0 layer 218 stacked on the CFET component layer 220, with respect to the Z-axis.

[0088] In FIG. 2A , the cross-section 200A includes: ARD1 240(1) and ARD1 240(2); ARD2 242(1) and ARD2 242(2); instances of metal-to-MD contact structures 250(1) and 250(2) in the context of source / drain (S / D) regions of ARD1 240(1) and 240(2); buried MD (BMD) contact structures 252(1) and 252(2); an instance of insulator 246 between MD contact structure 250(1) and BMD contact structure 252(1); an instance of contact-to-contact (C2C) contact structure 248 between MD contact structure 250(2) and BMD contact structure 252(2); M0_PG segments 224(1) and 224(2); M0 rte segments 226(1)-226(5); an instance of via-to-MD (VD) contact structure 258; and an instance of buried VD (BVD) contact structure 260.

[0089] MD contact structure 250(1) is not coupled to BMD 252(1) due to the instance of insulator 246. MD contact structure 250(2) is coupled to BMD 252(2) due to the instance of C2C contact structure 248. In some embodiments, the instance of insulator 246 between MD contact structure 250(1) and BMD 252(1) is replaced by the instance of C2C contact structure 248. In some embodiments, the instance of C2C contact structure 248 between MD contact structure 250(2) and BMD 252(2) is replaced by the instance of insulator 246.

[0090] In FIG. 2B , the cross-section 200B differs from the cross-section 200A of FIG. 2A as follows. Metal-to-gate (MG) contact structures 246(1) and 246(2) correspondingly replace MD contact structures 250(1) and 250(2). Buried MG (BMG) contact structures 248(1) and 248(2) correspondingly replace BMD contact structures 252(1) and 252(2). Cross-section 200B includes an instance of via-to-MG (VG) contact structure 254 instead of an instance of VD contact structure 258. Cross-section 200B includes an instance of buried VG (BVG) contact structure 256 instead of an instance of BVD contact structure 260.

[0091] In FIG. 2BIn some embodiments, an instance of the C2C contact structure 248 is located between the MG contact structure 246(1) and the BMG contact structure 248(1). An instance of the insulator 246 is located between the MG contact structure 246(2) and the BMG contact structure 248(2). In some embodiments, the instance of the insulator 246 between the MG contact structure 246(2) and the BMG contact structure 248(2) is replaced by an instance of the C2C contact structure 248. In some embodiments, the instance of the C2C contact structure 248 between the MG contact structure 246(1) and the BMG contact structure 248(1) is replaced by an instance of the insulator 246.

[0092] Additionally, as part of developing one or more embodiments of the present application, the present inventor has recognized that, for a given AR stack, the use of the BVG contact structure 256 results in a taller backside ARD2 relative to the frontside ARD1 in order to reduce, if not eliminate, the overlap between the backside ARD2 and an instance of the BVG contact structure 256 relative to the Y-axis; that the layout map of the third given cell region can be altered to reduce, if not eliminate, the use of instances of the BVG contact structure 256 in order to facilitate, correspondingly, the use of taller versions of the backside ARD2; that the use of taller versions of the backside ARD2 will improve the performance of the third given cell region compared to the use of shorter versions of the backside ARD2; and more generally, that the layout map of the third given cell region can be altered to reduce the use of instances of the BVG contact structure 256 in order to facilitate the use of taller versions of the backside ARD2, and correspondingly, better cell region performance, e.g., faster speed. Generally speaking, the benefits of reducing, if not eliminating, such overlap include: reducing the risk of damage to the dielectric between an instance of the backside ARD2 and the BMG (e.g., 248(2)) due to the proximity of a corresponding instance of the BVG contact structure 256; reducing the distortion (e.g., shifting) of the threshold voltage of a transistor composed of an instance of the BVG contact structure 256 and a corresponding portion of the backside ARD2 due to the proximity of the corresponding instance of the BVG contact structure 256; or the like.

[0093] Thus, at least some of the present embodiments: use a BVG-reduced layout of a cell region that is arranged to reduce usage of instances of BVG junction structures 256, which correspondingly facilitates use of higher versions of backside ARD2s; use of higher versions of backside ARD2s in a BVG-reduced layout improves performance of a cell region compared to use of correspondingly shorter versions of backside ARD2s, otherwise requiring reduction (if not elimination) of overlap between instances of backside ARD2s and BVG junction structures 256 with respect to the Y-axis; and better performance of a BVG-reduced cell region, e.g., faster speed, is achieved due to use of higher versions of backside ARD2s, facilitated by reduction of usage of shorter versions of backside ARD2s, otherwise requiring reduction (if not elimination) of overlap between instances of backside ARD2s and BVG junction structures 256. FIGS. 4A-4D is an example of a BVG-reduced layout that yields a corresponding cell region that exhibits speed improvement compared to a non-BVG-reduced counterpart layout.

[0094] FIG. 2D is a cross-sectional view 210(1)' of a cell region having a CFET architecture according to some embodiments. Corresponding to FIG. 2D The cell region of cross-section 210(1)' of FIG. 1A is an example of cell region 110(1) of FIG. 2D The cell region of cross-section 210(1)' of FIGS. 2A-2B is a variant of cell region 210(1) of

[0095] In FIG. 2D The differences of cell region 210(1)' from cell region 210(1) of FIGS. 2A-2B are as follows. ARD1 240(1) is replaced by ARD1 240(3). ARD2 242(1) is replaced by ARD2 242(3). MG junction structure 246(1) is replaced by MG junction structure 246(3). BMG junction structure 248(1) is replaced by BMG junction structure 248(3). Cell region 210(1)' includes MG-to-BM0(VGTB) junction structure 262 that couples MG junction structure 246(3) to BM0 rte segment 240(2).

[0096] For a given AR stack in a third given cell region, the cell region has a CFET architecture and is oriented in an orthogonal Cartesian coordinate system (similar to the coordinates assumed by the present embodiments), a MG-to-BM0(VGTB) junction structure is used (in some embodiments) to connect a frontside active region ARD1 to a corresponding BM0 rte segment. An example of a VGTB junction structure is FIG. 2Dof the VGTB contact structure 262, where the VGTB contact structure 262 couples the MG contact structure 246(3) to the BM0_rte segment 240(2).

[0097] In addition, as part of developing one or more embodiments of the present application, the present inventors have recognized that, for a given AR stack, using instances of the VGTB contact structure 262, in order to facilitate the VGTB contact structure 262 extending through portions of tiers that would otherwise be occupied by a taller backside ARD2 version as the frontside ARD1, results in a shorter backside ARD2 relative to the frontside ARD1; that the layout of the third given cell region can be altered to reduce, if not eliminate, the use of instances of the VGTB contact structure 262, thereby facilitating the use of taller versions of the backside ARD2 accordingly; that the use of taller versions of the backside ARD2 will improve the performance of the third given cell region compared to using shorter versions of the backside ARD2; and more generally that the layout of the third given cell region can be altered to reduce the use of instances of the VGTB contact structure 262, thereby facilitating the use of taller versions of the backside ARD2 and the corresponding better performance of the cell region, e.g., faster speed.

[0098] Thus, at least some of the existing embodiments: use a VGTB-reduced cell region layout that is configured to reduce the use of instances of the VGTB contact structure 262, which facilitates the use of taller versions of the backside ARD2 accordingly; use taller versions of the backside ARD2 in the VGTB-reduced layout to improve the performance of the cell region compared to using correspondingly shorter versions of the backside ARD2, which would otherwise be needed to accommodate instances of the VGTB contact structure 262; and achieve better performance, e.g., faster speed, of the VGTB-reduced cell region due to the use of taller versions of the backside ARD2, which is facilitated by reducing the use of shorter versions of the backside ARD2, which would otherwise be needed to accommodate instances of the VGTB contact structure 262. FIGS. 4A-4D is an example of a VGTB-reduced layout that results in a corresponding cell region that exhibits speed improvement compared to a non-VGTB-reduced counterpart layout.

[0099] FIGS. 3A-3B are corresponding backside layouts 339R_3A and 339R_3B of the AO22D1 cell region according to some embodiments.

[0100] In some embodiments, AOD22D1 is an alphanumeric literal string used as an adjective, intended to mean that a cell region having backside layout 339R_3A is an AND-OR cell region, where an AND gate portion has two inputs, or an OR gate has two inputs, and a driving strength of the cell region is unit driving strength D. In some embodiments, a value of unit driving strength D is determined, for example, by design rules and scales of a corresponding semiconductor process technology node.

[0101] AO22D1 cell region having backside layout 339R_3A has a similar arrangement as cell region 102(1).

[0102] In FIG. 3A , layout 339R_3A includes: a single instance of ARD2; BM0_PG segment BM0_PG(1); BM0_rte segments BM0_rte(1)-BM0_rte(2); and buried gate lines 392(1)-392(8).

[0103] With respect to the X-axis, adjacent ones of buried gate lines 392(1)-392(8) are separated by a uniform distance. In some embodiments, the uniform distance is a multiple of a given unit of distance measurement. In some embodiments, a value of the multiple is 1, such that the uniform distance is one instance of the given unit of distance measurement. In some embodiments, the unit of distance measurement is 1.0 CPP. In some embodiments, CCP is an abbreviation for contacted poly pitch. A value of CPP is determined, for example, by design rules and scales of a corresponding semiconductor process technology node. Here, the word “poly” in the term CPP does not necessarily mean corresponding to FIG. 3A Gate lines in semiconductor assemblies of

[0104] FIG. 3A In, a width of AO22D1 cell region corresponding to backside layout 339R_3A is 7 CPP. AO22D1 cell region corresponding to backside layout 339R_3A has a height h_102(1).

[0105] For the fourth given cell region according to the SOA, which is the counterpart of the AO22D1 cell region corresponding to the backside layout 339R_3A, the fourth given cell region includes an instance of the BVG contact structure, which reduces the height of the corresponding backside ARD2 in the fourth given cell region. The benefit of the AO22D1 cell region corresponding to the backside layout 339R_3A (and the AO22D1 cell region corresponding to the backside layout 339R_3B, as described below) is the avoidance of an instance of the BVG contact structure, such that the backside ARD2 in the AO22D1 cell region corresponding to the backside layout 339R_3A is taller than the corresponding backside ARD2 in the fourth given cell region according to the SOA.

[0106] The backside layout 339R_3A is one example of a VGTB-reduced layout that uses at least one taller version of a backside ARD2. In some embodiments of the AO22D1 cell region that partially corresponds to the backside layout 339R_3A, the use of at least one taller version of a backside ARD2 in a VGTB-reduced layout results in a corresponding cell region that is about 35% faster than the non-VGTB-reduced counterpart layout.

[0107] In some embodiments, the gate lines 392(1) and 392(8) are replaced by respective isolation dummy gates (IDGs) (as described below). In some embodiments, the gate line 392(5) is replaced by an IDG. In some embodiments in which the gate line 392(5) is replaced by an IDG (IDG 392(5)), the AO22D1 cell region with the backside layout 339R_3A is described as a combination of a first cell region to the left of the IDG 392(5) and a second cell region to the right of the IDG 392(5).

[0108] In some embodiments, an IDG is a dielectric structure that includes one or more dielectric materials and functions as an electrical isolation structure. Thus, an IDG is not an electrically conductive structure and thus does not function as, for example, an active gate or a transistor. An IDG includes one or more dielectric materials and functions as an electrical isolation structure. In some embodiments, an IDG is based on an MD junction structure or a BMD junction structure as a precursor. In some embodiments, a method of forming an IDG includes: forming an MD or BMD junction structure; sacrificing / removing (e.g., etching) the MD or BMD junction structure to form a trench around a corresponding ARP or ARN; (optionally) removing some or all of the corresponding ARP or ARN that was previously partially or completely surrounded by the MD or BMD junction structure to deepen the trench and thereby partially or completely isolate the corresponding ARP or ARN from extending beyond a corresponding left or right side of the X-axis cell region; and filling the trench with one or more dielectric materials such that the resulting electrical isolation structure (i.e., the IDG) has a physical size similar to the size of the sacrificed MD or BMD junction structure. In some embodiments, an IDG is a dielectric feature that includes one or more dielectric materials (e.g., oxide, nitride, oxynitride, or other suitable materials) and functions as an isolation feature. In some embodiments, an IDG is a continuous polysilicon over an oxide diffusion (OD) edge structure, referred to as a CPODE structure.

[0109] With respect to FIG. 3B The AO22D1 cell region with backside layout 339R_3B has a width of 4 CPP with respect to the cell boundary extending parallel to the X-axis. The AO22D1 cell region with backside layout 339R_3B is arranged into a third cell region above the cell boundary and a fourth cell region below the cell boundary with respect to the cell boundary extending parallel to the X-axis. The third cell region has a similar arrangement as cell region 102(1). The fourth cell region has a similar arrangement as cell region 110(1). Each of the third and fourth cell regions has a width of 4 CPP. The third cell region has a height of h_102(1). The fourth cell region has a height of h_110(1). The third and fourth cell regions together are an example of a stacked pair, such as stacked pair 188(2).

[0110] In FIG. 3B The AO22D1 cell region corresponding to backside layout 339R_3B has a width of 4 CPP. The AO22D1 cell region corresponding to backside layout 339R_3A has a height of h_102(1) + h_110(1). The AO22D1 cell region corresponding to backside layout 339R_3B is taller but narrower, i.e., has a smaller width, than the AO22D1 cell region corresponding to backside layout 339R_3A.

[0111] In FIG. 3BIn particular, the layout 339R_3B includes: first and second instances of ARD2 corresponding to third and fourth cell regions; BM0_PG segments BM0_PG(2)-BM0_PG(3); BM0_rte segments BM0_rte(3)-BM0_rte(5); buried gate lines 392(9)-392(13) in the third cell region; and buried gate lines 392(14)-392(18) in the fourth cell region. Buried gate lines 392(9)-392(13) are substantially colinear with buried gate lines 392(14)-392(18). In some embodiments, buried gate lines 392(9), 392(13), 392(14), and 392(18) are replaced by corresponding IDGs.

[0112] FIG. 3B The first instance of ARD2 in the third cell region is taller than the corresponding backside ARD2 in the fourth given cell region according to the second other method. In some embodiments, FIG. 3B The second instance of ARD2 in the fourth cell region is substantially the same height as the corresponding backside ARD2 in the fourth given cell region according to the second other method.

[0113] The backside layout 339R_3B is another example of a VGTB-reduced layout that uses at least one taller version of a backside ARD2. In some embodiments corresponding to AO22D1 cell regions of the backside layout 339R_3B, the use of at least one taller version of a backside ARD2 in a VGTB-reduced layout results in a corresponding cell region that is about 34% faster than the corresponding layout that is not VGTB-reduced.

[0114] FIGS. 4A-4B are corresponding frontside 439F_4A and backside 439_4B layouts of a FAD1 cell region according to some embodiments.

[0115] In some embodiments, FAD1 is an alphanumeric literal string used as an adjective that is intended to mean that a cell region having a frontside layout 439F_4A and a backside layout 439R_4B is a one-bit (unit cell) full adder (FA) whose drive strength is D1.

[0116] With respect to FIGS. 4A-4BEach of the fifth and sixth cell regions has a width of 9 CPP. The fifth cell region has a height of h_102(1). The sixth cell region has a height of h_110(1). The fifth and sixth cell regions together are an example of a stacked pair, such as stacked pair 188(2).

[0117] In the example of FIG. 4B, layout 439R_4B includes: a first instance of ARD2 in the fifth cell region and a second instance of ARD2 in the sixth cell region; BM0_PG segments BM0_PG(4) and BM0_PG(5) in the corresponding fifth and sixth cell regions; BM0_rte segments BM0_rte(6) - BM0_rte(8) in the corresponding fifth and sixth cell regions; buried gate lines in the corresponding fifth and / or sixth cell regions; and two instances of a BVG contact structure coupled to BM0_rte segment BM0_rte(7). In some embodiments, the leftmost buried gate line and the rightmost buried gate line of the fifth cell region are replaced by corresponding IDGs. In some embodiments, the leftmost buried gate line and the rightmost buried gate line of the sixth cell region are replaced by corresponding IDGs. FIG. 4A In the example of FIG. 4B, layout 439R_4B includes: a first instance of ARD2 in the fifth cell region and a second instance of ARD2 in the sixth cell region; BM0_PG segments BM0_PG(4) and BM0_PG(5) in the corresponding fifth and sixth cell regions; BM0_rte segments BM0_rte(6) - BM0_rte(8) in the corresponding fifth and sixth cell regions; buried gate lines in the corresponding fifth and / or sixth cell regions; and two instances of a BVG contact structure coupled to BM0_rte segment BM0_rte(7). In some embodiments, the leftmost buried gate line and the rightmost buried gate line of the fifth cell region are replaced by corresponding IDGs. In some embodiments, the leftmost buried gate line and the rightmost buried gate line of the sixth cell region are replaced by corresponding IDGs.

[0118] FIG. 4B In the example of FIG. 4B, layout 439R_4B includes: a first instance of ARD2 in the fifth cell region and a second instance of ARD2 in the sixth cell region; BM0_PG segments BM0_PG(4) and BM0_PG(5) in the corresponding fifth and sixth cell regions; BM0_rte segments BM0_rte(6) - BM0_rte(8) in the corresponding fifth and sixth cell regions; buried gate lines in the corresponding fifth and / or sixth cell regions; and two instances of a BVG contact structure coupled to BM0_rte segment BM0_rte(7). In some embodiments, the leftmost buried gate line and the rightmost buried gate line of the fifth cell region are replaced by corresponding IDGs. In some embodiments, the leftmost buried gate line and the rightmost buried gate line of the sixth cell region are replaced by corresponding IDGs.

[0119] ​The fifth given cell region according to the second other method is a corresponding portion of the FAD1 cell region corresponding to the front-side layout 439F_4A and the back-side layout 439R_4B, represented by three instances of a sixth given cell region according to the second other method, which are stacked on top of each other. The back-side of each of the three instances of the sixth given cell region has a BM0 rte segment aligned with two beta tracks, i.e., each instance of the sixth cell region has two aligned beta tracks. The fifth given cell region includes three corresponding instances of the ARD2 and five instances of the BVG contact structure, which reduces the corresponding height of the three corresponding instances of the back-side ARD2 in the fifth given cell region. The benefit of the FAD1 cell region corresponding to the front-side layout 439F_4A and the back-side layout 439R_4B is the avoidance of four instances of the BVG contact structure, which facilitates the at least first instance of the ARD2 in the fifth cell region to be taller than each of the three corresponding instances of the back-side ARD2 in the fifth given cell region according to the second other method. In some embodiments, FIG. 4B the second instance of the ARD2 in the sixth cell region according to some embodiments is shorter than the corresponding back-side ARD2 in each of the three instances of the sixth given cell region according to the second other method.

[0120] According to the second other method, the three instances of the sixth given cell region have an average of 2.0 aligned beta tracks per cell region. FIG. 4B The fifth and sixth cell regions according to some embodiments have BM0 rte segments aligned corresponding to two beta tracks and one beta track, respectively. Overall, FIGS. 4A-4B The fifth and sixth cell regions according to some embodiments have an average of 2.5 aligned beta tracks per cell region, which represents an improvement in wiring resources at least compared to the fifth given cell region according to the second other method.

[0121] The back-side layout 439R_4B is one example of a VGTB-reduced layout that uses at least one taller version of the back-side ARD2. In some embodiments of the FAD1 cell region corresponding to the front-side layout 439F_4A and the back-side layout 439R_4B, the use of at least one taller version of the back-side ARD2 in the VGTB-reduced layout produces a corresponding cell region that exhibits a speed improvement of about 12% compared to the non-VGTB-reduced corresponding layout.

[0122] FIGS. 4C-4D is the corresponding planar view 241 and back-side layout 439R_4D of the SDFQD1 according to some embodiments. FIG. 4C Also included is a front-side layout 439F_4C according to some embodiments that is located below the planar view 241.

[0123] In some embodiments, SDFQD1 is an alphanumeric literal string used as an adjective that is intended to mean that the cell region having the plan view 241 and the backside layout view 439R_4D is a scan-insertion DFF (SDFQ) whose drive strength is D1.

[0124] In FIG. 4C , the plan view 241 shows that the FAD1 cell region includes: a clock pulse (CP) inverter CPINV that generates an inverted version (CPB) of the CP; a CPB inverter CPBINV that generates an inverted version of the CPB; a scan enable (SE) signal inverter SEINV that generates an inverted version (SEB) of the SE; a multi-tasker MUX; a master latch; a slave latch; and an output buffer that includes a block Q and a PreQ.

[0125] With respect to each of FIGS. 4C-4D , and with respect to a cell boundary that extends parallel to the X axis, the SDFQD1 cell region having the plan view 241, the frontside layout view 439F_4C, and the backside layout view 439R_4D is arranged into a seventh cell region above the cell boundary and an eighth cell region below the cell boundary. The seventh cell region is arranged similarly to the cell region 102(1). The eighth cell region is arranged similarly to the cell region 110(1). Each of the seventh and eighth cell regions has a width of 12 CPP. The seventh cell region has a height h_102(1). The eighth cell region has a height h_110(1). The seventh and eighth cell regions together are an example of a stacked pair, such as the stacked pair 188(2).

[0126] In FIG. 4C , the layout view 439R_4C includes: a first instance (not shown) of the ARD1 in the seventh cell region and a second instance (not shown) of the ARD1 in the eighth cell region; the M0_PG segment is located in the corresponding seventh and eighth cell regions; the M0 rte segment is located in the corresponding seventh and eighth cell regions; the gate lines are located in the corresponding seventh and / or eighth cell regions. In some embodiments, the leftmost gate line and the rightmost gate line of the seventh cell region are replaced by corresponding IDGs. In some embodiments, the leftmost gate line and the rightmost gate line of the eighth cell region are replaced by corresponding IDGs.

[0127] In FIG. 4DIn some embodiments, the seventh unit region has a leftmost buried gate line and a rightmost buried gate line replaced by corresponding IDGs. In some embodiments, the eighth unit region has a leftmost buried gate line and a rightmost buried gate line replaced by corresponding IDGs.

[0128] The seventh given unit region according to the second other method is a corresponding portion of the SDFQD1 unit region corresponding to the plan view 241, the front side layout view 439F_4C, and the back side layout view 439R_4D, represented by two instances of an eighth given unit region according to the second other method, which are stacked on top of each other. The back side of each of the two instances of the eighth given unit region has BM0_rte segments aligned with two beta tracks, i.e., each instance of the eighth unit region has two aligned beta tracks. The seventh given unit region includes two corresponding instances of ARD2 and six instances of the BVG contact structure, which reduces the corresponding height of the two corresponding instances of back side ARD2 in the seventh given unit region. The benefit of the SDFQD1 unit region corresponding to the plan view 241, the front side layout view 439F_4C, and the back side layout view 439R_4D is the avoidance of five instances of the BVG contact structure, which facilitates at least the first instance of ARD2 in the seventh unit region being taller than each of the two corresponding instances of back side ARD2 in the seventh given unit region according to the second other method. In some embodiments, FIG. 4D The second instance of ARD2 in the eighth unit region of the SDFQD1 is shorter than the corresponding back side ARD2 in each of the three instances of the eighth given unit region according to the second other method.

[0129] According to the second other method, the two instances of the eighth given unit region have an average of 2.0 aligned beta tracks per unit region. FIG. 4D The seventh and eighth unit regions of the SDFQD1 have BM0_rte segments aligned with two beta tracks and one beta track, respectively. Overall, FIGS. 4C-4D The seventh and eighth unit regions of the SDFQD1 have an average of 2.5 aligned beta tracks per unit region, which represents an improvement at least in terms of routing resources compared to the seventh given unit region according to the second other method.

[0130] The back-side layout 439R_4D is an example of a VGTB-reduced layout that uses at least one higher version of the back-side ARD2. In some embodiments of the SDFQD1 cell regions corresponding to planar view 241, front-side layout 439F_4C, and back-side layout 439R_4D, the use of at least one higher version of the back-side ARD2 in the VGTB-reduced layout produces the corresponding cell regions, which exhibit an approximately 7.6% speed improvement compared to the corresponding non-VGTB-reduced layout.

[0131] FIGS. 5A-5B The figures show corresponding circuit diagrams of XOR / XNR594A and XOR / XNR594B according to some embodiments.

[0132] In some embodiments, XOR / XNR is an alphanumeric literal string used as an adjective to indicate that the circuit diagram is an exclusive OR (XOR) and exclusive NOR (XNR) circuit. FIGS. 5A-5B In each of these, a logical XOR output is generated at node Z. The logical XNR output is the opposite of the logical XOR output. Node Z is coupled to node ZN via an inverter. A logical XNR output is generated at node ZN.

[0133] exist FIG. 5A In the XOR / XNR594A, there are dummy devices D1-D2. Dummy device D1 is a short-circuited NMOS field-effect transistor (FET). Dummy device D2 is a short-circuited PMOS FET.

[0134] exist FIG. 5B In the XOR / XNR594B, there are dummy devices D3-D6. Each of dummy devices D3 and D4 is an NFET configured for a capacitor. Each of dummy devices D5 and D6 is a PFET configured for a capacitor.

[0135] FIGS. 5C-5D According to some embodiments FIG. 5A The corresponding front layout diagram 539F_5C and rear layout diagram 539R_5D of XOR / XNR594A.

[0136] about FIGS. 5C-5Deach of the first and second unit regions has a width of 5 CPP. The first unit region has a height of h_102(1). The second unit region has a height of h_110(1). The first and second unit regions together are an example of a stacked pair, e.g., stacked pair 188(1).

[0137] In the example of FIG. 5C, layout 539F_5C includes: a first instance of ARD1 (not shown) in the first unit region and a second instance of ARD1 (not shown) in the second unit region; M0_PG segments M0_PG(3) and M0_PG(4) are located in the corresponding first and second unit regions; M0_rte segments M0_rte(6)-M0_rte(10) are located in the corresponding first and second unit regions; gate lines are located in the corresponding first and / or second unit regions. In some embodiments, the leftmost and rightmost gate lines of the first unit region are replaced by corresponding IDGs. In some embodiments, the leftmost and rightmost gate lines of the second unit region are replaced by corresponding IDGs. FIG. 5C In the example of FIG. 5D, layout 539R_5D includes: a first instance of ARD2 (not shown) in the first unit region and a second instance of ARD2 (not shown) in the second unit region; BM0_PG segments BM0_PG(8) and BM0_PG(9) are located in the corresponding first and second unit regions; BM0_rte segments BM0_rte(11)-BM0_rte(13) are located in the corresponding first and second unit regions; buried gate lines are located in the corresponding first and / or second unit regions. In some embodiments, the leftmost and rightmost buried gate lines of the first unit region are replaced by corresponding IDGs. In some embodiments, the leftmost and rightmost buried gate lines of the second unit region are replaced by corresponding IDGs.

[0138] FIG. 5D In the example of FIG. 5D, layout 539R_5D includes: a first instance of ARD2 (not shown) in the first unit region and a second instance of ARD2 (not shown) in the second unit region; BM0_PG segments BM0_PG(8) and BM0_PG(9) are located in the corresponding first and second unit regions; BM0_rte segments BM0_rte(11)-BM0_rte(13) are located in the corresponding first and second unit regions; buried gate lines are located in the corresponding first and / or second unit regions. In some embodiments, the leftmost and rightmost buried gate lines of the first unit region are replaced by corresponding IDGs. In some embodiments, the leftmost and rightmost buried gate lines of the second unit region are replaced by corresponding IDGs.

[0139] ​Layout 539R_5D also includes BM1_rte segment BM1LI and two instances of a via to BM0_rte (BV0) junction structure. BM1_rte segment BM1LI is correspondingly coupled to BM0_rte segment BM0_rte (12) and BM0_rte (13) through instances of the BV0 junction structure. In some embodiments, BM1LI is an alphanumeric literal string used as an adjective intended to indicate that the BM1_rte segment is a local interconnect (LI) structure.

[0140] In FIG. 5C , it is assumed that ARD1 is doped with P-type dopant such that each of M0_PG (3) and M0_PG (4) is configured to carry / conduct a first reference voltage Vref1 = VSS. In FIG. 5D , it is assumed that ARD2 is doped with N-type dopant such that each of BM0_PG (8) and BM0_PG (9) is configured to carry / conduct a second reference voltage Vref2 = VDD.

[0141] In FIG. 5C , the selected one of the gate lines is shown with a different fill color and / or pattern to reflect that the selected gate line is coupled to dummy device D1. In FIG. 5D , the selected one of the buried gate lines is shown with a different fill color and / or pattern to reflect that the selected buried gate line is coupled to dummy device D2.

[0142] Backside layout 539R_5D is an example of a VGTB-reduced layout that uses at least one higher version of backside ARD2 compared to a ninth given cell region according to the second other approach, which is a counterpart based on XOR / XOR 594A of frontside layout 539F_5C and backside layout 539R_5D. In some embodiments based on XOR / XOR 594A of frontside layout 539F_5C and backside layout 539R_5D, using at least one higher version of backside ARD2 in a VGTB-reduced layout results in a corresponding cell region that has about 7% speed improvement compared to a non-VGTB-reduced counterpart layout.

[0143] FIGS. 5E-5F is a counterpart frontside layout 539F_5E and backside layout 539R_5F of XOR / XNR 594B according to some embodiments of FIG. 5B .

[0144] Regarding FIGS. 5E-5Feach of the first and second cell regions has a width of 5 CPP. The first cell region has a height of h_102(1). The second cell region has a height of h_110(1). The first and second cell regions together are an example of a stacked pair, e.g., stacked pair 188(1).

[0145] In FIG. 5E , layout 539F_5E includes: a first instance of ARD1 (not shown) in the eleventh cell region and a second instance of ARD1 (not shown) in the twelfth cell region; MO_PG segments MO_PG(5) and MO_PG(6) are located in the corresponding eleventh and twelfth cell regions; MO_rte segments MO_rte(11)-MO_rte(15) are located in the corresponding eleventh and twelfth cell regions; gate lines are located in the corresponding eleventh and / or twelfth cell regions. In some embodiments, the leftmost and rightmost gate lines of the eleventh cell region are replaced by corresponding IDGs. In some embodiments, the leftmost and rightmost gate lines of the twelfth cell region are replaced by corresponding IDGs.

[0146] In FIG. 5F , layout 539R_5F includes: a first instance of ARD2 (not shown) in the eleventh cell region and a second instance of ARD2 (not shown) in the twelfth cell region; BM0_PG segments BM0_PG(10) and BM0_PG(11) are located in the corresponding eleventh and twelfth cell regions; BM0_rte segments BM0_rte(14)-BM0_rte(16) are located in the corresponding eleventh and twelfth cell regions; buried gate lines are located in the corresponding eleventh and / or twelfth cell regions. In some embodiments, the leftmost and rightmost buried gate lines of the eleventh cell region are replaced by corresponding IDGs. In some embodiments, the leftmost and rightmost buried gate lines of the twelfth cell region are replaced by corresponding IDGs.

[0147] In FIG. 5E , assume that ARD1 is doped with P-type dopants such that each of MO_PG(5) and MO_PG(6) is configured to carry / conduct a first reference voltage Vref1 = VSS. In FIG. 5FIn the middle, ARD2 is assumed to dope N-type dopants, such that each of BM0_PG(10) and BM0_PG(11) is configured to carry / conduct a second reference voltage Vref2 = VDD.

[0148] In FIG. 5E the middle, two selected gate lines of the gate lines are shown with different fill colors and / or patterns to reflect the selected gate lines coupled with corresponding dummy devices D3-D4. In FIG. 5F the middle, two selected buried gate lines of the buried gate lines are shown with different fill colors and / or patterns to reflect the selected buried gate lines coupled with corresponding dummy devices D5-D6.

[0149] FIG. 5F The backside layout 539R_5F of FIG. 5D the backside layout 539R_5D omits two instances of BM1_rte segments BM1LI and BV0 contact structures. Although XOR / XNR 549B is not as fast as XOR / XNR 594A, the EUV mask used to produce the XOR / XOR cell region representative of XOR / XNR 594B and based on the frontside layout 539F_5E and the backside layout 539R_5F is two less than the EUV mask used to produce the XOR / XOR cell region representative of XOR / XNR 594A and based on the frontside layout 539F_5C and the backside layout 539R_5D.

[0150] FIG. 6 is a flowchart 600 of a method of fabricating a memory device according to some embodiments.

[0151] The method of flowchart 600 can be implemented, for example, according to some embodiments using EDA system 800 FIG. 8 , discussed below, and IC fabrication system 900 FIG. 9 , discussed below. Examples of devices that can be fabricated through the method of flowchart 600 include devices based on the layout graphs disclosed herein or the like.

[0152] In FIG. 6 the middle, the method of flowchart 600 includes blocks 602-604. At block 602, a layout graph is generated, including, among other things, one or more of the layout graphs disclosed herein, a layout graph corresponding to one or more of the devices disclosed herein, or the like. Block 602 is implemented, for example, according to some embodiments using EDA system 800 FIG. 8 , discussed below. From block 602, flow proceeds to block 604.

[0153] At block 604, based on the layout map, at least one of the following is performed: (A) performing one or more photolithography exposures, or (B) fabricating one or more photolithography masks, or (C) fabricating one or more components in a layer of a device, such as a semiconductor assembly. See the discussion of IC manufacturing system 900 below FIG. 9 .

[0154] FIG. 7A is a flowchart 710A of a method of fabricating a device according to some embodiments.

[0155] Flowchart 710A is an example of block 604 of FIG. 6 . Flowchart 710A includes blocks 712-716. Flowchart 710A shows the following sequence: block 712→ block 714→ block 716. In some embodiments, other sequences of blocks 712-716 are provided FIG. 7B . The examples provided in the context of flowchart 710A assume first, second, and third orthogonal directions that are parallel to the X-axis, Y-axis, and Z-axis, respectively. The method of flowchart 710A is implemented, for example, using IC manufacturing system 900 FIG. 9 , discussed below, according to some embodiments. Examples of devices that can be fabricated by the method of flowchart 710A can include devices based on the layout maps disclosed herein or the like.

[0156] At block 712, upper active regions are formed over lower active regions, respectively, the upper active regions including a first upper active region over a first lower active region, the first upper active region and the first lower active region together representing a first cell region, and a second upper active region over a second lower active region, the second upper active region and the second lower active region together representing a second cell region, the upper active regions having a first type of dopant over the lower active regions, respectively, the lower active regions having a second type of dopant different from the first type of dopant. The first upper active region and the first lower active region together represent the first cell region. The second upper active region and the second lower active region together represent the second cell region. Examples of the first upper active region and the first lower active region include ARD1 240(2) and ARD2 242(2) of cell region 102(1) or the like, respectively. Examples of the second upper active region and the second lower active region include ARD1 240(1) and ARD2 242(1) of cell region 110(1) or the like, respectively. Examples of the first and second dopants are P-type and N-type dopants or the like, respectively. From block 714, flow proceeds to block 716. FIGS. 2A-2B FIGS. 2A-2B

[0157] ​​At block 714, a first conductor is formed in the first metallized layer (M_first), which corresponds to over the upper active region of at least the first and second cell regions. The first conductor includes: first and second M_first power grid (PG) segments over the first and second cell regions and correspondingly configured for a first reference voltage; first M_first routing segments over the first cell region, correspondingly aligned with a first number Q1 of M_first routing tracks and configured for a corresponding routing signal; and second M_first routing segments over the second cell region, correspondingly aligned with a second number Q2 of M_first routing tracks and configured for a corresponding routing signal, the second number Q2 being less than the first number Q1 such that Q2 < Q1.

[0158] With regard to block 714, examples of the M_first layer are FIGS. 1A-1B the MET0 layer 118 of FIG. 1, FIGS. 2A-2B the MET0 layer 218 of FIG. 2, or the like.

[0159] Examples of the first and second M_first PG segments include FIG. 1A the M0_PG segments 124(1) and 124(2) of FIG. 1 configured for a first reference voltage (e.g., VSS), FIG. 2A the M0_PG segments 224(1) and 224(2) of FIG. 2 configured for a first reference voltage (e.g., VSS), or the like.

[0160] Examples of the first routing tracks are FIG. 1A the a routing tracks a1-a5 of FIG. 1, or the like.

[0161] Examples of the first M_first routing segments over the first cell region include FIG. 1A the M0 rte segments 126(1)-126(3) aligned with the a tracks a1-a3 for Q1 = 3, FIGS. 2A-2B the M0 rte segments 226(1)-226(3) of FIG. 2, or the like.

[0162] Examples of the second M_first routing segments over the second cell region include FIG. 1A the M0 rte segments 126(4)-126(5) aligned with the a tracks a4-a5 for Q2 = 2 (where (Q2 = 2) < (Q1 = 3)), FIGS. 2A-2B the M0 rte segments 226(4)-226(5) of FIG. 2, or the like.

[0163] Starting from block 714, the flow proceeds to block 716. At block 716, a second conductor is formed in a metallized first buried layer (BM_first layer), which corresponds to the lower active region below at least the first and second cell regions. The second conductor includes: first and second BM_first PG segments configured under the first and second cell regions and corresponding to a second reference voltage; a BM_first wiring segment under the first cell region, which is aligned with a third quantity Q3 of BM_first wiring traces and configured for a corresponding wiring signal; and a second BM_first wiring segment under the second cell region, which is aligned with a fourth quantity Q4 of BM_first wiring traces and configured for a corresponding wiring signal, wherein the fourth quantity Q4 is less than the third quantity Q3, such that Q4 < Q3.

[0164] Regarding square 716, the example for the first layer of BM_ is: FIGS. 1A-1B BMET0 layer 122, FIGS. 2A-2B 222 or similar.

[0165] Examples of the first and second BM_first PG segments include those configured for a second reference voltage (e.g., VDD). FIG. 1A BM0_PG segment 128(1) and BM0_PG segment 128(2) are configured for a second reference voltage (e.g., VDD). FIGS. 2A-2B BM0_PG segment 228(1) and BM0_PG segment 228(2) or similar.

[0166] An example of the second wiring trajectory is... FIG. 1A The β wiring trajectory β1-β3 or similar.

[0167] Examples of the first BM_first wiring segment under the first unit region include: FIG. 1A The BM0_rte segment 130(1)-130(2) is aligned with the β orbitals β1-β2 of Q3=2 accordingly. FIGS. 2A-2B BM0_rte segment 230(1)-230(2) or similar.

[0168] Examples of the second BM_first wiring segment under the second unit region include FIG. 1A The BM0_rte segment 130(3) is aligned with the β orbital β3 corresponding to Q4=1 (where (Q4=1)<(Q3=2)). FIGS. 2A-2B BM0_rte segment 230(3) or similar.

[0169] In some embodiments, the flow sequence in flowchart 710A is described as forming a front layer before the back layer. An example of a front layer is... FIG. 1B The front side of 139F_1B, FIGS. 2A-2Bfront side 239F or the like in FIG. 2B. FIG. 1B back side 139R_1B in FIG. 1A, FIGS. 2A-2B back side 239R in FIG. 2B, etc.

[0170] FIG. 7B is a flowchart 710B of a method of fabricating a device according to some embodiments.

[0171] Flowchart 710B is similar to flowchart 710A of FIG. 7A in that, for example, flowchart 710B includes the same blocks as flowchart 710, i.e., blocks 712-716. Flowchart 710B is different from flowchart 710A in that flowchart 710B shows a different flow order through blocks 712-716 compared to the order shown in flowchart 710A.

[0172] In FIG. 7B flowchart 710B shows the following sequence: block 712 -> block 716 -> block 716. In some embodiments, the order of flowchart 710B is described as forming the backside layer before the frontside layer.

[0173] FIG. 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0174] In some embodiments, EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, EDA system 800 is a general purpose computing device that includes a hardware processor 802 and a non-transitory, computer-readable storage medium 804. Storage medium 804 is encoded (i.e., stores) computer program code 806, i.e., a set of executable instructions. Execution of instructions 806 by hardware processor 802 represents (at least in part) an EDA tool implementing some or all of the methods disclosed herein, e.g., a method of generating a layout, a method of generating a layout such as disclosed herein or a layout corresponding to a device disclosed herein, or the like, according to one or more embodiments (hereinafter, referred to as the process and / or method).

[0175] Storage medium 804 stores, among other things, a layout 811, e.g., a layout disclosed herein or the like.

[0176] The processor 802 is electrically coupled via the bus 808 to a computer readable storage medium 804. The processor 802 is also electrically coupled to an I / O interface 810 via the bus 808. A network interface 812 is also electrically connected to the processor 802 via the bus 808. The network interface 812 connects the processor 802 and the computer readable storage medium 804 to an external component via a network 814, such that the processor 802 and the computer readable storage medium 804 can connect to external components via the network 814. The processor 802 is configured to execute computer program code 806 encoded in the computer readable storage medium 804, such that the system 800 is operable to perform some or all of the processes and / or methods described. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0177] In one or more embodiments, the computer readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and / or an optical disc. In one or more embodiments using optical discs, the computer readable storage medium 804 includes a compact disc-read only memory (CD-ROM), a compact disk-read / write (CD-R / W) and / or a digital video disc (DVD).

[0178] In one or more embodiments, the storage medium 804 stores computer program code 806 configured to cause the system 800 (where such execution represents (at least in part) an EDA tool) to be operable to perform some or all of the processes and / or methods described. In one or more embodiments, the storage medium 804 also stores information that facilitates the performance of some or all of the processes and / or methods described. In one or more embodiments, the storage medium 804 stores a standard cell library 807 including such standard cells disclosed herein. In some embodiments, the storage medium 804 stores one or more layout maps 811.

[0179] EDA system 800 includes I / O interface 810. I / O interface 810 is coupled to external circuits. In one or more embodiments, I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for communicating information and instructions to processor 802.

[0180] EDA system 800 also includes network interface 812 coupled to processor 802. Network interface 812 allows system 800 to communicate with network 814 to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface (e.g., BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA); or a wired network interface (e.g., ETHERNET, USB, or IEEE- 1364). In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 800.

[0181] System 800 is configured to receive information through I / O interface 810. Information received through I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. The information is transmitted to processor 802 through bus 808. EDA system 800 is configured to receive information related to a user interface (UI) through I / O interface 810. This information is stored in computer-readable medium 804 as UI 842.

[0182] In some embodiments, some or all of the mentioned processes and / or methods are implemented by a stand-alone software application executed by the processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented by a software application that is part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented by a software application that is part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented by a software application used by EDA system 800. In some embodiments, the software application used by EDA system 800 is a tool such as a tool available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool. or another suitable layout generation tool.

[0183] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memory (e.g., ROM, RAM), memory cards, or one or more of the like.

[0184] FIG. 9 This is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to some embodiments.

[0185] In some embodiments, based on FIG. 6 The layout diagram generated by block 602 is implemented in IC manufacturing system 900. FIG. 6 Block 604, wherein at least one of (A) or (B) is manufactured using manufacturing system 900, (A) one or more semiconductor masks, and (B) at least one component in a layer of an early semiconductor integrated circuit. In some embodiments, IC manufacturing system 900 implements FIGS. 7A-7B The flowchart.

[0186] exist FIG. 9 In this IC manufacturing system 900, entities such as design institutes 920, masking institutes 930, and IC manufacturers / fabrication plants (“fabs”) 950) interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more design institutes 920, masking institutes 930, and IC fabs 950 are owned by a larger company. In some embodiments, two or more design institutes 920, masking institutes 930, and IC fabs 950 coexist in a shared facility and use shared resources.

[0187] A design facility (or design team) 920 produces an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC device 960 to be fabricated. The various layers combine to form various IC features. For example, a portion of the IC design layout 922 includes various IC features, such as active regions, gate terminals, source and drain, metal lines or vias within interlayer dielectrics, and openings for bond pads, to be formed in a semiconductor substrate (e.g., a silicon die) and various material layers disposed on the semiconductor substrate. Source / drain regions can be referred to individually or collectively as a source or drain, depending on the context. The design facility 920 implements appropriate design procedures to form the IC design layout 922. The design process includes one or more of logic design, physical design, or layout routing. The IC design layout 922 is represented in one or more data files having geometric pattern information. For example, the IC design layout 922 is expressed in a GDSII file format or a DFII file format.

[0188] A mask facility 930 includes data preparation 932 and mask fabrication 934. The mask facility 930 uses the IC design layout 922 to fabricate one or more masks 935 to fabricate various layers of the IC device 960 according to the IC design layout 922. The mask facility 930 performs mask data preparation 932 in which the IC design layout 922 is converted into representative data files ("RDFs"). The mask data preparation 932 provides the RDFs to the mask fabrication 934. The mask fabrication 934 includes a mask writer. The mask writer converts the RDFs into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 932 to conform to specific characteristics of the mask writer and / or requirements of the IC wafer foundry 950. In some embodiments, the mask data preparation 932 and the mask fabrication 934 are collectively referred to as mask data preparation. FIG. 9 In some embodiments, the mask data preparation 932 and the mask fabrication 934 are collectively referred to as mask data preparation.

[0189] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for imaging errors, e.g., that can be caused by diffraction, interference, other process effects, or the like. OPC adjusts IC design layout 922. In some embodiments, mask data preparation 932 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjust features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0190] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout for undergoing the OPC process using a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in the semiconductor manufacturing flow, or the like. In some embodiments, the MRC modifies the IC design layout to compensate for restrictions during mask fabrication 934, which can undo portions of the modifications performed by OPC to satisfy the mask creation rules.

[0191] In some embodiments, mask data preparation 932 includes lithography process checking (LPC) that simulates the process to be performed by IC wafer foundry 950 to manufacture IC devices 960. LPC simulates this process based on IC design layout 922 to manufacture simulated manufactured devices, such as IC devices 960. Process parameters in the LPC simulation can include parameters associated with individual processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after a simulated manufactured device is manufactured through the LPC, if the simulated device is not sufficiently close in shape to satisfy design rules, then OPC and / or MRC are repeated to further improve IC design layout 922.

[0192] The above description of mask data preparation 932 has been simplified for clarity. In some embodiments, additional features are included in mask data preparation 932, such as logic operations (LOPs), to modify the IC design layout according to fabrication rules. Additionally, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different orders.

[0193] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a set of masks 935 is fabricated based on the modified IC design layout. In some embodiments, a pattern is formed on a mask (photomask or reticle) using an e-beam or multi- e-beam mechanism based on the modified IC design layout. The mask is formed through various techniques. In some embodiments, the mask is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image- sensitive material (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque regions and passes through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using phase shift techniques. In a phase shift mask (PSM), individual features in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask is an attenuated PSM or an alternating PSM. The mask generated by mask fabrication 934 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0194] IC wafer foundry 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC wafer foundry 950 is a semiconductor foundry. For example, there can be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for inline and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry business.

[0195] IC wafer foundry 950 uses the mask(s) 935 manufactured using mask manufacturing facility 930 to fabricate IC devices 960 using fabrication tools 952. Thus, IC wafer foundry 950 fabricates IC devices 960 using, at least indirectly, IC design layout 922. In some embodiments, IC wafer foundry 950 uses mask(s) 935 to fabricate semiconductor wafer 953 to form IC devices 960. Semiconductor wafer 953 includes a silicon substrate or other appropriate substrate having material layers formed thereon. Semiconductor wafer also includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent fabrication steps).

[0196] In some embodiments, the unit area (of the device) includes: a first active region over a second active region, the first active region having a first type of dopant, the second active region having a second type of dopant different from the first type of dopant; a M_first power grid (PG) segment configured for a first reference voltage in a first layer of metallization (M_first layer) over the first active region, and a M_first routing segment aligned with a first number of M_first routing tracks; and, a BM_first PG segment configured for a second reference voltage different from the first reference voltage in the first layer of metallization (BM_first layer) under the second active region, and a BM_first routing segment aligned with a second number of BM_first routing tracks, the second number being less than the first number.

[0197] In some embodiments, the second number of BM_first routing tracks is j, where j is a positive integer; and the first number of M_first routing tracks is j+1.

[0198] In some embodiments, 1≤j.

[0199] In some embodiments, 1≤j≤2.

[0200] In some embodiments, 1≤j.

[0201] In some embodiments, j=2.

[0202] In some embodiments, an apparatus includes: a first cell region stacked on a second cell region; each of the first and second cell regions includes a first active region over a second active region, the first active region having a first type of dopant, the second active region having a second type of dopant different from the first type of dopant; in a first layer of metallization (M_first_layer) over the first active region, a segment of M_first power grid (PG) having a first reference voltage, and a segment of M_first routing corresponding in alignment to a M_first routing trace; and, in a first layer of back metallization (BM_first_layer) under the second active region, a segment of BM_first PG having a second reference voltage different from the first reference voltage, and a segment of BM_first routing corresponding in alignment to a BM_first routing trace; some of the segments of M_first routing are corresponding in alignment to a first and a second number of the M_first routing traces in the first and second cell regions, the second number being less than the first number; some of the segments of BM_first routing are corresponding in alignment to a third and a fourth number of the BM_first routing traces in the first and second cell regions, the fourth number being less than the third number.

[0203] In some embodiments, the second number of M_f first routing traces is j, where j is a positive integer; the first number of M_first routing traces is j+1; the fourth number of BM_first routing traces is k, where k is a positive integer; the third number of BM_first routing traces is k+1.

[0204] In some embodiments, k = j+1.

[0205] In some embodiments, k ≤ j.

[0206] In some embodiments, 1 ≤ j.

[0207] In some embodiments, j = 1.

[0208] In some embodiments, j = 2.

[0209] In some embodiments, the first cell region is stacked on the second cell region with respect to a first direction. The first and second cell regions represent a first instance of a stack pair; the first cell region and the second cell region are in a column extending along the first direction. The apparatus further includes other instances of the stack pair in the column.

[0210] In some embodiments, the first instance and the other instances of the stack pair are adjacent in corresponding columns, such that there is no instance of another cell region between any two instances of the stack pair.

[0211] In some embodiments, the first and second cell regions are for their corresponding first instance; and adjacent instances of the stack pair are separated by other instances of the first cell region accordingly.

[0212] In some embodiments, the first and second unit regions are respective first instances thereof; and adjacent instances of the stack pair are separated by other instances of the second unit region.

[0213] In some embodiments, the method (of forming the apparatus) comprises: forming an active region, the active region comprising an upper active region over a corresponding lower active region, the upper active region having a first type of dopant, the lower active region having a second type of dopant different from the first type of dopant. The active region comprises a first upper active region over a corresponding first lower active region, which collectively represent a first unit region; and a second upper active region over a corresponding second lower active region, which collectively represent a second unit region. Forming a first conductor in a first layer of metallization (M_first_layer) over the upper active region, the first conductor comprising first and second segments of M_first_power ground (PG) over the first and second unit regions and configured for a first reference voltage. A first segment of M_first_wiring over the first unit region, aligned with a first number of M_first_wiring tracks corresponding thereto and configured for a corresponding wiring signal, and a second segment of M_first_wiring over the second unit region, aligned with a second number of M_first_wiring tracks corresponding thereto and configured for a corresponding wiring signal, the second number being less than the first number. Forming a second conductor in a first layer of back metallization (BM_first_layer) under the lower active region, the second conductor comprising first and second segments of BM_first_PG under the first and second unit regions and configured for a second reference voltage different from the first reference voltage. A first segment of BM_first_wiring under the first unit region, aligned with a third number of BM_first_wiring tracks corresponding thereto and configured for a corresponding wiring signal, and a second segment of BM_first_wiring under the second unit region, aligned with a fourth number of BM_first_wiring tracks corresponding thereto and configured for a corresponding wiring signal, the fourth number being less than the third number.

[0214] In some embodiments, the second number of M_first_wiring tracks is j, where j is a positive integer; the first number of M_first_wiring tracks is j+1; the fourth number of BM_first_wiring tracks is k, where k is a positive integer; and the first number of BM_first_wiring tracks is k+1.

[0215] In some embodiments, k = j+1.

[0216] In some embodiments, k ≤ j.

[0217] In some embodiments, 1 ≤ j.

[0218] In some embodiments, j = 1.

[0219] In some embodiments, j = 2.

[0220] In some embodiments, the first cell region is stacked on the second cell region with respect to the first direction. Forming the active regions further includes forming a first upper active region and a first lower active region in a first location in the pillar extending along the first direction. A second upper active region and a second lower active region are formed in a second location in the pillar such that the second cell region is stacked on the first cell region; the first and second cell regions represent a first instance of a stack pair; and forming the active regions further includes forming other instances of the stack pair in the pillar.

[0221] In some embodiments, forming the active regions further includes adjacently corresponding first and other instances of the stack pair in the pillar such that there is no instance of another cell region between any two instances of the stack pair.

[0222] In some embodiments, the second cell region is a first instance thereof, and forming the active regions further includes: forming additional instances of the first cell region; and separating adjacent instances of the stack pair by positioning respective additional instances of the first cell region therebetween.

[0223] In some embodiments, the first cell region is a first instance thereof, and forming the active regions further includes: forming additional instances of the second cell region; and separating adjacent instances of a row pair by positioning respective additional instances of the second cell region therebetween.

[0224] One of ordinary skill in the art will readily see that one or more of the disclosed embodiments realize one or more of the above advantages. After reading the foregoing specification, one of ordinary skill in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments, as broadly disclosed herein. It is therefore intended that the protection granted by Letters Patent hereon be limited only by the definition containing the limits as expressed in the claims hereon and equivalents thereof.

Claims

1. A unit region of a semiconductor device, characterized by, The cell region comprises: a first active region over a second active region, the first active region having a first type of dopant, the second active region having a second type of dopant different from the first type of dopant; in a first layer of metallization over the first active region: M_first power segment configured for a first reference voltage; and M_first routing segment aligned with a first number of M_first routing tracks; and in a first layer of metallization under the second active region: BM_first power segment configured for a second reference voltage different from the first reference voltage; and BM_first routing segment aligned with a second number of BM_first routing tracks, the second number being less than the first number.

2. The cell region of the semiconductor device of claim 1, wherein: the second number of the BM_first routing tracks is j, where j is a positive integer; and the first number of the M_first routing tracks is j+1.

3. The unit region of a semiconductor device according to claim 2, wherein 1≤j。 4. A semiconductor device, characterized by comprising: comprises: a first cell region stacked on a second cell region; each of the first cell region and the second cell region comprises: a first active region having a first type of dopant and a second active region having a second type of dopant different from the first type of dopant; in a first layer of metallization over the first active region: M_first power segment having a first reference voltage; and M_first routing segment correspondingly aligned with M_first routing tracks; and in a first layer of metallization under the second active region: BM_first power segment having a second reference voltage different from the first reference voltage; and BM_first routing segment correspondingly aligned with BM_first routing tracks; some of the M_first routing segments are correspondingly aligned with a first number and a second number of the M_first routing tracks in the first cell region and the second cell region, the second number being less than the first number; and some of the BM_first routing segments are correspondingly aligned with a third number and a fourth number of the BM_first routing tracks in the first cell region and the second cell region, the fourth number being less than the third number.

5. The semiconductor device of claim 4, wherein: the second number of the M_first routing tracks is j, where j is a positive integer; the first number of the M_first routing tracks is j+1; the fourth number of the BM_first routing tracks is k, where k is a positive integer; and the third number of the BM_first routing tracks is k+1.

6. The semiconductor device according to claim 5, wherein k < j.

7. The semiconductor device according to claim 4, wherein the first cell region is stacked on the second cell region with respect to a first direction; the first cell region and the second cell region represent a first instance of a stack pair; the first cell region and the second cell region are in a column extending in the first direction; and the device further comprises other instances of the stack pair in the column.

8. The semiconductor device of claim 7, wherein: The first instance and other instances of the stack pair correspondingly adjoin in the column, such that there is no instance of another cell region between any two instances of the stack pair.

9. The semiconductor device according to claim 7, wherein The first cell region and the second cell region are corresponding first instances thereof; and Adjacent instances of the stack pair are respectively separated by other instances of the first cell region.

10. The semiconductor device according to claim 7, wherein The first cell region and the second cell region are corresponding first instances thereof; and Adjacent instances of the stack pair are respectively separated by other instances of the second cell region.

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