ESD structure with high reliability

Abstract

The utility model provides an ESD structure with high reliability. The ESD structure comprises a GGPMOS tube M0, a GGNMOS tube M1, a GGNMOS tube M2, a resistor R1, a resistor R0 and a resistor R2, wherein the GGPMOS tube M0 and the GGNMOS tube M1 are respectively connected with a PAD layer; the GGNMOS tube M2 is connected in parallel with the tube M1; according to the utility model, both the GND and the VDD are provided with ESD (Electro-Static Discharge) discharge paths, the ESD test can pass through 4KV voltage at most through a tape-out test, the area is saved as much as possible under the permission of a process design rule, and the process time and the economic cost of the traditional ESD design are saved; the chip can be well protected from being influenced by static electricity, and the probability of failure, locking and damage of the chip caused by the static electricity is greatly reduced; according to the utility model, the stability of the ESD structure is ensured, and the damage or failure of the chip caused by electrostatic discharge in the manufacturing, transportation and use processes of the chip is greatly reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of electricity, specifically relates to a high reliability ESD structure. BACKGROUND

[0002] ESD is one of the most important reliability problems in MOS integrated circuits. High-density integrated circuit devices have the characteristics of short line spacing, thin lines, high integration, fast transportation speed, low power and high input impedance, thus leading to the sensitivity of such devices to static electricity, which is called static sensitive device. The energy of static discharge has little effect on traditional electronic components, which is not easy to detect, but these high-density integrated circuit components may fail or cause the "soft breakdown" phenomenon that is difficult to be detected by people, resulting in device lock, reset, data loss and unreliable impact on normal operation of the device, reducing the reliability of the device, and even causing damage.

[0003] The loss caused by ESD in the integrated circuit industry is a very serious problem. According to statistics, the loss caused by ESD in the integrated circuit work is as high as 25%, so the layout of an ESD is very important in the integrated circuit layout.

[0004] Due to the huge loss caused by ESD to the integrated circuit industry, the ESD protection problem in integrated circuits has attracted more and more attention. The conventional ESD design has the following three defects

[0005] 1. Only one GGNMOS tube is used for ESD discharge to GND;

[0006] 2. The highest voltage that can be passed through the traditional ESD structure is 2KV;

[0007] 3. The design of the traditional ESD protection circuit is a design-flow-test-adjust design-flow-test design mode, which has a long cycle and high cost; SUMMARY

[0008] The utility model discloses in order to solve the problem of ESD structure reliability, provide a kind of high reliability ESD structure, there is ESD discharge passage to GND and to VDD, after flow piece test, this ESD test can pass through the highest voltage 4KV, under the design rule allowed in process, try to save area, and save the process time and economic cost of traditional ESD design;It can very good protect chip from static electricity, greatly reduce the probability of chip failure, lock, damage caused by static electricity;The utility model not only guarantees the stability of ESD structure, greatly reduces the chip damage or failure caused by electrostatic discharge in the process of manufacturing, transportation and use.

[0009] The utility model provides a high reliability's ESD structure, including GGPMOS pipe M0, GGNMOS pipe M1 with PAD layer is connected respectively, GGNMOS pipe M2 with pipe M1 parallel connection, the resistance R1 of connecting in pipe M0 gate and source, the resistance R0 of connecting in pipe M1 gate and source and the resistance R2 of connecting in pipe M2 drain and pipe M1 drain,

[0010] Pipe M0 drain and PAD layer are connected, and the source is connected with one end of resistance R1, and then the power supply voltage VDD is connected, pipe M1 drain and PAD layer are connected, and the source is connected with one end of resistance R0, and then the ground is connected, pipe M2 drain is connected between resistance R2 and output, and the gate is connected with the source, and then the ground is connected,

[0011] The resistance R0 and resistance R1 resistance value are same, and the size of pipe M2 is less than the size of pipe M0.

[0012] The utility model discloses a high reliability's ESD structure, as preferred mode, pipe M0 is used to the ESD discharge of power supply voltage VDD, and pipe M1 is used to the ESD discharge of GND,

[0013] The resistance R0 and resistance R1 resistance value are same, and the size of pipe M2 is less than the size of pipe M0.

[0014] The utility model discloses a high reliability's ESD structure, as preferred mode, the resistance R2 resistance value is 300Ω.

[0015] The utility model discloses a high reliability's ESD structure, as preferred mode, the size of pipe M2 is 1 / 6 of the size of pipe M0.

[0016] The utility model discloses a high reliability's ESD structure, as preferred mode, the size of pipe M2 is 1 / 4 of the size of pipe M1.

[0017] The utility model discloses a high reliability's ESD structure, as preferred mode, in layout structure, pipe M1 and pipe M2 share isolated ground ring.

[0018] The utility model has the following advantages:

[0019] (1) the utility model has the ESD discharge passage to GND and to VDD, and after wafer test, this ESD test can pass through 4KV voltage at most, under the design rule of process, saves the area as far as possible, and saves the process time and economic cost of traditional ESD design.

[0020] (2) the utility model can protect the chip from static electricity very well, and the probability of failure, lock, damage of chip caused by static electricity is greatly reduced.

[0021] (3)The utility model discloses a stable ESD structure, greatly reduce the chip in manufacturing, transportation, and use process because of static electricity discharge leads to chip damage or failure. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a circuit diagram of the ESD structure with high reliability;

[0023] Figure 2 It is a layout of the ESD structure with high reliability;

[0024] Figure 3 It is an enlarged view of the layout structure of the lower half GGNMOS of the ESD structure with high reliability;

[0025] Figure 4 It is an enlarged view of the layout structure of the upper half GGPMOS of the ESD structure with high reliability. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments.

[0027] Embodiment 1

[0028] As Figure 1 shown, an ESD structure with high reliability, layout circuit structure reference Figures 2 to 4 , from this drawing M1 is GGNMOS, the ESD discharge to gnd, M0 is GGPMOS, the ESD discharge to vdd, generally M1's gate can be directly connected to GND, but when ESD occurs, not every NMOS "finger" can be turned on, so the effective voltage withstand value of ESD protection circuit is determined by the several NMOS "fingers" that start to conduct. In order to avoid this situation, improve the protection ability of ESD device, can add a resistance R0 with the resistance value equal to 1k ohm between M1 gate and ground, and a 1k ohm resistance R1 is also added between the gate end of M0 and vdd. This function is also to ensure that all "fingers" can be turned on at the same time, and increase the current discharge capacity of ESD.

[0029] Only primary ESD protection, when large ESD current, the tube in the circuit is still possible to be broken down, in order to avoid this situation, a small size GGNMOS can be added near the input receiving end for ESD protection, which is used to clamp the input receiving end gate voltage, Figure 2 The size of M2 in the middle is 1 / 6 of M0.

[0030] Reference Figure 3This is the lower half of the ESD GGNMOS: M1, and the resistance between the gate and source R0 and the next stage GGNMOS: M2, R2 is the voltage dividing resistance of the ESD. Figure 4 This is the upper half of the ESD GGNMOS: M0, and the resistance between the gate and source R1.

[0031] As many vias and contacts as possible are made when connecting the source end and the drain end, so that the discharge capacity of the ESD current can be improved.

[0032] The above is only the preferred specific implementation of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. An ESD structure with high reliability, characterized in that: The GGPMOS tube M0 and the GGNMOS tube M1 are connected with the PAD layer respectively, the GGNMOS tube M2 is connected in parallel with the tube M1, the resistance R1 is connected between the gate and the source of the tube M0, the resistance R0 is connected between the gate and the source of the tube M1, and the resistance R2 is connected between the drain of the tube M2 and the drain of the tube M1; The drain of the tube M0 is connected with the PAD layer, the source is connected with one end of the resistance R1 and then connected with the power voltage VDD, the drain of the tube M1 is connected with the PAD layer, the source is connected with one end of the resistance R0 and then grounded, the drain of the tube M2 is connected between the resistance R2 and the output, and the gate is connected with the source and then grounded; The resistance R0 has the same resistance value as the resistance R1, and the size of the tube M2 is smaller than the size of the tube M0.

2. The ESD structure of claim 1, wherein: The tube M0 is used for ESD discharge of the power voltage VDD, and the tube M1 is used for ESD discharge of GND. The resistance value of the resistance R0 and the resistance value of the resistance R1 are both 1kΩ.

3. The ESD structure of claim 1, wherein: The resistance value of the resistance R2 is 300Ω.

4. The ESD structure of claim 1, wherein: The size of the tube M2 is 1 / 6 of the size of the tube M0.

5. The ESD structure of claim 4, wherein: The size of the tube M2 is 1 / 4 of the size of the tube M1.

6. The ESD structure of claim 1, wherein: In the layout structure, the tube M1 and the tube M2 share the isolated ground ring.

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