Display device

Abstract

A display device is provided. The display device includes: a substrate; a first sub-pixel electrode over the substrate; a conductive bank layer disposed on the first sub-pixel electrode and including a first opening overlapping the first sub-pixel electrode; a first intermediate layer overlapping the first sub-pixel electrode and contacting the first sub-pixel electrode through the first opening of the conductive bank layer; and an opposing electrode covering the first intermediate layer and the conductive bank layer. The first intermediate layer includes a first portion at a center of the first intermediate layer and a second portion extending peripherally from the first portion. The upper surface of the second portion includes an inclined surface inclined toward the upper surface of the substrate with respect to the extending direction.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0012446, filed on January 26, 2024, and all benefits therefrom, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. BACKGROUND

[0004] A display device can visually display data. The display device can display an image using a light emitting diode. The display device is used for various purposes, and various attempts have been made to design a display device having improved quality. SUMMARY

[0005] One or more embodiments include a display device capable of displaying a high-quality image and a method of manufacturing the display device. However, such a technical problem is an example, and the present disclosure is not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description, or can be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments, a display device includes a substrate, a first sub-pixel electrode above the substrate, a conductive bank barrier disposed on the first sub-pixel electrode and including a first opening overlapping the first sub-pixel electrode, a first intermediate layer overlapping the first sub-pixel electrode and contacting the first sub-pixel electrode through the first opening of the conductive bank barrier, and an opposite electrode covering the first intermediate layer and the conductive bank barrier, wherein the first intermediate layer includes a first portion at a center of the first intermediate layer and a second portion extending from the first portion at a periphery, and an upper surface of the second portion includes an inclined surface inclined toward an upper surface of the substrate with respect to an extension direction of the second portion.

[0008] The inclined surface of the second portion can be inclined at an angle of about 15° to about 45° with respect to the upper surface of the substrate.

[0009] A vertical distance from the upper surface of the substrate to an upper surface of the first portion of the first intermediate layer can be greater than a vertical distance from the upper surface of the substrate to the upper surface of the second portion of the first intermediate layer.

[0010] The display device can further include an insulating layer disposed between a peripheral portion of the first sub-pixel electrode and the conductive bank barrier layer and including an opening overlapping the first opening.

[0011] At least a portion of the first intermediate layer can be disposed on an upper surface of the insulating layer.

[0012] A width of the first opening of the conductive bank barrier layer can be greater than a width of the opening of the insulating layer.

[0013] An edge of a second portion of the first intermediate layer can be in contact with the conductive bank barrier layer.

[0014] An edge of a second portion of the first intermediate layer can be adjacent to the conductive bank barrier layer.

[0015] The counter electrode can continuously cover at least a portion of an upper surface of the conductive bank barrier layer, at least a portion of a side surface of the conductive bank barrier layer, and an upper surface of the first intermediate layer.

[0016] The display device can further include a second sub-pixel electrode over the substrate, and a second intermediate layer overlapping the second sub-pixel electrode and contacting the second sub-pixel electrode through a second opening of the conductive bank barrier layer, wherein the counter electrode can continuously cover the first intermediate layer, the conductive bank barrier layer, and the second intermediate layer.

[0017] According to one or more embodiments, a method of manufacturing a display device includes forming a first sub-pixel electrode over a substrate, forming a conductive bank barrier layer including a first opening overlapping the first sub-pixel electrode, forming a first intermediate layer overlapping the first sub-pixel electrode and contacting the first sub-pixel electrode through the first opening of the conductive bank barrier layer, and forming a counter electrode covering the first intermediate layer and the conductive bank barrier layer, wherein the first intermediate layer includes a first portion at a center of the first intermediate layer and a second portion extending from the first portion in a periphery, and an upper surface of the second portion includes an inclined surface inclined toward an upper surface of the substrate with respect to an extension direction of the second portion.

[0018] The method can further include forming an insulating layer disposed between a peripheral portion of the first sub-pixel electrode and the conductive bank barrier layer and including an opening overlapping the first opening, wherein a width of the first opening of the conductive bank barrier layer can be greater than a width of the opening of the insulating layer.

[0019] The forming of the conductive bank can include forming a preliminary conductive bank including a first conductive layer and a second conductive layer on the first conductive layer, and removing the second conductive layer of the preliminary conductive bank, wherein the second conductive layer can include a tip extending in a direction from a point where a side surface of the first conductive layer intersects a bottom surface of the second conductive layer.

[0020] The removing of the second conductive layer can be performed after the forming of the first intermediate layer.

[0021] The forming of the first intermediate layer can include forming the first intermediate layer and a first dummy intermediate layer, forming a first sacrificial layer on the first intermediate layer and a first dummy sacrificial layer on the first dummy intermediate layer, forming a first photoresist pattern overlapping the first sub-pixel electrode, etching the first dummy intermediate layer and the first dummy sacrificial layer using the first photoresist pattern as a mask, and removing the first photoresist pattern.

[0022] The method can further include removing the first sacrificial layer.

[0023] The method can further include forming a second sub-pixel electrode over the substrate, and forming a second intermediate layer overlapping the second sub-pixel electrode and contacting the second sub-pixel electrode through a second opening of the conductive bank, wherein the counter electrode can continuously cover the first intermediate layer, the conductive bank, and the second intermediate layer.

[0024] The forming of the second intermediate layer can include forming the second intermediate layer and a second dummy intermediate layer, forming a second sacrificial layer on the second intermediate layer and a second dummy sacrificial layer on the second dummy intermediate layer, forming a second photoresist pattern overlapping the second sub-pixel electrode, etching the second dummy intermediate layer and the second dummy sacrificial layer using the second photoresist pattern as a mask, and removing the second photoresist pattern.

[0025] The method can further include removing the second sacrificial layer, wherein the removing of the second sacrificial layer can be performed simultaneously with the removing of the first sacrificial layer.

[0026] An edge of a second portion of the first intermediate layer can be in contact with or adjacent to the conductive bank. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] FIG. 1A and FIG. 1B is a schematic perspective view of a display device according to an embodiment;

[0029] FIG. 2 is a schematic equivalent circuit diagram of a light emitting diode corresponding to one of the sub-pixels of a display device according to an embodiment and of a sub-pixel circuit connected to the relevant light emitting diode;

[0030] FIG. 3 is a schematic cross-sectional view of a display device according to an embodiment and illustrates a structure corresponding to a first light emitting diode provided to the display device;

[0031] FIG. 4 is a schematic cross-sectional view of a stack structure of a first light emitting diode included in a display device according to an embodiment;

[0032] FIG. 5 is a schematic cross-sectional view of a display device according to another embodiment;

[0033] FIG. 6 is a plan view of a display device according to an embodiment;

[0034] FIG. 7 is a cross-sectional view of a display device according to an embodiment taken along the line X-X’ of FIG. 6 ; and

[0035] FIG. 8A to FIG. 8J is a schematic cross-sectional view corresponding to a process of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0036] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are described herein by referring to the drawings, only in an effort to explain aspects of the present description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0037] Since the present disclosure allows various changes and numerous embodiments, certain embodiments will be illustrated in the drawings and described in the written description in detail. The effects and features of the present disclosure and methods for achieving them will be clarified by referring to the embodiments described in detail herein with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0038] Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout and repetitive description thereof is omitted.

[0039] Although terms such as "first" and "second" can be used to describe various elements, the elements are not limited to the above terms. The above terms are used to distinguish one element from another.

[0040] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0041] It will be understood that the terms "comprises" and / or "comprising," as used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0042] It will be further understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly on the other layer, region, or element, or intervening layers, regions, or elements can also be present. That is, for example, one layer, region, or element can intervene between a layer, region, or element that is "on" another layer, region, or element.

[0043] For ease of explanation, the size of elements in the drawings can be exaggerated or reduced. As an example, the size and thickness of each element illustrated in the drawings are arbitrarily indicated, and thus the present disclosure is not necessarily limited thereto.

[0044] In cases where a specific embodiment can be implemented differently, a specific process sequence can be performed in a different order from the described sequence. As an example, two processes described in succession can be performed substantially simultaneously or in reverse order.

[0045] In this specification, "A and / or B" means A or B, or A and B. In this specification, "at least one of A and B" means A or B, or A and B.

[0046] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, it can be "directly connected" to the other layer, region, or element, or can be "indirectly connected" to the other layer, region, or element, with yet another layer, region, or element interposed therebetween. For example, it will be understood that when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be "directly electrically connected" to the other layer, region, or element, or can be "indirectly electrically connected" to the other layer, region, or element, with yet another layer, region, or element interposed therebetween.

[0047] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different orientations that are not perpendicular to each other.

[0048] As used herein, the term "about" or "approximately," includes the stated value and includes a reasonable range of deviation that a person of ordinary skill in the art would determine to be a suitable tolerance range for the particular value being discussed. For example, the term "about" can mean within one or more standard deviations of the stated value or within ± 30%, 20%, 10%, 5%.

[0049] As used herein, the term "substantially" means approximately or virtually. The term "substantially equal" means approximately equal or virtually equal. The term "substantially the same" means approximately the same or virtually the same. The term "substantially perpendicular" means approximately perpendicular or virtually perpendicular. The term "substantially parallel" means approximately parallel or virtually parallel.

[0050] FIG. 1A and FIG. 1B is a schematic perspective view of a display device 1 according to an embodiment.

[0051] Referring to FIG. 1A and FIG. 1B , the display device 1 can include a display area DA and a non-display area NDA outside the display area DA. The display area DA can be configured to display an image by the sub-pixels P arranged in the display area DA. The non-display area NDA is arranged outside the display area DA and does not display an image. The non-display area NDA can completely surround the display area DA. A driver or the like configured to provide an electrical signal or power to the display area DA can be arranged in the non-display area NDA. A pad can be arranged in the non-display area NDA, to which an electronic element or a printed circuit board can be electrically connected.

[0052] Although FIG. 1A In an embodiment, the display area DA has a polygonal (e.g., quadrangular) shape in which a length of the polygonal shape in the x direction is less than a length of the polygonal shape in the y direction, but FIG. 1B In another embodiment, the display area DA has a polygonal (e.g., quadrangular) shape in which a length of the polygonal shape in the y direction is less than a length of the polygonal shape in the x direction. Although FIG. 1A and FIG. 1B shows that the display area DA has an approximately quadrangular shape, but the present disclosure is not limited thereto. In another embodiment, the display area DA can have various shapes such as an N-gon (where N is a natural number of 3 or more), a circular shape, or an elliptical shape. Although FIG. 1A and FIG. 1B In the embodiments illustrated in and, the display area DA has a shape in which a corner of the display area DA includes a vertex at which straight lines intersect, but in another embodiment, the display area DA can have a polygonal shape having a rounded corner.

[0053] Hereinafter, for convenience of description, although a case in which the display apparatus 1 is a smartphone is described, the display apparatus 1 according to the disclosure is not limited thereto. The display apparatus 1 can be applied to various products including a television, a notebook computer, a monitor, a billboard, an Internet of Things (IoT) apparatus, and portable electronic apparatuses including a mobile phone, a smartphone, a tablet Personal Computer (PC), a mobile communication terminal, an electronic organizer, an electronic book, a Portable Multimedia Player (PMP), a navigation, and an Ultra-Mobile Personal Computer (UMPC). In some aspects, the display apparatus 1 according to an embodiment can be applied to wearable devices including a smart watch, a watch phone, a glasses-type display, and a Head-Mounted Display (HMD). In some aspects, in an embodiment, the display apparatus 1 can be applied to a display screen in a car instrument panel, a center panel for a car or a Center Information Display (CID) arranged on an instrument panel, an interior mirror display replacing a side mirror of a car, and a display of an entertainment system arranged on a back side of a front seat of a car for a rear seat passenger.

[0054] FIG. 2 A schematic equivalent circuit diagram of a Light Emitting Diode (LED) corresponding to one of sub-pixels of a display apparatus according to an embodiment and a sub-pixel circuit connected to the related Light Emitting Diode (LED).

[0055] Reference FIG. 2 The Light Emitting Diode (LED) can be electrically connected to the sub-pixel circuit PC, and the sub-pixel circuit PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. A sub-pixel electrode (e.g., an anode) of the Light Emitting Diode (LED) can be electrically connected to the first transistor T1, and an opposite electrode (e.g., a cathode) can be electrically connected to an auxiliary line VSL and can receive a voltage corresponding to a common voltage ELVSS through the auxiliary line VSL.

[0056] The second transistor T2 is configured to transmit a data signal Dm to the first transistor T1 according to a scan signal Sgw input through a scan line GW, in which the data signal Dm is input through a data line DL.

[0057] The storage capacitor Cst can be connected to the second transistor T2 and a driving voltage line PL, and is configured to store a voltage corresponding to a difference between a voltage transmitted from the second transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0058] The first transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and is configured to control a driving current ID according to a voltage stored in the storage capacitor Cst. d The driving current ID dA driving voltage flows from the driving voltage line PL to the light emitting diode LED. The light emitting diode LED can be configured to emit light having a color corresponding to the driving current I d corresponding to a preset luminance.

[0059] Although reference is made to FIG. 2 the sub-pixel circuit PC is described as including two transistors and one storage capacitor, the present disclosure is not limited thereto. In another embodiment, the sub-pixel circuit PC can include three or more transistors and two or more storage capacitors.

[0060] FIG. 3 is a schematic cross-sectional view of a display apparatus 1 according to an embodiment, and illustrates a cross-sectional structure corresponding to a first light emitting diode LED 1 provided to the display apparatus 1. FIG. 4 is a schematic cross-sectional view of a stack structure of a first light emitting diode LED 1 included in a display apparatus 1 according to an embodiment. In some aspects, FIG. 5 is a schematic cross-sectional view of a display apparatus 1 according to another embodiment, and illustrates FIG. 3 a modified embodiment of

[0061] Reference is made to FIG. 3 , the display area DA of the display apparatus 1 can include the first light emitting diode LED 1 disposed above the substrate 100. The first light emitting diode LED 1 can include a first sub-pixel electrode 1210, a first intermediate layer 1220 on the first sub-pixel electrode 1210, and an opposite electrode 1230 on the first intermediate layer 1220. The first light emitting diode LED 1 can be configured to emit light of a first color.

[0062] The substrate 100 can include glass or a polymer resin. In an embodiment, the substrate 100 can have a structure in which a base layer including a polymer resin and an isolation layer are stacked. The polymer resin can include, for example, polyether sulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, cellulose triacetate (TAC), cellulose acetate propionate (CAP), or the like.

[0063] The first light emitting diode LED 1 can be electrically connected to a first sub-pixel circuit PC1 disposed between the substrate 100 and the first light emitting diode LED 1. As described herein with reference to FIG. 2 , the first sub-pixel circuit PC1 can include a transistor and a storage capacitor. In an embodiment, FIG. 3 illustrates a first transistor T1 and a storage capacitor Cst of the first sub-pixel circuit PC1.

[0064] A buffer layer 110 can be provided between the substrate 100 and the first transistor T1. The buffer layer 110 can prevent impurities from penetrating a semiconductor layer of a transistor (e.g., the first transistor T1). The buffer layer 110 can include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and include a single layer or a plurality of layers including the described inorganic insulating material.

[0065] The first transistor T1 can include a first semiconductor layer 120 and a first gate electrode 140, where the first semiconductor layer 120 is on the buffer layer 110, and the first gate electrode 140 overlaps a channel region of the first semiconductor layer 120. The first semiconductor layer 120 can include a silicon-based semiconductor material, such as polysilicon. Alternatively or additionally, the first semiconductor layer 120 can include an oxide-based semiconductor material. The first semiconductor layer 120 can include a channel region, a first region, and a second region, the first region and the second region being on two opposite sides of the channel region. The first region and the second region are regions including a higher impurity concentration than an impurity concentration of the channel region or are conductive regions. One of the first region and the second region can correspond to a source region, and the other can correspond to a drain region.

[0066] A gate insulating layer 130 can be provided between the first semiconductor layer 120 and the first gate electrode 140. The gate insulating layer 130 can include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and include a single layer or a plurality of layers including the described inorganic insulating material.

[0067] A first interlayer insulating layer 150 can be provided on the first gate electrode 140. The first interlayer insulating layer 150 can include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and include a single layer or a plurality of layers including the described inorganic insulating material.

[0068] A source electrode 160 and a drain electrode 162 can be electrically connected to a source region and a drain region of the first semiconductor layer 120, respectively. A first organic insulating layer 170 can be provided on the source electrode 160 and the drain electrode 162. The first organic insulating layer 170 can include an organic insulating material. The storage capacitor Cst can include at least two capacitor electrodes overlapping each other. In the embodiment described with reference to FIG. 3 The first capacitor electrode (not illustrated) can be on the same layer as the first semiconductor layer 120, the second capacitor electrode (not illustrated) can be on the same layer as the first gate electrode 140, and / or the third capacitor electrode (not illustrated) can be on the same layer as the drain electrode 162, in the embodiment described. Each of the source electrode 160 and the drain electrode 162 can include aluminum (Al), copper (Cu), and / or titanium (Ti), and include a single layer or a plurality of layers including the described material.

[0069] The connection metal CM can be disposed on the first organic insulating layer 170, and the first sub-pixel electrode 1210 of the first light emitting diode LED1 can be connected to the connection metal CM through a contact hole formed in the second organic insulating layer 180. The connection metal CM can electrically connect the first sub-pixel circuit PC1 to the first sub-pixel electrode 1210 of the first light emitting diode LED1. The first organic insulating layer 170 can include an organic insulating material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). The connection metal CM can include aluminum (Al), copper (Cu), and / or titanium (Ti), and include a single layer or multiple layers including the described materials.

[0070] In another embodiment, the first sub-pixel electrode 1210 of the first light emitting diode LED1 can be directly connected to the first sub-pixel circuit PC1. In another embodiment, a plurality of connection metals disposed on different layers can be disposed between the first sub-pixel electrode 1210 of the first light emitting diode LED1 and the first sub-pixel circuit PC1. The first sub-pixel electrode 1210 of the first light emitting diode LED1 can be electrically connected to the first sub-pixel circuit PC1 through the plurality of connection metals.

[0071] The first sub-pixel electrode 1210 of the first light emitting diode LED1 can be disposed on the second organic insulating layer 180. The second organic insulating layer 180 can include an organic insulating material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0072] The first sub-pixel electrode 1210 can include a metal and / or a conductive oxide. As an example, the first sub-pixel electrode 1210 can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a layer under and / or on the reflective layer including ITO, IZO, ZnO, or In2O3. In an embodiment, the first sub-pixel electrode 1210 can have a structure of an ITO layer, an Ag layer, and an ITO layer stacked in order.

[0073] The conductive dam layer 300 can be disposed on the first sub-pixel electrode 1210, and the insulating layer 190 between the conductive dam layer 300 and the first sub-pixel electrode 1210 (e.g., a peripheral portion of the first sub-pixel electrode 1210). The conductive dam layer 300 can include a first opening 300OP1 through the conductive dam layer 300 in a thickness direction of the conductive dam layer 300. The first opening 300OP1 of the conductive dam layer 300 can overlap the first sub-pixel electrode 1210.

[0074] The conductive bank barrier 300 can be electrically insulated from the first sub-pixel electrode 1210 by the insulating layer 190. The insulating layer 190 can be formed to completely cover the substrate 100. As an example, the insulating layer 190 can be in direct contact with the upper surface of the outer portion of the first sub-pixel electrode 1210 and the upper surface of the second organic insulating layer 180 on which the first sub-pixel electrode 1210 is not disposed. The insulating layer 190 can cover the side surface (i.e., edge) of the first sub-pixel electrode 1210. The insulating layer 190 can include an inorganic insulating material. In the case where the insulating layer 190 includes an inorganic insulating material, quality degradation of the light emitting diode due to gas emitted from the insulating layer 190 during a process of manufacturing the display device can be prevented or reduced, compared to the case where the insulating layer 190 includes an organic insulating material.

[0075] The insulating layer 190 can include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and include a single-layer structure or a multi-layer structure including the described inorganic insulating material. The insulating layer 190 can include an opening 190OP overlapping the first opening 300OP1 of the conductive bank barrier 300 and the first sub-pixel electrode 1210. A width W1 of the opening 190OP of the insulating layer 190 can be less than a width W2 of the first opening 300OP1.

[0076] The first intermediate layer 1220 can be in direct contact with the first sub-pixel electrode 1210 through the opening 190OP of the insulating layer 190. For example, the first intermediate layer 1220 overlaps the first sub-pixel electrode 1210 and contacts the first sub-pixel electrode 1210 through the first opening 300OP1 of the conductive bank barrier 300. The first intermediate layer 1220 can include a first portion 1220a at the center of the first intermediate layer 1220 and a second portion 1220b extending from the first portion 1220a at the periphery. For example, the second portion 1220b can extend in a direction (e.g., X direction, Y direction) away from the first portion 1220a and the center of the first intermediate layer 1220. The first portion 1220a can be a central portion of the first intermediate layer 1220, and the second portion 1220b can be a peripheral portion of the first intermediate layer 1220. In some aspects, the second portion 1220b can be referred to as an outer portion of the first intermediate layer 1220. The first portion 1220a of the first intermediate layer 1220 can overlap and contact the first sub-pixel electrode 1210, and the second portion 1220b can extend on and overlap and contact the insulating layer 190. At least a portion (e.g., the second portion 1220b) of the first intermediate layer 1220 can be disposed on the upper surface of the insulating layer 190.

[0077] The first intermediate layer 1220 disposed between the opposite electrode 1230 and the first sub-pixel electrode 1210 can be configured to emit light of a first color. The width W1 of the opening 190OP of the insulating layer 190 can correspond to the width of the emission area of the first light emitting diode LED1.

[0078] The first intermediate layer 1220 can include a first emission layer 1222 as FIG. 4 The first intermediate layer 1220 can include a common layer disposed between the first sub-pixel electrode 1210 and the first emission layer 1222 and / or between the first emission layer 1222 and the opposite electrode 1230. Hereinafter, the common layer between the first sub-pixel electrode 1210 and the first emission layer 1222 is referred to as a first common layer 1221, and the common layer between the first emission layer 1222 and the opposite electrode 1230 is referred to as a second common layer 1223.

[0079] The first emission layer 1222 can include a polymer organic material or a low molecular weight organic material configured to emit light having a preset color (e.g., red, green, or blue). In another embodiment, the first emission layer 1222 can include an inorganic material or a quantum dot.

[0080] The first common layer 1221 can include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second common layer 1223 can include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first common layer 1221 and the second common layer 1223 can each include an organic material.

[0081] Referring to FIG. 3 The upper surface 1220at of the first portion 1220a of the first intermediate layer 1220 can include a flat surface, and the upper surface 1220bt of the second portion 1220b can include an inclined surface inclined toward the upper surface 100t of the substrate 100 with respect to the extension direction of the second portion 1220b (e.g., the direction from the center of the first intermediate layer 1220 to the peripheral portion). For example, the distance between the inclined surface and the upper surface 100t of the substrate 100 can decrease in the extension direction of the second portion 1220b. In other words, the distance between the inclined surface and the upper surface 100t of the substrate 100 can decrease in the direction from the center of the first intermediate layer 1220 to the peripheral portion.

[0082] The flat surface of the first portion 1220a of the first intermediate layer 1220 can be inclined (e.g., declined) at an angle of about 0° to about 15° toward the upper surface 100t of the substrate 100. In other words, the flat surface of the first portion 1220a of the first intermediate layer 1220 can be inclined at an angle of about 0° to about 15° with respect to a virtual plane L1 parallel to the upper surface 100t of the substrate 100.

[0083] The inclined surface of the second portion 1220b of the first intermediate layer 1220 can be inclined (e.g., descending) toward the upper surface 100t of the substrate 100 at an angle θ of about 15° to about 45°. In other words, the inclined surface of the second portion 1220b of the first intermediate layer 1220 can be inclined (e.g., descending) at an angle θ of about 15° to about 45° with respect to a virtual plane L1 parallel to the upper surface 100t of the substrate 100. The inclined surface of the second portion 1220b of the first intermediate layer 1220 can have a gentle slope with respect to the upper surface 100t of the substrate 100.

[0084] In an embodiment, the upper surface 1220bt of the second portion 1220b of the first intermediate layer 1220 can include an inclined surface having a preset angle. However, the present disclosure is not limited thereto. In another embodiment, the upper surface 1220bt of the second portion 1220b can include inclined surfaces having different respective angles. As an example, the inclined angle of the inclined surface can decrease in a direction from the periphery to the center.

[0085] In an embodiment, a vertical distance from the upper surface 100t of the substrate 100 to the upper surface 1220at of the first portion 1220a of the first intermediate layer 1220 can be greater than a vertical distance from the upper surface 100t of the substrate 100 to the upper surface 1220bt of the second portion 1220b of the first intermediate layer 1220. In other words, a vertical distance h1 from a virtual plane L1 parallel to the upper surface 100t of the substrate 100 to the upper surface 1220at of the first portion 1220a of the first intermediate layer 1220 can be greater than a vertical distance h2 from the virtual plane L1 to the upper surface 1220bt of the second portion 1220b of the first intermediate layer 1220.

[0086] The inclined structure of the upper surface 1220bt of the second portion 1220b of the first intermediate layer 1220 can be formed by the tip structure of the preliminary conductive barrier layer 300’ described herein with reference to FIG. 8A and FIG. 8B In an embodiment, as illustrated in FIG. 21, the edge 1220e of the second portion 1220b of the first intermediate layer 1220 can be in contact with the side surface 300s of the conductive barrier layer 300. However, the present disclosure is not limited thereto. In another embodiment, as

[0087] illustrated in FIG. 22, the edge 1220e of the second portion 1220b of the first intermediate layer 1220 can be spaced apart from the side surface 300s of the conductive barrier layer 300. However, the present disclosure is not limited thereto. FIG. 3 FIG. 5As illustrated in FIG. 12B, the edge 1220e of the second portion 1220b of the first intermediate layer 1220 can be disposed such that the edge 1220e is adjacent to the side surface 300s of the conductive bank layer 300. In this case, for example, the edge 1220e of the second portion 1220b of the first intermediate layer 1220 can be in contact with the upper surface 190t of the insulating layer 190. As an example, in an embodiment, the conductive bank layer 300 and the first intermediate layer 1220 can be formed such that the shortest distance between the side surface 300s of the conductive bank layer 300 and the edge 1220e of the second portion 1220b of the first intermediate layer 1220 is 1 µm or less. The term "adjacent" used herein can refer to being close to another element, with or without being in contact with the other element. For example, in some cases, adjacent elements can be in contact with each other. In some other examples, adjacent elements can be in the vicinity of each other (e.g., spaced apart by a threshold distance or less).

[0088] The counter electrode 1230 can include a conductive material having a low work function. As an example, the counter electrode 1230 can include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), and iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In some aspects, the counter electrode 1230 can further include a layer on the (semi-)transparent layer, the layer including ITO, IZO, ZnO, or In2O3.

[0089] The counter electrode 1230 can be integrally formed in the display area DA of the substrate 100. The counter electrode 1230 can continuously extend such that the counter electrode 1230 covers the first intermediate layer 1220 and the conductive bank layer 300. The counter electrode 1230 can further extend beyond the edge 1220e of the second portion 1220b of the first intermediate layer 1220 and be in direct contact with the conductive bank layer 300. As an example, as illustrated in FIG. 12B, the counter electrode 1230 can be in direct contact with the upper surface of the first intermediate layer 1220, the upper surface of the conductive bank layer 300, and at least a portion of the side surface 300s of the conductive bank layer 300 (e.g., a portion of the side surface 300s of the conductive bank layer 300 on which the first intermediate layer 1220 is not disposed). FIG. 3 and FIG. 5 As illustrated in FIG. 12B, the edge 1220e of the second portion 1220b of the first intermediate layer 1220 can be disposed such that the edge 1220e is adjacent to the side surface 300s of the conductive bank layer 300. In this case, for example, the edge 1220e of the second portion 1220b of the first intermediate layer 1220 can be in contact with the upper surface 190t of the insulating layer 190. As an example, in an embodiment, the conductive bank layer 300 and the first intermediate layer 1220 can be formed such that the shortest distance between the side surface 300s of the conductive bank layer 300 and the edge 1220e of the second portion 1220b of the first intermediate layer 1220 is 1 µm or less. The term "adjacent" used herein can refer to being close to another element, with or without being in contact with the other element. For example, in some cases, adjacent elements can be in contact with each other. In some other examples, adjacent elements can be in the vicinity of each other (e.g., spaced apart by a threshold distance or less).

[0090] A capping layer (not illustrated) can be further disposed on the counter electrode 1230. The counter electrode 1230 can be protected by the capping layer disposed thereon. The capping layer can be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. In an embodiment, the capping layer can be omitted.

[0091] A first inorganic encapsulation layer 510 can be disposed on the opposite electrode 1230. The first inorganic encapsulation layer 510 can be entirely formed in the display area DA of the substrate 100 and can extend toward the non-display area NDA (see FIG. 1A and FIG. 1B ). The first inorganic encapsulation layer 510 can overlap the first light emitting diode LED1 and be configured to protect the first light emitting diode LED1. As an example, as exemplified in FIG. 3 and FIG. 5 , the first inorganic encapsulation layer 510 can continuously overlap the first light emitting diode LED1 and the conductive bank barrier 300.

[0092] The first inorganic encapsulation layer 510 can include at least one inorganic insulating material of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and can be deposited using a chemical vapor deposition method.

[0093] FIG. 6 is a plan view of a display apparatus according to an embodiment, and FIG. 7 is a cross-sectional view of the display apparatus taken along the line X-X’ of FIG. 6 .

[0094] Referring to FIG. 6 and FIG. 7 , as exemplified in FIG. 6 , the conductive bank barrier 300 can include openings, e.g., first to third openings 300OP1, 300OP2, and 300OP3, respectively, corresponding to the first to third sub-pixels. The first to third openings 300OP1, 300OP2, and 300OP3 can be arranged such that the first to third openings 300OP1, 300OP2, and 300OP3 are separated from each other, and the conductive bank barrier 300 can have a mesh structure in a plan view.

[0095] Referring to FIG. 6 , the first to third light emitting diodes LED1, LED2, and LED3 can be disposed in the first to third openings 300OP1, 300OP2, and 300OP3 of the conductive bank barrier 300, respectively.

[0096] Referring to FIG. 7 , the first to third light emitting diodes LED1, LED2, and LED3 over the substrate 100 can be electrically connected to the first to third sub-pixel circuits PC1, PC2, and PC3, respectively.

[0097] The first to third sub-pixel circuits PC1, PC2, and PC3 can have substantially the same structure. As an example, the structure of the second sub-pixel circuit PC2 and the third sub-pixel circuit PC3 can be the same as that of the first sub-pixel circuit PC1. In this regard, each of the second sub-pixel circuit PC2 and the third sub-pixel circuit PC3 is exemplified in FIG. 7 FIG. 2B.

[0098] The first to third light emitting diodes LED1, LED2, and LED3 can have substantially the same structure. As described herein with reference to FIG. 3 to FIG. 5 FIG. 2A, FIG. 7 The first light emitting diode LED1, as exemplified in

[0099] The second light emitting diode LED2 can include a stack structure of a second sub-pixel electrode 2210, a second intermediate layer 2220, and the counter electrode 1230 disposed in a second opening 300OP2 of the conductive bank barrier 300. The second intermediate layer 2220 overlaps the second sub-pixel electrode 2210 and contacts the second sub-pixel electrode 2210 through the second opening 300OP2 of the conductive bank barrier 300. The second intermediate layer 2220 can include a first portion 2220a arranged at a center of the second intermediate layer 2220, and the second intermediate layer 2220 can include a second portion 2220b extending from the first portion 2220a at a periphery. An upper surface of the second portion 2220b of the second intermediate layer 2220 can include a sloped surface that gently slopes (e.g., descends) toward an upper surface of the substrate 100 with respect to an extension direction of the second portion 2220b (e.g., a direction from the center of the second intermediate layer 2220 to the peripheral portion).

[0100] The third light emitting diode LED3 can include a stack structure of the third sub-pixel electrode 3210, the third intermediate layer 3220, and the counter electrode 1230 disposed in the third opening 300OP3 of the conductive bank barrier 300. The third intermediate layer 3220 can include a first portion 3220a arranged at a center of the third intermediate layer 3220 and a second portion 3220b extending from the first portion 3220a at a periphery. An upper surface of the second portion 3220b of the third intermediate layer 3220 can include an inclined surface that gently inclines (e.g., descends) toward the upper surface of the substrate 100 with respect to an extension direction of the second portion 3220b (e.g., a direction from the center of the third intermediate layer 3220 to the peripheral portion).

[0101] The second light emitting diode LED2 and the third light emitting diode LED3 can include substantially the same structure and materials, except that the emission layer of the second intermediate layer and the emission layer of the third intermediate layer are configured to emit light of a different color from the light emitted from the emission layer of the first intermediate layer, and the emission layer of the second intermediate layer and the emission layer of the third intermediate layer include a material configured to emit light of a different color from the color of light emitted from the material of the emission layer of the first intermediate layer. In other words, the structure of the cross-section corresponding to each of the second light emitting diode LED2 and the third light emitting diode LED3 is substantially the same or similar to the structure described herein with reference to FIG. 3 to FIG. 5

[0102] The counter electrode 1230 can continuously extend such that the counter electrode 1230 covers the first intermediate layer 1220 of the first light emitting diode LED1, the second intermediate layer 2220 of the second light emitting diode LED2, the third intermediate layer 3220 of the third light emitting diode LED3, and the conductive bank barrier 300. The counter electrode 1230 can extend to pass an edge of each of the first intermediate layer 1220, the second intermediate layer 2220, and the third intermediate layer 3220, and be in direct contact with the conductive bank barrier 300. As an example, as illustrated in FIG. 3, the counter electrode 1230 can be in direct contact with the upper surface of the first intermediate layer 1220, the upper surface of the second intermediate layer 2220, the upper surface of the third intermediate layer 3220, the upper surface of the conductive bank barrier 300, and at least a portion of the side surface 300s of the conductive bank barrier 300 (e.g., a portion of the side surface 300s of the conductive bank barrier 300 on which the first intermediate layer 1220, the second intermediate layer 2220, and the third intermediate layer 3220 are not disposed). FIG. 7 FIG. 2 ) and FIG. 4, the counter electrode 1230 can be in direct contact with the upper surface of the first intermediate layer 1220, the upper surface of the second intermediate layer 2220, the upper surface of the third intermediate layer 3220, the upper surface of the conductive bank barrier 300, and at least a portion of the side surface 300s of the conductive bank barrier 300 (e.g., a portion of the side surface 300s of the conductive bank barrier 300 on which the first intermediate layer 1220, the second intermediate layer 2220, and the third intermediate layer 3220 are not disposed).

[0103] ​​According to an embodiment, the contact area between the counter electrode 1230 and the conductive bank 300 is sufficiently secured, which can prevent deterioration of display quality caused by a voltage drop of the counter electrode 1230 of the large-sized display device 1. Accordingly, the display device 1 having high display quality can be provided.

[0104] The encapsulation layer 500 can include a first inorganic encapsulation layer 510, an organic encapsulation layer 520 on the first inorganic encapsulation layer 510, and a second inorganic encapsulation layer 530 on the organic encapsulation layer 520. The encapsulation layer 500 can overlap the first to third light emitting diodes LED1, LED2, and LED3, and protect the first to third light emitting diodes LED1, LED2, and LED3. The encapsulation layer 500 can continuously overlap the first to third light emitting diodes LED1, LED2, and LED3 and the conductive bank 300. As an example, the first inorganic encapsulation layer 510 can continuously overlap the first to third light emitting diodes LED1, LED2, and LED3 and the conductive bank 300.

[0105] The organic encapsulation layer 520 can include a polymer-based material. The polymer-based material can include an acrylic resin, an epoxy resin, a polyimide, and a polyethylene. In an embodiment, the organic encapsulation layer 520 can include an acrylate.

[0106] The second inorganic encapsulation layer 530 can include at least one inorganic insulating material of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0107] FIG. 8A to FIG. 8J is a schematic cross-sectional view corresponding to a process of manufacturing a display device according to an embodiment, and illustrates a process of manufacturing the display device FIG. 7 . Referring to FIG. 8A to FIG. 8J a method of manufacturing a display device according to an embodiment is described.

[0108] In the description of the methods and processes herein, the operations can be performed in a different order than shown and / or described, or the operations can be performed at different times, or with different sequences, or some operations can be omitted. Certain operations can also be added to the methods and processes. The descriptions of elements "may be provided", "may be formed", "may be etched", and "may be removed", etc. include methods, processes, and techniques for providing, forming, positioning, etching, and modifying elements, etc. according to the example aspects described herein.

[0109] Referring to FIG. 8AThe method can include forming the first, second, and third sub-pixel electrodes 1210, 2210, and 3210 on the second organic insulating layer 180, and the method can include forming the insulating layer 190 covering side surfaces (i.e., edges) of each of the first, second, and third sub-pixel electrodes 1210, 2210, and 3210. The insulating layer 190 can include openings overlapping the first, second, and third sub-pixel electrodes 1210, 2210, and 3210, respectively.

[0110] The method can include forming the preliminary conductive bank layer 300' on the insulating layer 190. The preliminary conductive bank layer 300' can include conductive layers having different etching selectivities. In an embodiment, the preliminary conductive bank layer 300' can include a first conductive layer 310 and a second conductive layer 320 on the first conductive layer 310. The first and second conductive layers 310 and 320 can include metals having different respective etching selectivities. For example, the etching selectivity of the metal included in the first conductive layer 310 can be different from the etching selectivity of the metal included in the second conductive layer 320. In an embodiment, the first conductive layer 310 can include a layer including aluminum (Al), and the second conductive layer 320 can include a layer including titanium (Ti).

[0111] Although the preliminary conductive bank layer 300' is exemplified as including two conductive layers in FIG. 8A , the present disclosure is not limited thereto. In another embodiment, the preliminary conductive bank layer 300' can include the first conductive layer 310, the second conductive layer 320 on the first conductive layer 310, and a third conductive layer under the first conductive layer 310.

[0112] The method can include forming the preliminary conductive bank layer 300' by etching a preliminary first conductive layer (not illustrated) and a preliminary second conductive layer (not illustrated) having different etching selectivities. The method can include forming the first and second conductive layers 310 and 320 by removing a portion of the preliminary first conductive layer and a portion of the preliminary second conductive layer. In this case, an opening can be formed in the first conductive layer 310, in which the opening overlaps the first, second, and third sub-pixel electrodes 1210, 2210, and 3210. An opening can be formed in the second conductive layer 320, and the openings can overlap the first, second, and third sub-pixel electrodes 1210, 2210, and 3210, respectively.

[0113] As an example, the method can include forming a first opening 310OP1 in the first conductive layer 310 that overlaps the first sub-pixel electrode 1210, and the method can include forming a first opening 320OP2 in the second conductive layer 320 that overlaps the first sub-pixel electrode 1210. The width of the opening of the second conductive layer 320 can be less than the width of the opening of the first conductive layer 310. As an example, the width of the first opening 320OP1 of the second conductive layer 320 can be less than the width of the first opening 310OP1 of the first conductive layer 310.

[0114] In an embodiment, the preliminary conductive dam layer 300’ can include an undercut structure in a cross-sectional view. As an example, the second conductive layer 320 can include a tip TP that extends (i.e., protrudes) in a direction (e.g., a lateral direction) from a point CP where a side surface 310s of the first conductive layer 310 intersects a bottom surface 320b of the second conductive layer 320.

[0115] Referring to FIG. 8B The method can include forming a first intermediate layer 1220 and a first sacrificial layer 410 each overlapping the first sub-pixel electrode 1210. In an embodiment, the method can include forming the first intermediate layer 1220 by a deposition method such as thermal deposition. The first sacrificial layer 410 can be configured to protect the first intermediate layer 1220. The first sacrificial layer 410 can include a metallic material. As an example, the first sacrificial layer 410 can include aluminum (Al).

[0116] The method can include depositing the first intermediate layer 1220 and the first sacrificial layer 410 without a separate mask. The deposited material used to form the first intermediate layer 1220 can form the preliminary conductive dam layer 300’, the second sub-pixel electrode 2210, or a first dummy intermediate layer 1220D that overlaps the third sub-pixel electrode 3210. In some aspects, the deposited material used to form the first sacrificial layer 410 can form the preliminary conductive dam layer 300’, the second sub-pixel electrode 2210, or a first dummy sacrificial layer 410D that overlaps the third sub-pixel electrode 3210. The first intermediate layer 1220 and the first dummy intermediate layer 1220D can be separated and spaced apart from each other. The first sacrificial layer 410 and the first dummy sacrificial layer 410D can be separated and spaced apart from each other. The first intermediate layer 1220 and the first dummy intermediate layer 1220D can include the same material and / or the same number of conductive layers (e.g., a first common layer, an emissive layer, and a second common layer). The first sacrificial layer 410 and the first dummy sacrificial layer 410D can include the same material.

[0117] An incident angle of the deposition material forming the first intermediate layer 1220 can be affected by (e.g., limited by) the undercut structure of the preliminary conductive barrier layer 300’. Specifically, for example, the first intermediate layer 1220 can be deposited inside the first opening 310OP of the first conductive layer 310 of the preliminary conductive barrier layer 300’, and can include a first portion 1220a and a second portion 1220b extending from the first portion 1220a in a periphery. In this case, due to the tip TP of the second conductive layer 320 of the preliminary conductive barrier layer 300’, an upper surface of the second portion 1220b of the first intermediate layer 1220 adjacent to the preliminary conductive barrier layer 300 can include a tilted surface tilted (e.g., descending) toward the upper surface of the substrate 100 with respect to an extension direction of the second portion 1220b. In an example, the extension direction of the second portion 1220b can be a direction from a center of the first intermediate layer 1220 toward a peripheral portion.

[0118] Referring to FIG. 8C , FIG. 8D and FIG. 8E , the method can include forming a first photoresist pattern PR1 covering the first intermediate layer 1220 and the first sacrificial layer 410. Next, the method can include etching the first dummy intermediate layer 1220D and the first dummy sacrificial layer 410D using the first photoresist pattern PR1 as a mask. In this case, the etching process can be performed as a dry etching and / or a wet etching. In an example, the etching process can include removing all of the first dummy intermediate layer 1220D and the first dummy sacrificial layer 410D not completely covered by the first photoresist pattern PR1.

[0119] Then, the method can include removing the first photoresist pattern PR1.

[0120] Referring to FIG. 8F , the second intermediate layer 2220 and the second sacrificial layer 420 can each overlap with the second sub-pixel electrode 2120, and the third intermediate layer 3220 and the third sacrificial layer 430 can each overlap with the third sub-pixel electrode 3120. The method can include sequentially removing the second intermediate layer 2220, the second sacrificial layer 420, the third intermediate layer 3220, and the third sacrificial layer 430. As an example, the method can include forming the second intermediate layer 2220 and the second sacrificial layer 420, and the method can include then forming the third intermediate layer 3220 and the third sacrificial layer 430. The formation of the second intermediate layer 2220 and the second sacrificial layer 420 and the formation of the third intermediate layer 3220 and the third sacrificial layer 430 can be performed by substantially the same processes as described with reference to FIG. 8B to FIG. 8E .

[0121] In an embodiment, the first, second, and third sacrificial layers 410, 420, and 430 can include the same material. As an example, the first, second, and third sacrificial layers 410, 420, and 430 can include aluminum (Al). The present disclosure is not limited thereto. In another embodiment, the first, second, and third sacrificial layers 410, 420, and 430 can include different metallic materials, respectively.

[0122] Referring to FIG. 8G The method can include forming the conductive barrier 300 by removing the second conductive layer 320 of the preliminary conductive barrier 300’. The method can include removing the second conductive layer 320 by etching, and the etching process can be performed by dry etching or can be performed by a combination of dry etching and wet etching. In this case, the first, second, and third intermediate layers 1220, 2220, and 3220 can be protected by the first, second, and third sacrificial layers 410, 420, and 430, respectively. The first conductive layer 310 from which the second conductive layer 320 is removed can correspond to the conductive barrier 300.

[0123] Referring to FIG. 8H The method can include removing the first, second, and third sacrificial layers 410, 420, and 430 by etching. In an embodiment, the method can include simultaneously performing a process of removing the first, second, and third sacrificial layers 410, 420, and 430. Alternatively, the method can include sequentially performing a process of removing the first, second, and third sacrificial layers 410, 420, and 430. In some cases, if the etching process is performed by dry etching, the first, second, and third intermediate layers 1220, 2220, and 3220 can be damaged by plasma. Accordingly, in order to prevent or reduce damage to the first, second, and third intermediate layers 1220, 2220, and 3220, the method can include performing the etching process by wet etching.

[0124] Then, the method can include drying the substrate 100 by heat-treating the substrate 100 at a temperature of 100°C (or about 100°C) or less.

[0125] Referring to FIG. 8IThe method can include forming the counter electrode 1230. In an embodiment, the method can include forming the counter electrode 1230 by a deposition method such as thermal deposition. The method can include forming the counter electrode 1230 continuously so that the counter electrode 1230 is continuous on the first intermediate layer 1220, the second intermediate layer 2220, the third intermediate layer 3220, and the conductive bank barrier layer 300. The stack structure of the first sub-pixel electrode 1210, the first intermediate layer 1220, and the counter electrode 1230 can correspond to the first light emitting diode LED1. The stack structure of the second sub-pixel electrode 2210, the second intermediate layer 2220, and the counter electrode 1230 can correspond to the second light emitting diode LED2. The stack structure of the third sub-pixel electrode 3210, the third intermediate layer 3220, and the counter electrode 1230 can correspond to the third light emitting diode LED3.

[0126] Reference FIG. 8J FIG. 8A to FIG. 8J The method can include forming the encapsulation layer 500 on the counter electrode 1230. The method can include forming the first inorganic encapsulation layer 510, the organic encapsulation layer 520, and the second inorganic encapsulation layer 530 in sequence.

[0127] According to embodiments, a display device having high quality and a method of manufacturing the same can be implemented. However, the scope of the present disclosure is not limited to this effect.

[0128] It should be understood that the embodiments described herein are to be considered illustrative, and not restrictive, in character. Descriptions of features or aspects within each embodiment should generally be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device, characterized by comprising: The display device includes: a substrate; a first sub-pixel electrode over the substrate; a conductive bank barrier disposed on the first sub-pixel electrode and including a first opening overlapping the first sub-pixel electrode; a first intermediate layer overlapping the first sub-pixel electrode and contacting the first sub-pixel electrode through the first opening of the conductive bank barrier; and an opposite electrode covering the first intermediate layer and the conductive bank barrier, wherein the first intermediate layer includes a first portion at a center of the first intermediate layer and a second portion extending from the first portion at a periphery, and an upper surface of the second portion includes an inclined surface inclined toward an upper surface of the substrate with respect to an extending direction of the second portion.

2. The display device according to claim 1, wherein The inclined surface of the second portion is inclined at an angle of about 15° to about 45° with respect to the upper surface of the substrate.

3. The display device according to claim 1, wherein A vertical distance from the upper surface of the substrate to an upper surface of the first portion of the first intermediate layer is greater than a vertical distance from the upper surface of the substrate to the upper surface of the second portion of the first intermediate layer.

4. The display device according to claim 1, wherein The display device further includes an insulating layer disposed between a peripheral portion of the first sub-pixel electrode and the conductive bank barrier and including an opening overlapping the first opening.

5. The display device according to claim 4, wherein At least a portion of the first intermediate layer is disposed on an upper surface of the insulating layer.

6. The display device according to claim 4, wherein A width of the first opening of the conductive bank barrier is greater than a width of the opening of the insulating layer.

7. The display device according to claim 1, wherein An edge of the second portion of the first intermediate layer is in contact with the conductive bank barrier.

8. The display device according to claim 1, wherein An edge of the second portion of the first intermediate layer is adjacent to the conductive bank barrier.

9. The display device according to claim 1, wherein The opposite electrode continuously covers an upper surface of the conductive bank barrier, at least a portion of a side surface of the conductive bank barrier, and an upper surface of the first intermediate layer.

10. The display device according to claim 1, wherein The display device further includes: a second sub-pixel electrode over the substrate; and a second intermediate layer overlapping the second sub-pixel electrode and contacting the second sub-pixel electrode through a second opening of the conductive bank barrier, wherein the opposite electrode continuously covers the first intermediate layer, the conductive bank barrier, and the second intermediate layer.

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