Detection circuit of DRED controller and optical storage inverter

Abstract

The utility model discloses a detection circuit of a DRED controller and an optical storage inverter, the detection circuit comprises six communication lines which are respectively connected with six input ports of the controller, the first to fourth communication lines are respectively connected with corresponding intermediate nodes of controlled switches, the fifth communication line is connected with a tenth controlled switch and a detection resistor, and the detection resistor is connected with the tenth controlled switch. The sixth communication line is connected with a ninth controlled switch; five pull-up resistors are respectively connected with a power supply and corresponding communication lines, wherein the first to fourth pull-up resistors are also connected with corresponding divider resistors. By adding a pull-up resistor and a divider resistor to the input pin of the controller, when the on-off state of the DRED controller is changed, the controller can judge the specific on-off state of the DRED controller by detecting the voltage signal of each pin, so that the inverter can respond in time and work in a corresponding mode.

Description

TECHNICAL FIELD

[0001] The utility model relates to inverter technical field, especially a kind of detection circuit of DRED controller and optical storage inverter. BACKGROUND

[0002] In 2016, Australian power grid company released the latest Australian and New Zealand photovoltaic grid-connected inverter and photovoltaic optical storage inverter safety standard "AS NZS 4777.2-2015", which requires that all photovoltaic inverters sold to Australia and New Zealand after July 2016 must comply with the latest safety standards. In the "AS NZS 4777.2-2015" safety standard, DRMs (Demand Response Modes, demand response mode) are added: using an external control box-DRED (Demand Response Enabling Device, demand response enabling device), active scheduling and reactive scheduling of power grid can be realized in real time and quickly, and photovoltaic inverter can also operate stably during scheduling.

[0003] In the DRMs of photovoltaic grid-connected inverter, there are 9 demands in total, among which DRM0: Operate the disconnection device is a mode that inverter must have, and inverter should detect and respond to supported DRMs within 2s, and inverter should maintain response when a certain mode is valid.

[0004] Therefore, a detection circuit that can accurately reflect the switch state of DRED controller S0-S9 in optical storage inverter is needed, and inverter responds to related working mode according to detection result. Utility model content

[0005] The utility model aims at providing a kind of detection circuit of DRED controller and optical storage inverter, and all switch action states of DRED controller are identified, so that inverter detects and responds corresponding working mode in time.

[0006] In order to solve the above-mentioned utility model purpose, the utility model provides a kind of detection circuit of DRED controller, comprising:

[0007] A first communication line has one end connected to a first input port of the controller and the other end connected to a middle node of the first controlled switch and the fifth controlled switch; a second communication line has one end connected to a second input port of the controller and the other end connected to a middle node of the second controlled switch and the sixth controlled switch; a third communication line has one end connected to a third input port of the controller and the other end connected to a middle node of the third controlled switch and the seventh controlled switch; a fourth communication line has one end connected to a fourth input port of the controller and the other end connected to a middle node of the fourth controlled switch and the eighth controlled switch; a fifth communication line has one end connected to a fifth input port of the controller and the other end connected to a tenth controlled switch and a detection resistor of the controller, and the other end of the tenth controlled switch is connected to the other end of the detection resistor; a sixth communication line has one end connected to a sixth input port of the controller and the other end connected to a ninth controlled switch, and the other end of the ninth controlled switch is connected to the tenth controlled switch and the detection resistor;

[0008] A first pull-up resistor has one end connected to a power supply and the other end connected to a first voltage dividing resistor and the first communication line; a second pull-up resistor has one end connected to the power supply and the other end connected to a second voltage dividing resistor and the second communication line; a third pull-up resistor has one end connected to the power supply and the other end connected to a third voltage dividing resistor and the third communication line; a fourth pull-up resistor has one end connected to the power supply and the other end connected to a fourth voltage dividing resistor and the fourth communication line; and a fifth pull-up resistor has one end connected to the power supply and the other end connected to the fifth communication line.

[0009] Optionally, a first current limiting resistor has one end connected to the first input port and the other end connected to a node of the first communication line and the first voltage dividing resistor; a second current limiting resistor has one end connected to the second input port and the other end connected to a node of the second communication line and the second voltage dividing resistor; a third current limiting resistor has one end connected to the third input port and the other end connected to a node of the third communication line and the third voltage dividing resistor; a fourth current limiting resistor has one end connected to the fourth input port and the other end connected to a node of the fourth communication line and the fourth voltage dividing resistor; a fifth current limiting resistor has one end connected to the fifth input port and the other end connected to the fifth pull-up resistor; and a sixth current limiting resistor has one end connected to the sixth input port and the other end connected to the sixth communication line.

[0010] Optionally, the controller comprises an MCU chip.

[0011] Optionally, the first input port, the second input port, the third input port, the fourth input port and the fifth input port are AD ports of the MCU chip.

[0012] Optionally, the sixth input port is an IO port of the MCU chip.

[0013] Optionally, the first pull-up resistor has a resistance range of 20-30kΩ, the second pull-up resistor has a resistance range of 20-30kΩ, the third pull-up resistor has a resistance range of 20-30kΩ, the fourth pull-up resistor has a resistance range of 20-30kΩ, and the fifth pull-up resistor has a resistance range of 20-30kΩ.

[0014] Optionally, the first voltage dividing resistor has a resistance range of 10-20kΩ, the second voltage dividing resistor has a resistance range of 10-20kΩ, the third voltage dividing resistor has a resistance range of 10-20kΩ, and the fourth voltage dividing resistor has a resistance range of 10-20kΩ.

[0015] Optionally, the power supply voltage has a range of 2-3V.

[0016] Optionally, the first current limiting resistor has a resistance range of 5-10kΩ, the second current limiting resistor has a resistance range of 5-10kΩ, the third current limiting resistor has a resistance range of 5-10kΩ, the fourth current limiting resistor has a resistance range of 5-10kΩ, the fifth current limiting resistor has a resistance range of 5-10kΩ, and the sixth current limiting resistor has a resistance range of 5-10kΩ.

[0017] The utility model also provides a kind of light storage inverter, including inverter circuit and controller, the light storage inverter also includes the detection circuit as described above, and the controller is used to control the input and output of the inverter circuit according to the detection result of the detection circuit.

[0018] Compared with prior art, the detection circuit of the DRED controller provided by the utility model adds pull-up resistor and voltage dividing resistor on each input pin of the controller, when the switch state of the DRED controller changes, the specific switch state of the DRED controller can be judged by detecting each pin voltage signal, and then the inverter can respond in time and work in corresponding mode;All switch action states of the DRED controller can be accurately identified by the detection circuit provided by the utility model, and operational amplifier does not need to be used, so that cost can be reduced and circuit can be simplified. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is the detection circuit schematic diagram of the DRED controller in the utility model embodiment.

[0020] In the drawing: 1, first communication line;2, second communication line;3, third communication line;4, fourth communication line;5, fifth communication line;6, sixth communication line;

[0021] S1, first controlled switch; S2, second controlled switch; S3, third controlled switch; S4, fourth controlled switch; S5, fifth controlled switch; S6, sixth controlled switch; S7, seventh controlled switch; S8, eighth controlled switch; S9, ninth controlled switch; S0, tenth controlled switch;

[0022] R1, first pull-up resistor; R2, second pull-up resistor; R3, third pull-up resistor; R4, fourth pull-up resistor; R0, fifth pull-up resistor;

[0023] R5, first voltage dividing resistor; R6, second voltage dividing resistor; R7, third voltage dividing resistor; R8, fourth voltage dividing resistor;

[0024] R11, first current limiting resistor; R12, second current limiting resistor; R13, third current limiting resistor; R14, fourth current limiting resistor; R10, fifth current limiting resistor; R15, sixth current limiting resistor;

[0025] R9, detection circuit. DETAILED DESCRIPTION

[0026] The utility model will be described below in conjunction with the schematic diagram, wherein the preferred embodiment of the utility model is indicated, it should be understood that the person skilled in the art can modify the utility model described herein, and still realize the advantageous effect of the utility model. Therefore, the following description should be understood as the extensive knowledge of the person skilled in the art, and not as the limitation of the utility model.

[0027] The serial number of the component in this paper, for example, "first", "second" and the like, is only used to distinguish the described object, and has no any order or technical meaning. And the "connection" and "coupling" of the present application include direct and indirect connection (coupling) if not specially stated. In the description of the utility model, it should be understood that the orientation or position relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the utility model.

[0028] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0029] The present application will be described in more detail in the following paragraphs with reference to the drawings. According to the following description, the advantages and features of the present application will be more apparent. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0030] The circuit structure of the DRED controller is shown in Figure 1 The DRED circuit of the DRED controller includes first to tenth controlled switches S0-S9, wherein the first controlled switch S1 and the fifth controlled switch S5 are connected in series to form a first branch, the second controlled switch S2 and the sixth controlled switch S6 are connected in series to form a second branch, the third controlled switch S3 and the seventh controlled switch S7 are connected in series to form a third branch, the fourth controlled switch S4 and the eighth controlled switch S8 are connected in series to form a fourth branch, and the detection resistor R9 forms a fifth branch. The five branches are connected in parallel with each other.

[0031] Specifically, one end of the first to fourth controlled switches S1, S2, S3 and S4 is connected in parallel, and one end of the fifth to eighth controlled switches S5, S6, S7 and S8 is connected in parallel. One end of the ninth controlled switch S9 is connected to the parallel end of S1, S2, S3 and S4, and the other end is grounded. One end of the tenth controlled switch S0 is connected to the fifth communication line 5, and the other end is connected to the intermediate node between the ninth controlled switch S9 and the parallel end of the first to fourth controlled switches S1, S2, S3 and S4.

[0032] The present application provides a detection circuit for the DRED controller, please continue to refer to Figure 1 The detection circuit comprises:

[0033] A first communication line 1 has one end connected to a first input port DRM1 / 5 of the controller and the other end connected to a middle node of a first controlled switch S1 and a fifth controlled switch S5; a second communication line 2 has one end connected to a second input port DRM2 / 6 of the controller and the other end connected to a middle node of a second controlled switch S2 and a sixth controlled switch S6; a third communication line 3 has one end connected to a third input port DRM3 / 7 of the controller and the other end connected to a middle node of a third controlled switch S3 and a seventh controlled switch S7; a fourth communication line 4 has one end connected to a fourth input port DRM4 / 8 of the controller and the other end connected to a middle node of a fourth controlled switch S4 and an eighth controlled switch S8; a fifth communication line 5 has one end connected to a fifth input port REF GEN / 0 of the controller and the other end connected to a tenth controlled switch S0 and a detection resistor of the controller, and the other end of the tenth controlled switch S0 is connected to the other end of the detection resistor; a sixth communication line 6 has one end connected to a sixth input port COM LOAD / 0 of the controller and the other end connected to a ninth controlled switch S9, and the other end of the ninth controlled switch S9 is connected to the tenth controlled switch S0 and the detection resistor.

[0034] A first pull-up resistor R1 has one end connected to a power supply and the other end connected to a first voltage dividing resistor R5 and the first communication line 1; a second pull-up resistor R2 has one end connected to the power supply and the other end connected to a second voltage dividing resistor R6 and the second communication line 2; a third pull-up resistor R3 has one end connected to the power supply and the other end connected to a third voltage dividing resistor R7 and the third communication line 3; a fourth pull-up resistor R4 has one end connected to the power supply and the other end connected to a fourth voltage dividing resistor R8 and the fourth communication line 4; a fifth pull-up resistor R0 has one end connected to the power supply and the other end connected to the fifth communication line 5.

[0035] In the embodiment, the detection circuit R9 can collect the voltages of the relevant nodes by using the first communication line 1 to the sixth communication line 6, analyze the input voltages of the first input port DRM1 / 5, the second input port DRM2 / 6, the third input port DRM3 / 7, the fourth input port DRM4 / 8, the fifth input port REF GEN / 0 and the sixth input port COM LOAD / 0 of the MCU chip, and then determine the on-off states of the switches of the DRED controller.

[0036] Further, please continue to refer to Figure 1 It also includes a current limiting resistor.

[0037] Specifically, the first current-limiting resistor R11 has one end connected to the first input port DRM1 / 5 and the other end connected to the node between the first communication line 1 and the first voltage-dividing resistor R5; the second current-limiting resistor R12 has one end connected to the second input port DRM2 / 6 and the other end connected to the node between the second communication line 2 and the second voltage-dividing resistor R6; the third current-limiting resistor R13 has one end connected to the third input port DRM3 / 7 and the other end connected to the node between the third communication line 3 and the third voltage-dividing resistor R7; the fourth current-limiting resistor R14 has one end connected to the fourth input port DRM4 / 8 and the other end connected to the node between the fourth communication line 4 and the fourth voltage-dividing resistor R8; the fifth current-limiting resistor R10 has one end connected to the fifth input port REF GEN / 0 and the other end connected to the fifth pull-up resistor R0; and the sixth current-limiting resistor R15 has one end connected to the sixth input port COM LOAD / 0 and the other end connected to the sixth communication line 6.

[0038] Further, the controller comprises an MCU chip.

[0039] Further, the first input port, the second input port, the third input port, the fourth input port and the fifth input port are AD ports of the MCU chip.

[0040] Further, the sixth input port is an IO port of the MCU chip.

[0041] Further, the first pull-up resistor R1 has a resistance value ranging from 20 to 30 kΩ, the second pull-up resistor R2 has a resistance value ranging from 20 to 30 kΩ, the third pull-up resistor R3 has a resistance value ranging from 20 to 30 kΩ, the fourth pull-up resistor R4 has a resistance value ranging from 20 to 30 kΩ, and the fifth pull-up resistor R0 has a resistance value ranging from 20 to 30 kΩ.

[0042] Further, the first voltage-dividing resistor R5 has a resistance value ranging from 10 to 20 kΩ, the second voltage-dividing resistor R6 has a resistance value ranging from 10 to 20 kΩ, the third voltage-dividing resistor R7 has a resistance value ranging from 10 to 20 kΩ, and the fourth voltage-dividing resistor R8 has a resistance value ranging from 10 to 20 kΩ.

[0043] Further, the power supply voltage ranges from 2 to 3 V.

[0044] Further, the first current-limiting resistor R11 has a resistance value ranging from 5 to 10 kΩ, the second current-limiting resistor R12 has a resistance value ranging from 5 to 10 kΩ, the third current-limiting resistor R13 has a resistance value ranging from 5 to 10 kΩ, the fourth current-limiting resistor R14 has a resistance value ranging from 5 to 10 kΩ, the fifth current-limiting resistor R10 has a resistance value ranging from 5 to 10 kΩ, and the sixth current-limiting resistor R15 has a resistance value ranging from 5 to 10 kΩ.

[0045] Further, the utility model still provides a kind of light storage inverter, including inverter circuit and controller, the light storage inverter also includes the detection circuit R9 as described above, the controller is used to control the input and output of the inverter circuit according to the detection result of the detection circuit R9.

[0046] Further, the detection circuit as described above is used, the voltage signal of the first input port DRM1 / 5, the second input port DRM2 / 6, the third input port DRM3 / 7, the fourth input port DRM4 / 8, the fifth input port REF GEN / 0, the sixth input port COM LOAD / 0 of MCU chip is analyzed, and the switch state of each controlled switch S0 to S9 of DRED controller is judged.

[0047] Specifically:

[0048] First, the state of each controlled switch in DRED controller is S0-S8 open, and the ninth controlled switch S9 is closed under normal circumstances. At this time, the port voltage of the first communication line 1 to the fifth communication line 5 connected to the MCU chip can be detected as +VA·R5 / (R1+R5), +VA·R6 / (R2+R6), +VA·R7 / (R3+R7), +VA·R8 / (R4+R8) and +VA·R9 / (R0+R9), which can be used to determine the switch state as controlled switch S0-S8 open and the ninth controlled switch S9 closed, so that the inverter works normally.

[0049] When the port voltage of the fifth communication line 5 connected to the MCU is detected as +VA, it indicates that the controlled switches S0-S9 are open, and it is determined that the external control box is disconnected from the detection circuit, so that the light storage inverter stops. Or when the port voltage of the fifth communication line 5 connected to the MCU is detected as 0V, it indicates that the controlled switches S1-S8 are open, the tenth controlled switch S0 and the ninth controlled switch S9 are closed, which also makes the light storage inverter stop.

[0050] On the premise of excluding the tenth controlled switch S0 closed or the ninth controlled switch S9 open, the following detection is carried out:

[0051] When the port voltage of the first communication line 1 connected to the MCU is detected as 0V, it indicates that the tenth controlled switch S0 is open, the controlled switches S2-S8 are open, the first controlled switch S1 and the ninth controlled switch S9 are closed, so that the light storage inverter stops receiving grid power.

[0052] When the port voltage of the second communication line 2 connected to the MCU is detected as 0V, it indicates that the tenth controlled switch S0 is open, the first controlled switch S1 is open, the controlled switches S3-S8 are open, the second controlled switch S2 and the ninth controlled switch S9 are closed, so that the light storage inverter receives no more than 50% of the rated power of the grid power and emits as much reactive power as possible.

[0053] When the port voltage of the third communication line 3 connected to the MCU is detected as 0V, it indicates that the tenth controlled switch S0 is open, the first controlled switch S1 is open, the second controlled switch S2 is open, the controlled switches S4-S8 are open, the third controlled switch S3 and the ninth controlled switch S9 are closed, so that the light storage inverter receives no more than 75% of the rated power of the grid power and emits as much reactive power as possible.

[0054] When the port voltage of the fourth communication line 4 connected to the MCU is detected as 0V, it indicates that the controlled switches S0-S3 are open, the controlled switches S5-S8 are open, the fourth controlled switch S4 and the ninth controlled switch S9 are closed, so that the light storage inverter increases the received grid power.

[0055] When the port voltage of the first communication line 1 connected to the MCU is detected as +VA·(R5 / / R9) / (R5 / / R9+R0 / / R1), it indicates that the controlled switches S0-S4, the controlled switches S6-S8 are open, the fifth controlled switch S5 and the ninth controlled switch S9 are closed, so that the light storage inverter stops emitting power to the grid.

[0056] When the port voltage of the second communication line 2 connected to the MCU is detected as +VA·(R6 / / R9) / (R6 / / R9+R0 / / R2), it indicates that the controlled switches S0-S5, the seventh controlled switch S7 are open, the eighth controlled switch S8 is open, the sixth controlled switch S6 and the ninth controlled switch S9 are closed, so that the light storage inverter emits no more than 50% of the rated power to the grid.

[0057] When the port voltage of the third communication line 3 connected to the MCU is detected as +VA·(R7 / / R9) / (R7 / / R9+R0 / / R3), it indicates that the controlled switches S0-S6, the eighth controlled switch S8 are open, the seventh controlled switch S7 and the ninth controlled switch S9 are closed, so that the light storage inverter emits no more than 75% of the rated power to the grid and absorbs as much reactive power as possible.

[0058] When the port voltage of the fourth communication line 4 connected to the MCU is detected as +VA·(R8 / / R9) / (R8 / / R9+R0 / / R4), it indicates that the controlled switches S0-S7 are open, the eighth controlled switch S8 and the ninth controlled switch S9 are closed, so that the light storage inverter increases the active power emitted to the grid.

[0059] In summary, the utility model provides a kind of detection circuit and light storage inverter of DRED controller, and pull-up resistance and voltage dividing resistance are added to each input pin of MCU chip, when the switch state of DRED controller changes, MCU chip can detect each pin voltage signal to judge the specific switch state of DRED controller, so that inverter can respond in time and work in corresponding mode;Current-limiting resistance is additionally added in detection circuit, current-limiting protection resistance, which can avoid damage caused by large current on MCU chip;The detection circuit provided by the utility model can accurately identify all switch action states of DRED switch box, has wide applicability, simple structure and low cost;Without using operational amplifier, cost can be reduced and circuit can be simplified.

[0060] Obviously, those skilled in the art can make various modifications and variations to the utility model without departing from the spirit and scope of the utility model. Thus, if these modifications and variations of the utility model fall within the scope of the utility model claims and their equivalents, the utility model also intends to include these modifications and variations.

Claims

1. A detection circuit of a DRED controller, characterized by, The application relates to a controller for controlling a plurality of switches, comprising: a first communication line, one end of which is connected to a first input port of a controller, and the other end of which is connected to an intermediate node of a first controlled switch and a fifth controlled switch; a second communication line, one end of which is connected to a second input port of the controller, and the other end of which is connected to an intermediate node of a second controlled switch and a sixth controlled switch; a third communication line, one end of which is connected to a third input port of the controller, and the other end of which is connected to an intermediate node of a third controlled switch and a seventh controlled switch; a fourth communication line, one end of which is connected to a fourth input port of the controller, and the other end of which is connected to an intermediate node of a fourth controlled switch and an eighth controlled switch; a fifth communication line, one end of which is connected to a fifth input port of the controller, and the other end of which is connected to a tenth controlled switch and a detection resistor of the controller, and the other end of the tenth controlled switch is connected to the other end of the detection resistor; and a sixth communication line, one end of which is connected to a sixth input port of the controller, and the other end of which is connected to a ninth controlled switch, and the other end of the ninth controlled switch is connected to the tenth controlled switch and the detection resistor; a first pull-up resistor, one end of which is connected to a power supply, and the other end of which is connected to a first voltage dividing resistor and the first communication line; a second pull-up resistor, one end of which is connected to the power supply, and the other end of which is connected to a second voltage dividing resistor and the second communication line; a third pull-up resistor, one end of which is connected to the power supply, and the other end of which is connected to a third voltage dividing resistor and the third communication line; and a fourth pull-up resistor, one end of which is connected to the power supply, and the other end of which is connected to a fourth voltage dividing resistor and the fourth communication line; a fifth pull-up resistor, one end of which is connected to the power supply, and the other end of which is connected to the fifth communication line.

2. The detection circuit of a DRED controller of claim 1, wherein, The application further comprises current limiting resistors; a first current limiting resistor, one end of which is connected to the first input port, and the other end of which is connected to a node of the first communication line and the first voltage dividing resistor; a second current limiting resistor, one end of which is connected to the second input port, and the other end of which is connected to a node of the second communication line and the second voltage dividing resistor; a third current limiting resistor, one end of which is connected to the third input port, and the other end of which is connected to a node of the third communication line and the third voltage dividing resistor; a fourth current limiting resistor, one end of which is connected to the fourth input port, and the other end of which is connected to a node of the fourth communication line and the fourth voltage dividing resistor; a fifth current limiting resistor, one end of which is connected to the fifth input port, and the other end of which is connected to the fifth pull-up resistor; and a sixth current limiting resistor, one end of which is connected to the sixth input port, and the other end of which is connected to the sixth communication line.

3. The detection circuit of a DRED controller of claim 1, wherein, The controller comprises an MCU chip.

4. The detection circuit of a DRED controller of claim 3, wherein, The first input port, the second input port, the third input port, the fourth input port and the fifth input port are AD ports of the MCU chip.

5. The detection circuit of a DRED controller of claim 3, wherein, The sixth input port is an IO port of the MCU chip.

6. The detection circuit of a DRED controller of claim 1, wherein, The first pull-up resistor has a resistance value in the range of 20-30kΩ, the second pull-up resistor has a resistance value in the range of 20-30kΩ, the third pull-up resistor has a resistance value in the range of 20-30kΩ, the fourth pull-up resistor has a resistance value in the range of 20-30kΩ, and the fifth pull-up resistor has a resistance value in the range of 20-30kΩ.

7. The detection circuit of a DRED controller of claim 1, wherein, The resistance value of the first voltage dividing resistor ranges from 10 to 20 kΩ, the resistance value of the second voltage dividing resistor ranges from 10 to 20 kΩ, the resistance value of the third voltage dividing resistor ranges from 10 to 20 kΩ, and the resistance value of the fourth voltage dividing resistor ranges from 10 to 20 kΩ.

8. The detection circuit of a DRED controller of claim 1, wherein, The power supply voltage ranges from 2 to 3 V.

9. The detection circuit of a DRED controller of claim 2, wherein, The resistance value of the first current limiting resistor ranges from 5 to 10 kΩ, the resistance value of the second current limiting resistor ranges from 5 to 10 kΩ, the resistance value of the third current limiting resistor ranges from 5 to 10 kΩ, the resistance value of the fourth current limiting resistor ranges from 5 to 10 kΩ, the resistance value of the fifth current limiting resistor ranges from 5 to 10 kΩ, and the resistance value of the sixth current limiting resistor ranges from 5 to 10 kΩ.

10. A light storage inverter comprising an inverter circuit and a controller, characterized in that, The optical storage inverter further comprises the detection circuit according to any one of claims 1 to 9, and the controller is configured to control the input and output of the inverter circuit according to the detection result of the detection circuit.

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