Single-chip EtherCAT slave station core board
By integrating the AsiaInfo AX58200 chip into a single-chip EtherCAT slave core board, the problems of low localization rate of core boards, hardware complexity, and high cost have been solved, achieving modular design and cost reduction.
Patent Information
- Application Number
- CN202520173638.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-26
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2035-01-26
AI Technical Summary
The processors and peripheral chips of existing core boards mainly rely on foreign components, resulting in a low localization rate, and the EtherCAT slave hardware is complex and costly.
Using the AsiaInfo AX58200 chip, the MCU and EtherCAT protocol chip are integrated into one chip to design a single-chip EtherCAT slave core board, which includes a core control chip, a power management module and an RJ45 interface, thus achieving module standardization.
The core board was localized, simplifying the hardware structure, reducing costs, and improving the system's flexibility and scalability through modular design.
Smart Images
Figure CN223712164U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of EtherCAT slave station core board, especially relates to a single-chip EtherCAT slave station core board. BACKGROUND
[0002] At present, the processor and peripheral chip of most core boards are composed of foreign components, which leads to low localization rate of the core board and cannot realize independent controllability.
[0003] EtherCAT protocol is a standard industrial control protocol, has the advantages of stable and reliable, transmission speed is fast, usually EtherCAT slave station is with MCU + special protocol chip to realize, hardware is complex, cost is high. CONTENT OF UTILITY MODEL
[0004] The utility model solves the technical problem in the prior art to provide a single-chip EtherCAT slave station core board, which integrates MCU and EtherCAT protocol chip into a chip by adopting Axin AX58200 chip, does not need external expansion function chip, realizes single-chip solution, designs and develops core control board, and is matched with different function boards through the core control board to form different function modules, which is helpful to realize the standardization of modules.
[0005] The utility model adopts the following technical scheme to solve the above technical problem:
[0006] A single-chip EtherCAT slave station core board, comprising a core control chip, a power management module, an expansion socket and an RJ45 interface, wherein the power management module, the expansion socket and the RJ45 interface are connected to the core control chip.
[0007] The power management module comprises a chip U11, a 5V voltage terminal, a resistor R69, a capacitor C63, a capacitor C58, an inductor L9, a resistor R65, a capacitor C27, a resistor R57, a resistor R65, a resistor R49, a capacitor C25, a capacitor C32, and a 1.2V voltage terminal; one end of the resistor R69, one end of the capacitor C63, one end of the capacitor C58, and a pin 4 of the chip U11 are connected to the 5V voltage terminal respectively, the other end of the resistor R69 is connected to a pin 1 of the chip U11, a pin 2 of the chip U11 is connected to the other end of the capacitor C58 and the other end of the capacitor C63 and grounded respectively, a pin 3 of the chip U11 is connected to one end of the inductor L9, the other end of the inductor L9 is connected to one end of the capacitor C27, one end of the resistor R57, one end of the capacitor C32, one end of the capacitor C25, and the 1.2V voltage terminal respectively, the other end of the capacitor C27 is grounded, a pin 6 of the chip U11 is connected to the other end of the resistor R57 and one end of the resistor R49 respectively, the other end of the resistor R49 is grounded, a pin 5 of the chip U11 is connected to one end of the resistor R65, the other end of the resistor R65 is connected to the 1.2V voltage terminal, and the other end of the capacitor C25 and the other end of the capacitor C32 are grounded respectively.
[0008] The chip U12, a resistor R108, a capacitor C83, a capacitor C80, an inductor L15, a capacitor C73, a resistor R91, a capacitor C75, a capacitor C70, a resistor R100, and a resistor R93 are connected to a 3.3V voltage terminal; one end of the resistor R108, one end of the capacitor C83, one end of the capacitor C80, and a pin 1 of the chip U12 are connected to a 5V voltage terminal respectively; a pin 2 of the chip U12 is connected to the other end of the capacitor C80 and the other end of the capacitor C83 and grounded respectively, a pin 3 of the chip U12 is connected to one end of the inductor L15, the other end of the inductor L15 is connected to one end of the capacitor C73, one end of the resistor R91, one end of the capacitor C75, one end of the capacitor C70, and the 3.3V voltage terminal respectively; the other end of the capacitor C75 and the other end of the capacitor C70 are grounded, the other end of the capacitor C73 is grounded, and the other end of the resistor R91 is connected to one end of the resistor R100 and a pin 6 of the chip U12 respectively; a pin 5 of the chip U12 is connected to one end of the resistor R65, the other end of the resistor R65 is connected to the 3.3V voltage terminal, and the other end of the resistor R100 is grounded.
[0009] As a further preferred scheme of the single-chip EtherCAT slave station core board, the core control chip adopts AX58200.
[0010] As a further preferred scheme of the single-chip EtherCAT slave station core board, the RJ45 interface comprises a U5D chip, and the U5D chip is an AX58200 related network interface pin.
[0011] As a further preferred scheme of the single-chip EtherCAT slave station core board, the expansion socket comprises an I2C bus, a 232 bus and an IO signal line; the I2C bus, the 232 bus and the IO signal line available for the AX58200 are led to a 100-pin pin, and different functional pins are selected and used when the core board is connected with different functional modules.
[0012] Compared with the prior art, the above technical scheme has the following technical effects:
[0013] The utility model discloses a core control chip, power management module, expansion socket, RJ45 interface, power management module, expansion socket, RJ45 interface are connected with core control chip respectively, adopt sub - signal AX58200 chip, and the MCU and EtherCAT protocol chip are integrated to a chip, need not external expansion function chip, realize single -chip solution, and the core control board is developed to the design, is matched through the core control board and different function board, forms different functional module, is helpful to realize the standardization of module, and the following picture is the function block diagram of core board, and the control information is transmitted to core board control chip AX58200 through RJ45 input net mouth, and AX58200 receives information, and the information that this module needs to handle is sent to external equipment through expansion interface, and the state signal of external equipment is gathered, is added to the information flow, is transmitted to the next module through RJ45 output net mouth, and finally the state information of all modules is sent back to the upper controller. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 It is the principle diagram of the single-chip EtherCAT slave station core board of the utility model,
[0015] Figure 2 It is the circuit diagram of power management module of the utility model,
[0016] Figure 3 It is the circuit diagram of expansion socket of the utility model,
[0017] Figure 4 It is the circuit diagram of RJ45 interface of the utility model. DETAILED DESCRIPTION
[0018] The technical scheme of the utility model will be explained further in detail as follows in combination with the drawings:
[0019] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.
[0020] A single-chip EtherCAT slave station core board, EtherCAT protocol is a standard industrial control protocol, has the advantages of stable and reliable, fast transmission speed, usually the EtherCAT slave station is MCU + dedicated protocol chip to realize, hardware is complex, high cost.
[0021] The single-chip EtherCAT slave station core board provided by the application comprises a core control chip, a power management module, an expansion socket and an RJ45 interface. Figure 1 The power management module, the expansion socket and the RJ45 interface are connected with the core control chip.
[0022] The application provides an integrated solution, adopts the AX58200 chip of Yaxin, integrates the MCU and the EtherCAT protocol chip into a chip, does not need external expansion function chip, realizes the single-chip solution, designs and develops the core control board, is matched with different function boards through the core control board, forms different function modules, is helpful to realize the standardization of the module, and the following figure is the function block diagram of the core board.
[0023] Function description:
[0024] The power management realizes the conversion of input 5V power into 3.3V and 1.2V required on the board, and supplies each chip. Figure 2 As shown in the principle diagram, U5A is the core control chip related power supply pin.
[0025] Core control chip: the core control chip adopts AX58200, integrates MCU, EtherCAT PHY.
[0026] The principle diagram of the RJ45 interface is as shown in Figure 3 U5D is the AX58200 related network interface pin.
[0027] Expansion socket: the expansion socket leads the I2C bus, 232 bus and IO signal line available for AX58200 to a 100-pin pin, and selects to use different function pins when the core board is connected with different function modules. Figure 4 As shown in the related principle diagram:
[0028] Working principle:
[0029] The upper control system transmits control information to the core board control chip AX58200 through the RJ45 input network port, the AX58200 receives the information, transmits the information needed to be processed by the module to the external device through the expansion interface, collects the state signal of the external device, adds the state signal to the information flow, transmits the information flow to the next module through the RJ45 output network port, and finally sends the state information of all the modules back to the upper controller.
[0030] The above only describes some exemplary embodiments of the present application by way of illustration, without doubt, for those skilled in the art, without departing from the spirit and scope of the present application, the described embodiments can be modified in various ways. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the present application.
Claims
1. A single-chip EtherCAT slave core board, characterized in that: It includes a core control chip, a power management module, an expansion socket, and an RJ45 interface; the power management module, expansion socket, and RJ45 interface are respectively connected to the core control chip; The power management module includes a chip U11, a 5V voltage terminal, a resistor R69, a capacitor C63, a capacitor C58, an inductor L9, a resistor R65, a capacitor C27, a resistor R57, a resistor R65, a resistor R49, a capacitor C25, a capacitor C32, and a 1.2V voltage terminal. The 5V voltage terminal is connected to one end of resistor R69, one end of capacitor C63, one end of capacitor C58, and pin 4 of chip U11. The other end of resistor R69 is connected to pin 1 of chip U11. Pin 2 of chip U11 is connected to the other ends of capacitor C58 and capacitor C63 respectively. Pin 3 of chip U11 is connected to one end of inductor L9. The other end of inductor L9 is connected to one end of capacitor C27, one end of resistor R57, one end of capacitor C32, one end of capacitor C25, and the 1.2V voltage terminal. The other end of capacitor C27 is grounded. Pin 6 of chip U11 is connected to the other end of resistor R57 and one end of resistor R49. The other end of resistor R49 is grounded. Pin 5 of chip U11 is connected to one end of resistor R65. The other end of resistor R65 is connected to the 1.2V voltage terminal. The other ends of capacitor C25 and capacitor C32 are grounded. The circuit consists of chip U12, resistor R108, capacitors C83 and C80, inductor L15, capacitor C73, resistor R91, capacitor C75, capacitor C70, resistor R100, resistor R93, and a 3.3V voltage terminal. A 5V voltage terminal is connected to one end of resistor R108, one end of capacitor C83, one end of capacitor C80, and pin 1 of chip U12. Pin 2 of chip U12 is connected to the other ends of capacitors C80 and C83 and grounded. Pin 3 of chip U12 is connected to one end of inductor L15. One end of inductor L15 is connected to one end of capacitor C73, one end of resistor R91, one end of capacitor C75, one end of capacitor C70, and the 3.3V voltage terminal. The other ends of capacitors C75 and C70 are grounded, and the other end of capacitor C73 is grounded. The other end of resistor R91 is connected to one end of resistor R100 and pin 6 of chip U12. Pin 5 of chip U12 is connected to one end of resistor R65. The other end of resistor R65 is connected to the 3.3V voltage terminal, and the other end of resistor R100 is grounded.
2. The single-chip EtherCAT slave core board according to claim 1, characterized in that: The core control chip used is AX58200.
3. The single-chip EtherCAT slave core board according to claim 1, characterized in that: The RJ45 interface includes a U5D chip, which is a network interface pin of the AX58200.
4. The single-chip EtherCAT slave core board according to claim 1, characterized in that: The expansion socket includes an I2C bus, a 232 bus, and IO signal lines; it is used to bring the I2C bus, 232 bus, and IO signal lines available to the AX58200 to a 100-pin connector, allowing different function pins to be selected when the core board is connected to different functional modules.