EMMC chip testing device and chip sorting system

Abstract

The utility model provides an eMMC chip testing device and a sorting system. The eMMC chip testing device is used for a chip sorting system and comprises a first circuit board and a second circuit board, the first circuit board is provided with an SOC processor, a TF card electrically connected with the SOC processor and a first connector arranged at the edge of the circuit board, the TF card is used for storing system mirror image files, the SOC processor supports an HS400 mode, and the highest frequency is not lower than 200 MHz; an eMMC test seat is arranged on one plane of the second circuit board, and the eMMC test seat is used for accommodating an eMMC chip to be tested; a second connector is arranged on the edge of the plane, opposite to the eMMC test seat, of the second circuit board, the first end of the second connector is used for being connected with the first connector, and the second end of the second connector is used for penetrating through the second circuit board and being electrically connected with the eMMC chip to be tested placed in the containing space. According to the invention, the to-be-tested chip can be rapidly replaced for continuous testing, the testing efficiency is improved, and resource waste is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory testing, and particularly relates to an eMMC chip testing device and a chip sorting system. BACKGROUND

[0002] An eMMC chip (Embedded Multi Media Card) is widely used in various mobile electronic devices, and is often tested for performance by using an Androbench (a benchmark test application). When the eMMC chip is used as a single storage device, if a traditional single steady-state performance testing device is used, the bandwidth, latency and IOPS (Input / Output Operations Per Second) in a certain time period (usually set to 6 hours) are tested after the to-be-tested eMMC chip reaches a steady state.

[0003] In the related art, the eMMC chip is a device that is not easy to remove, and the existing testing device is not convenient for replacement testing of multiple to-be-tested eMMC chips, that is, the to-be-tested chip cannot be quickly replaced for continuous testing, resulting in low testing efficiency and resource waste.

[0004] Based on this, the present application provides an eMMC chip testing device and a chip sorting system. SUMMARY

[0005] In view of the problem in the related art that the eMMC chip is a device that is not easy to remove, the to-be-tested chip cannot be quickly replaced for continuous testing, resulting in low testing efficiency and resource waste, the present application provides an eMMC chip testing device and a chip sorting system.

[0006] The purpose of the present application is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present application provides an eMMC chip testing device, which is used in a chip sorting system and includes a first circuit board and a second circuit board. A SOC processor, a TF card electrically connected to the SOC processor and a first connector arranged at the edge of the circuit board are arranged on the first circuit board. The TF card is used to store a system image file, and the SOC processor supports an HS400 mode and has a highest frequency of not less than 200 MHz.

[0008] A plane of the second circuit board is provided with an eMMC test seat, the eMMC test seat is used for accommodating an eMMC chip to be tested; a second connector is provided on an edge of a plane of the second circuit board opposite to the eMMC test seat, a first end of the second connector is used for connecting the first connector, and a second end of the second connector is used for penetrating through the second circuit board and electrically connecting with the eMMC chip to be tested placed in the accommodation space.

[0009] In some possible implementation manners, the eMMC test seat comprises a test seat body and a test seat gland, the test seat body comprises an accommodation space used for placing the eMMC chip to be tested; and the second end of the second connector is arranged in the accommodation space, and the test seat gland is used for applying a force to the eMMC chip to be tested towards the second end of the second connector when the eMMC chip to be tested is placed in the accommodation space.

[0010] In some possible implementation manners, the clock signal end, the data strobe signal end, the command signal end and the data signal end of the SOC processor are electrically connected with the first connector and the second connector respectively.

[0011] In some possible implementation manners, the data signal end comprises a first signal end to an eighth signal end, and is used for realizing eight-bit data transmission between the SOC processor and the eMMC chip to be tested.

[0012] In some possible implementation manners, a power supply monitoring circuit of the SOC processor is electrically connected with the first connector and the second connector.

[0013] In some possible implementation manners, four corners of the first circuit board are respectively provided with through holes used for positioning and fixing.

[0014] In some possible implementation manners, the SOC processor is RK3588.

[0015] In a second aspect, the present application provides a chip sorting system, comprising the eMMC chip testing device of any one of the first aspect.

[0016] In some possible implementation manners, the chip sorting system further comprises a shifting device arranged beside the eMMC chip testing device, the shifting device is used for placing an eMMC chip to be tested in the eMMC chip testing device for testing, and removing the eMMC chip to be tested after testing.

[0017] In some possible implementation manners, the shifting device is a suction cup shifting device, which comprises a mechanical arm, a suction cup arranged at one end of the mechanical arm, and a negative pressure providing device connected with the suction cup; the negative pressure providing device is configured to provide suction force for the suction cup to suck the eMMC chip to be tested; and the mechanical arm is configured to drive the suction cup to realize grabbing, carrying and placing of the eMMC chip to be tested.

[0018] In combination with the technical solutions and the solved technical problems described above, the technical solutions to be protected by the present application have the following advantages and positive effects:

[0019] The SOC processor supporting the HS400 mode and having a highest frequency not lower than 200MHz can meet the performance requirement of the eMMC chip in the high-speed test mode, can quickly process test data, accurately send and receive test instructions, and ensure the stability of the test process and the accuracy of the test result. The system image file is stored in the TF card, so that the eMMC chip to be tested is only used for testing, and when the test program or the system function needs to be improved subsequently, the system image file in the TF card only needs to be updated, without the need to replace the hardware device. The test device can be started from the TF card, instead of relying on the system or application data stored in the eMMC chip to be tested, the eMMC chip to be tested only serves as a device to be tested in the test process, without participating in system starting or running, and the hot plug function can be realized. The design of the eMMC test seat makes the eMMC chip to be tested convenient to put in and take out, compared with the traditional embedded eMMC chip test mode, the device only needs to simply take out and put in the chip from the test seat, a large amount of time and labor cost is saved, resource waste is avoided, and the continuity and efficiency of the test are improved. BRIEF DESCRIPTION OF DRAWINGS

[0020] The present application will be further described below in combination with the drawings and embodiments.

[0021] Figure 1 is a structural block diagram of an eMMC chip test device provided by an embodiment of the present application.

[0022] Figure 2 is a structural schematic diagram of an eMMC chip test device provided by an embodiment of the present application.

[0023] Figure 3 is a structural schematic diagram of an eMMC chip test device provided by an embodiment of the present application.

[0024] FIG. 1 is a structural schematic diagram of an eMMC chip test device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0025] The application will be further described below in conjunction with the drawings and specific embodiments. It should be noted that the following described embodiments or technical features can be combined with each other to form new embodiments without conflict. The implementation procedures of the application will be described below with reference to the drawings and preferred embodiments, and those skilled in the art can easily understand other advantages and effects of the application from the disclosure. The application can also be implemented or applied by different specific implementation procedures, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the application. It should be understood that the preferred embodiments are only for illustrating the application, and are not intended to limit the protection scope of the application.

[0026] eMMC is the abbreviation of embedded MultiMediaCard. MultiMediaCard, MMC, is a Flash Memory Card standard, which defines the architecture of MMC and the interface and protocol for accessing Flash Memory. And eMMC is an extension of MMC to meet the needs of higher standards of performance, cost, size, stability, ease of use, etc.

[0027] Since the eMMC chip is a non-removable device, to achieve efficient performance testing of any eMMC chip using the same development board, higher requirements are put forward for the support mode and performance of the SOC processor. At the same time, the eMMC chip needs to be designed as a removable device, so that the eMMC chip on the board can be replaced with a different chip under test. In this case, the eMMC chip in the related art stores system or application data, and cannot realize eMMC hot plug, which further reduces the test efficiency of the eMMC chip.

[0028] To realize quick replacement of the chip under test for continuous testing, improve test efficiency and avoid resource waste, the application provides an eMMC chip testing device and chip sorting system that can support eMMC hot plug.

[0029] Embodiment 1

[0030] Reference is made to Figure 1 , Figure 2 and Figure 3The embodiment provides an eMMC chip testing device. The eMMC chip testing device is used in a chip sorting system and comprises a first circuit board 100 and a second circuit board 200. The first circuit board 100 is provided with a SOC processor 110, a TF card 120 electrically connected to the SOC processor 110 and a first connector 130 arranged at the edge of the circuit board. The TF card 120 is used for storing a system image file. The SOC processor 110 supports an HS400 mode and has a highest frequency not lower than 200MHz.

[0031] The second circuit board 200 is provided with an eMMC testing seat 210 on one plane. The eMMC testing seat 210 is used for accommodating a to-be-tested eMMC chip. The second circuit board 200 is provided with a second connector 220 on the edge of the plane opposite to the eMMC testing seat 210. A first end of the second connector 220 is used for connecting the first connector 130. A second end of the second connector 220 is used for penetrating through the second circuit board 200 and electrically connecting the to-be-tested eMMC chip placed in the accommodation space.

[0032] It can be considered that the second circuit board 200 comprises two opposite planes. The eMMC testing seat 210 is arranged on one plane, and the second connector 220 is arranged on the other plane and penetrates through the second circuit board 200 and the eMMC testing seat 210, so that the second end of the second connector 220 is electrically connected to the to-be-tested eMMC chip in the accommodation space. The first end and the second end of the second connector 220 are opposite ends. It can also be considered that the SOC processor 110 on the first circuit board 100 is connected to the first end of the second connector 220 through the first connector 130. In this case, the second end of the second connector 220 penetrates through the second circuit board 200 and is electrically connected to the to-be-tested eMMC chip placed in the accommodation space of the eMMC testing seat 210. This design realizes the electrical connection between the SOC processor 110 and the to-be-tested eMMC chip and provides a channel for signal transmission. Meanwhile, the SOC processor 110 supports the HS400 mode and has a highest frequency not lower than 200MHz. Specifically, in the testing process, the SOC processor 110 sends various control signals (such as CLK clock signals and command signals) and data signals (DAT0-DAT7 signals) to the to-be-tested eMMC chip through the first connector 130 and the second connector 220 and receives response signals from the to-be-tested eMMC chip.

[0033] Meanwhile, the TF card 120 stores a system image file to enable the test system (corresponding to the system image file) to start. During the starting process, the SOC processor 110 loads the system image file from the TF card 120 to complete the initialization and loading of the system. Then, the SOC processor 110 starts the running of the test program to perform the test of the eMMC chip to be tested.

[0034] In this way, the SOC processor 110 supporting the HS400 mode and having a highest frequency not lower than 200 MHz can meet the performance requirements of the eMMC chip in the high-speed test mode, can quickly process test data, accurately send and receive test instructions, and ensure the stability of the test process and the accuracy of the test results. The system image file is stored in the TF card 120, so that the eMMC chip to be tested is only used for testing, and when the test program or system function needs to be improved subsequently, the system image file in the TF card 120 only needs to be updated, without the need to replace the hardware device. The test device can start from the TF card 120 instead of relying on the system or application data stored in the eMMC chip to be tested, and the eMMC chip to be tested only serves as a device to be tested in the test process and does not participate in the system starting or running, so that the hot plug function can be realized. The design of the eMMC test seat 210 enables the eMMC chip to be tested to be conveniently placed in and taken out, and compared with the traditional embedded eMMC chip test mode, the device only needs to simply take out and place the chip from the test seat, thereby saving a large amount of time and labor cost, avoiding resource waste, and improving the continuity and efficiency of the test.

[0035] In a specific application, a memory 150 is further arranged on the first circuit board 100 and connected with the SOC processor 110 to serve as a system running memory 150.

[0036] In some embodiments, the eMMC test seat 210 includes a test seat body and a test seat gland (not shown in the figure), the test seat body includes a containing space for placing the eMMC chip to be tested, and the second end of the second connector 220 is arranged in the containing space, and the test seat gland is used to apply a force to the eMMC chip to be tested towards the second end of the second connector 220 when the eMMC chip to be tested is placed in the containing space.

[0037] It can be understood that the test seat body is internally provided with a containing space for placing the eMMC chip to be tested. The size and shape of the containing space can be matched with the eMMC chip to ensure that the chip can be accurately and stably placed therein. The second end of the second connector 220 is arranged in the containing space to enable the pins thereof to accurately correspond to the interface of the eMMC chip to be tested. When the eMMC chip to be tested is placed in the containing space, the interface of the chip is electrically connected with the pins of the second connector 220, thereby providing a channel for signal transmission and power supply.

[0038] The test seat cover is an auxiliary component of the test seat. After the eMMC chip to be tested is placed in the accommodation space, the test seat cover exerts a force on the chip towards the second connector 220. Specifically, the test seat cover can be connected to the test seat body through a rotating shaft. The cover can rotate within a certain angle range around the rotating shaft, thereby realizing the fixation or release of the chip. When the cover is rotated to a position covering the accommodation space, the cover exerts pressure on the chip; when the cover is rotated (in a direction away from the chip), the chip can be freely placed or taken out. This design can reduce the overall volume of the test seat, making it more compact, and facilitating the opening and closing of the test seat cover and the taking and placing of the eMMC chip to be tested using a displacement device such as a suction cup.

[0039] In specific applications, before the test starts, the displacement device places the eMMC chip to be tested in the accommodation space of the test seat body. At this time, the interface of the eMMC chip to be tested is in preliminary contact with the pins of the second connector 220. Then, the test seat cover is installed in place, and the cover exerts a downward force on the chip, making the eMMC chip to be tested tightly fit with the pins of the second connector 220, ensuring the stability of the electrical connection. After the eMMC chip to be tested is tightly connected with the connector, the SOC processor 110 on the first circuit board 100 establishes communication with the eMMC chip to be tested through the first connector 130 and the second connector 220. The SOC processor 110 sends control signals and data signals, and the eMMC chip to be tested performs corresponding operations according to the signals and feeds back the test results to the SOC processor 110.

[0040] During the entire test process, the test seat cover continuously exerts a stable force on the chip, ensuring that the connection state of the chip and the connector is not disturbed by external factors.

[0041] After the test is completed, the displacement device (opens the test seat cover) takes out the tested eMMC chip and places a new eMMC chip to be tested in the accommodation space. Repeating the above process can realize the continuous testing of multiple eMMC chips.

[0042] Therefore, the force exerted by the test seat cover can effectively eliminate the signal transmission problems caused by poor contact between the chip and the connector. In high-speed signal transmission (such as HS400 mode), tight electrical connection can significantly reduce signal interference and transmission errors, thereby improving the accuracy and reliability of the test results. During the test, especially in the case of mechanical vibration or improper operation, the chip may become loose, causing the test to be interrupted or failed. The test seat cover fixes the position of the chip, avoiding such loosening phenomenon, and ensuring the stability of the test process.

[0043] In some embodiments, referring to Figure 1The clock signal end CLK, the data strobe signal end Data Strobe, the command signal end CMD and the data signal end (DAT0 to DAT7) of the SOC processor 110 are respectively electrically connected with the second connector 220 through the first connector 130.

[0044] The clock signal is the basis of eMMC communication, which is used to synchronize the data transmission between the SOC processor 110 and the eMMC chip under test. The SOC processor 110 generates a clock pulse through the clock signal end SLK and transmits the clock signal to the eMMC chip under test through the first connector 130 and the second connector 220. The data strobe signal Data Strobe is used to assist data transmission, helping the receiving end to more accurately sample the data signal in the high-speed transmission mode (HS400 mode). The command signal end CMD is used for the SOC processor 110 to send various instructions such as read-write commands, initialization commands, state query commands, etc. to the eMMC chip under test. The data signal end is used to transmit the actual data content (data signal) between the SOC processor 110 and the eMMC chip under test.

[0045] The eMMC chip under test determines the timing according to the received CLK signal, assists data sampling according to the Data Strobe signal, performs corresponding operations according to the command signal, and exchanges data with the SOC processor 110 through the data signal.

[0046] In some embodiments, the data signal end includes a first signal end to an eighth signal end, which is used to realize eight-bit data transmission between the SOC processor 110 and the eMMC chip under test.

[0047] The data signal end is composed of eight independent signal ends, which are marked as a first signal end to an eighth signal end (DAT0 to DAT7), and each signal end is responsible for transmitting one bit of data, which can significantly improve the data transmission efficiency. It can be considered that, in the data transmission process, the SOC processor 110 decomposes the data to be transmitted into eight-bit binary data, and each bit of data is sent to the second connector 220 through the corresponding signal end (DAT0 to DAT7). The second connector 220 transmits eight-bit data to the data interface of the eMMC chip under test. Using eight-bit data signal end for parallel transmission can complete the exchange of eight-bit data in a single clock cycle, compared with single-line data transmission (1-bit mode), the data transmission rate is improved, so as to fully utilize the high-speed characteristics supported by the protocol in the HS400 mode of eMMC, and significantly improve the test efficiency.

[0048] In some embodiments, the power monitoring circuit 160 (PMSC) of the SOC processor 110 is electrically connected with the second connector 220 through the first connector 130.

[0049] In the test device, the power management and supply controller (PMSC) of the SOC processor 110 is electrically connected to the VCC end and the VCCQ end of the second connector 220 through the first connector 130. Inside the eMMC chip to be tested, the VCC end is used for the Flash memory, and the VCCQ end is used for the controller and the MMC interface.

[0050] The power management and supply controller 160 controls and manages the power supply of the eMMC chip to be tested. By controlling the level state of the VCC (Flash memory power supply) and VCCQ (controller and MMC interface power supply) pins, the power-on and power-off operations of the eMMC chip are realized.

[0051] At the beginning of the test, the PMSC sets the VCC and VCCQ pins to high level through the first connector 130 and the second connector 220, providing stable power supply for the eMMC chip; after the test is completed, the PMSC sets these pins to low level, cutting off the power supply, in order to save power consumption and protect the chip.

[0052] At the same time, the PMSC can also monitor the state of the power supply in real time, detect whether the power voltage is within the normal range, and trigger a protection mechanism when an abnormality is detected (such as excessively low or high voltage), for example, automatically cutting off the power supply or sending an alarm signal.

[0053] In some embodiments, the four corners of the first circuit board 100 are respectively provided with through holes 140 for positioning and fixing.

[0054] The four through holes 140 on the first circuit board 100 are used for precise alignment with other components (such as a support frame or other circuit boards) during assembly. During installation, the through holes 140 are aligned with corresponding positioning pins or screw holes, ensuring the accurate position of the first circuit board 100 in space.

[0055] In some embodiments, the SOC processor 110 is RK3588. The eMMC interface of RK3588 supports high-speed mode (such as HS400), with a maximum frequency not lower than 200MHz, and has powerful processing capability and rich interface functions, which can meet the high-performance requirements of eMMC chip testing.

[0056] As an example, referring to Figure 1 the structural block diagram of an eMMC chip test device is shown, a test flow of a test device is provided.

[0057] After the system is started from the TF card 120, the SOC processor 110 controls the VCC and VCCQ pins to output a high level, and the system recognizes and mounts the eMMC chip device. The test program starts running, and the SOC processor 110 performs performance testing on the eMMC chip according to a preset test scheme through signal connection with the eMMC chip to be tested, such as read-write speed testing, time delay testing, and the like.

[0058] After the test program ends, the SOC processor 110 controls to unmount the eMMC device, and then controls the VCC and VCCQ pins to output a low level to turn off the power supply of the eMMC chip. The chip in the eMMC test seat 210 is taken out, and other chips to be tested are replaced, and the above test process is repeated to realize continuous testing of hot plug and unplug of multiple eMMC chips.

[0059] Embodiment 2

[0060] The embodiment provides a chip sorting system including the eMMC chip testing device of any one of the embodiments 1. It can obtain the same technical effects as the eMMC chip testing device of the embodiment 1, which will not be repeated here.

[0061] In some embodiments, the chip sorting system further includes a shifting device arranged beside the eMMC chip testing device, and the shifting device is used to place the eMMC chip to be tested in the eMMC chip testing device for testing, and remove the eMMC chip to be tested after testing.

[0062] The shifting device has a multi-degree-of-freedom movement capability and can move flexibly in a three-dimensional space. For example, it is equipped with a grabbing tool (such as a suction cup, a clamping jaw, etc.) for grabbing and releasing the eMMC chip to be tested. In the embodiment, the grabbing tool can be a suction cup (which generates suction force through negative pressure) or a clamping jaw (which clamps the chip through a mechanical structure). The suction cup generates suction force through a negative pressure providing device to firmly adsorb the chip to be tested; the clamping jaw clamps the chip through a mechanical structure to ensure the stability of the chip during the carrying process. The movement of the shifting device is controlled by a central control system (such as a PLC, an industrial computer, etc.), the position information of the chip is obtained through a sensor (such as a photoelectric sensor, a vision system, a position sensor, etc.), and the action of the mechanical arm is realized according to the preset program instructions, so as to realize automatic carrying of the chip. The specific implementation of the present application is not limited.

[0063] In a specific application, the eMMC chips to be tested are placed on a tray or a conveyor belt. The shifting device picks up the chips from the tray and transports them above the test seats of the eMMC chip testing device. The positioning device (such as a vision system or a mechanical positioning pin) of the chip sorting system ensures the precise alignment of the chips with the test seats. The shifting device places the eMMC chips to be tested into the test seats and releases the gripping tool. At this time, the power monitoring circuit (PMSC) of the testing device powers on the eMMC chips to be tested, and the test program starts running.

[0064] After the test is completed, the PMSC cuts off the power, and the shifting device picks up the eMMC chips to be tested again, removes them from the test seats, and places them in a designated area (such as a tray of qualified products or a tray of unqualified products). The shifting device repeats the above process to realize the continuous testing of multiple chips.

[0065] In some embodiments, the shifting device is a suction cup shifting device, which includes a mechanical arm, a suction cup arranged at one end of the mechanical arm, and a negative pressure providing device connected to the suction cup. The negative pressure providing device is used to provide suction force to the suction cup for adsorbing the eMMC chips to be tested. The mechanical arm is used to drive the suction cup to realize the picking up, carrying, and placing of the eMMC chips to be tested.

[0066] The mechanical arm can be composed of multiple telescopic or rotatable arm segments, which can realize multi-degree-of-freedom motion. The motion of the mechanical arm is driven by a motor, and the end of the mechanical arm is installed with a suction cup for picking up and placing the chips to be tested. The suction cup is installed at one end of the mechanical arm and directly contacts the eMMC chips to be tested. The suction cup is made of flexible material, for example, which can adapt to the surface shape of the chips to ensure the stability and reliability of adsorption. The negative pressure providing device (such as a vacuum pump or a negative pressure generator) is connected to the suction cup through an air pipe to generate and maintain negative pressure. When the negative pressure providing device is started, negative pressure is formed inside the suction cup, thereby generating adsorption force for firmly adsorbing the eMMC chips to be tested.

[0067] The suction cup shifting device realizes the automated process of chip testing, reducing the time and errors of manual operation. For example, in a large-scale chip sorting scenario, automated picking up, carrying, and placing operations can significantly improve the testing efficiency.

[0068] It should be noted that in the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b and c can be single or multiple. It should be noted that "at least one" can also be interpreted as "one or more".

[0069] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are configured to distinguish similar objects, and are not necessarily configured to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0070] The present application is described from the point of view of use, efficiency, progress and novelty, which meets the functional improvement and use requirements emphasized by the Patent Law. The above description and drawings of the specification are only preferred embodiments of the present application, and are not limited to the present application. Therefore, all similar, similar, equivalent, and similar structures, devices, features, etc. made according to the scope of the patent application of the present application shall be within the scope of the patent application of the present application.

Claims

1. An eMMC chip testing apparatus, characterized by, The eMMC chip testing device is used in a chip sorting system, including a first circuit board and a second circuit board. The first circuit board is provided with a SOC processor, a TF card electrically connected to the SOC processor, and a first connector located on the edge of the circuit board. The TF card is used to store system image files. The SOC processor supports HS400 mode and has a maximum frequency of not less than 200MHz. An eMMC test socket is provided on one plane of the second circuit board, which is used to accommodate the eMMC chip under test; a second connector is provided on the edge of the plane opposite to the eMMC test socket of the second circuit board, the first end of the second connector is used to connect to the first connector, and the second end of the second connector is used to pass through the second circuit board and be electrically connected to the eMMC chip under test placed in the accommodating space.

2. The eMMC chip testing apparatus of claim 1, wherein, The eMMC test socket includes a test socket body and a test socket cover. The test socket body includes a receiving space for placing the eMMC chip under test. The second end of the second connector is disposed in the receiving space. The test socket cover is used to apply a force toward the second end of the second connector to the eMMC chip under test when the eMMC chip under test is placed in the receiving space.

3. The eMMC chip testing apparatus of claim 2, wherein, The clock signal terminal, data strobe signal terminal, command signal terminal, and data signal terminal of the SOC processor are electrically connected to the second connector via the first connector.

4. The eMMC chip testing device according to claim 3, characterized in that, The data signal terminal includes a first signal terminal to an eighth signal terminal, used to realize eight-bit data transmission between the SOC processor and the eMMC chip under test.

5. The eMMC chip testing device according to claim 2, characterized in that, The power monitoring circuit of the SOC processor is electrically connected to the second connector via the first connector.

6. The eMMC chip testing apparatus according to claim 1, characterized in that, The first circuit board has through holes at its four corners for positioning and fixing.

7. The eMMC chip testing apparatus according to claim 1, characterized in that, The SOC processor is RK3588.

8. A chip sorting system, characterized in that, Includes the eMMC chip testing apparatus according to any one of claims 1-7.

9. The chip sorting system according to claim 8, characterized in that, The chip sorting system also includes a shifting device disposed next to the eMMC chip testing device. The shifting device is used to place the eMMC chip to be tested in the eMMC chip testing device for testing, and to remove the eMMC chip to be tested after testing.

10. The chip sorting system according to claim 9, characterized in that, The displacement device is a suction cup displacement device, which includes a robotic arm and a suction cup disposed at one end of the robotic arm, as well as a negative pressure supply device connected to the suction cup; the negative pressure supply device is used to provide suction force to the suction cup to adsorb the eMMC chip under test, and the robotic arm is used to drive the suction cup to realize the gripping, transporting and placement of the eMMC chip under test.

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