Filter circuit chip, packaging structure of microphone assembly and microphone

Abstract

The utility model provides a filter circuit chip, a packaging structure of a microphone assembly and a microphone. The filter circuit chip comprises a first conductive layer, M dielectric layers, M second conductive layers, M conductive traces, a grounding end and a plurality of bonding pads, the first conductive layer is provided with a first surface and a second surface which are opposite; the M dielectric layers are arranged between the first conductive layer and the second conductive layer and are arranged at intervals in the direction parallel to the second surface; the M second conductive layers and the M dielectric layers are correspondingly arranged; the second conductive layer, the conductive trace and the grounding end are connected with the bonding pad; the grounding end is connected with the first conductive layer; the M second conductive layers are connected with the M conductive traces in a one-to-one correspondence manner; at least a portion of the first conductive layer, the dielectric layer, and the second conductive layer form a capacitor structure in a direction perpendicular to the second surface, and the M conductive traces form a resistive structure. Based on the above structure, the size of the filter circuit can be reduced, thereby improving the pickup effect of the microphone.

Description

Technical Field

[0001] This application relates to the field of microelectromechanical systems (MEMS) technology, and in particular to a filter circuit chip, a microphone assembly packaging structure, and a microphone. Background Technology

[0002] In existing technologies, microphone assembly packaging typically includes an ASIC chip, a microphone chip, a filter circuit, a housing, and a circuit board. The housing and circuit board together form a cavity, and the ASIC chip, microphone chip, and filter circuit are all housed within this cavity and mounted on the circuit board. The cavity plays a role in adjusting the sound pickup effect; the smaller the cavity, the worse the sound pickup. However, the filter circuit can excessively occupy space within the cavity, further reducing the microphone assembly's sound pickup performance and impacting the user experience. Utility Model Content

[0003] This application provides a filter circuit chip, a packaging structure for a microphone assembly, and a microphone to solve the technical problem that filter circuits occupy too much cavity space when laid out separately in the prior art.

[0004] In a first aspect, this application proposes a filter circuit chip, the chip comprising a first conductive layer, M dielectric layers, M second conductive layers, M conductive traces, a ground terminal, and multiple pads; M is a positive integer;

[0005] The first conductive layer has opposing first and second surfaces;

[0006] The M dielectric layers are disposed between the first conductive layer and the second conductive layer, and are spaced apart in a direction parallel to the second surface;

[0007] The M second conductive layers are disposed corresponding to the M dielectric layers and are arranged on the surfaces of the M dielectric layers away from the first conductive layer;

[0008] The second conductive layer, the conductive trace, and the ground terminal are all connected to the pad;

[0009] The grounding terminal is also connected to the first conductive layer;

[0010] The M second conductive layers are connected one-to-one with the M conductive traces;

[0011] At least a portion of the first conductive layer, the dielectric layer, and the second conductive layer form a capacitor structure in a direction perpendicular to the second surface, and the M conductive traces form a resistive structure.

[0012] In addition to one or more of the features disclosed above, or as an alternative, the conductive trace includes a plurality of elongated metal pieces and a plurality of bends; the plurality of elongated metal pieces are connected in sequence through the bends; the conductive trace is connected to the second conductive layer through the bends.

[0013] In addition to one or more of the features disclosed above, or alternatively, the material of the first conductive layer includes low-resistivity silicon.

[0014] In addition to one or more of the features disclosed above, or as an alternative, the plurality of pads includes 2×M+1 pads; the 2×M+1 pads include: M first pads, M second pads, and one third pad; the M first pads are respectively connected to the M second conductive layers; the M second pads are respectively connected to the M conductive traces; and the third pad is connected to the ground terminal.

[0015] In addition to one or more of the features disclosed above, or as an alternative, the chip further includes a passivation layer disposed on a second surface of the first conductive layer, the passivation layer enclosing the M dielectric layers, the M second conductive layers, the M conductive traces, and the ground terminal.

[0016] In addition to one or more of the features disclosed above, or as an alternative, the passivation layer has a plurality of vias on the side away from the second surface; the pads pass through the vias and are connected to the M second conductive layers, the M conductive traces, and the ground terminal.

[0017] In addition to one or more of the features disclosed above, or as an alternative, the M conductive traces are disposed in the same layer as the M second conductive layers.

[0018] In addition to one or more of the features disclosed above, or as an alternative, the M conductive traces are disposed on the M second conductive layers; the second conductive layers and the conductive traces are spaced apart in a direction perpendicular to the second surface.

[0019] In addition to one or more of the features disclosed above, the chip also includes a passivation layer, and at least a portion of the passivation layer is filled within the interval.

[0020] Secondly, this application proposes a packaging structure for a microphone assembly, characterized in that the packaging structure for the microphone assembly includes a filter circuit chip, an ASIC chip, a microphone chip, a housing, a circuit board, a first wire, and a second wire as described in any embodiment.

[0021] The housing is disposed on one side of the circuit carrier board, and the housing and the circuit carrier board form a cavity.

[0022] The filter circuit chip and the ASIC chip are stacked in the cavity along the thickness direction of the microphone assembly's packaging structure;

[0023] The pads in the filter circuit chip are connected to the circuit board, and the first surface in the filter circuit chip is connected to the ASIC chip.

[0024] The microphone chip is disposed on the circuit board and housed within the cavity;

[0025] The ASIC chip is electrically connected to the circuit board via the first wire and to the microphone chip via the second wire;

[0026] The circuit board is provided with a sound inlet hole that extends through the thickness direction of the microphone assembly's packaging structure, or the housing is provided with a sound inlet hole that extends through the thickness direction of the microphone assembly's packaging structure.

[0027] In addition to one or more of the features disclosed above, or as an alternative, if the circuit board has a sound inlet hole that extends through the thickness direction of the microphone assembly's packaging structure, the microphone chip covers the sound inlet hole.

[0028] Thirdly, this application proposes a microphone, the microphone including a packaging structure for a microphone assembly as described in any embodiment.

[0029] This application can achieve the following beneficial effects: By integrating the filter circuit on the IPD chip, the size of the filter circuit can be reduced, the space occupied by the filter circuit in the cavity can be reduced, thereby improving the microphone's sound pickup effect. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the packaging structure of a microphone assembly in the prior art;

[0032] Figure 2 This is a schematic diagram of the packaging structure of a microphone assembly in the prior art;

[0033] Figure 3 A schematic diagram of the structure of a filter circuit chip provided for an embodiment of this application;

[0034] Figure 4 A cross-sectional view of a filter circuit chip provided for an embodiment of this application;

[0035] Figure 5 A top view of a filter circuit chip provided for an embodiment of this application;

[0036] Figure 6 A schematic diagram of the structure of a filter circuit chip provided for an embodiment of this application;

[0037] Figure 7 A schematic diagram of the structure of a filter circuit chip provided for an embodiment of this application;

[0038] Figure 8 A cross-sectional view of a filter circuit chip provided for an embodiment of this application;

[0039] Figure 9 An equivalent circuit diagram of a filter circuit chip provided for an embodiment of this application;

[0040] Figure 10 This is a schematic diagram of the packaging structure of a microphone assembly provided for an embodiment of this application.

[0041] Figure label:

[0042] 1-Filter circuit chip, 11-First conductive layer, 111-First surface, 112-Second surface, 12-Dielectric layer, 13-Second conductive layer, 14-Conductive trace, 141-Long strip metal part, 142-Bent portion, 15-Ground terminal, 16-Pad, 161-First pad, 162-Second pad, 163-Third pad, 17-Passivation layer;

[0043] 2-ASIC chip, 3-microphone chip, 4-housing, 5-circuit board, 6-first wire, 7-second wire, 8-cavity, 9-sound inlet hole, 10-glue;

[0044] 21-Filter circuit, 211-External resistor, 212-External capacitor. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0046] In the description of this application, it should be noted that the terms "vertical direction," "up," "down," "horizontal," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0047] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or a connection through an intermediate medium; they can refer to the internal communication of two components or a coupling. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0048] In the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0049] In the prior art, see [reference] Figure 1 As shown, the packaging structure of a microphone assembly typically includes an ASIC chip 2, a microphone chip 3, a filter circuit 21, a housing 4, and a circuit board 5. The housing 4 and the circuit board 5 enclose a cavity 8. The filter circuit 21 includes an external resistor 211 and an external capacitor 212. A sound inlet 9 is provided on the circuit board 5. The ASIC chip 2, microphone chip 3, and filter circuit 21 are all mounted on the circuit board 5 and housed within the cavity 8. The cavity 8 plays a role in adjusting the sound pickup effect; the smaller the space in the cavity 8, the worse the sound pickup effect. The filter circuit 21, however, occupies too much space in the cavity 8, thus reducing the sound pickup effect of the microphone assembly and affecting the user experience.

[0050] In the prior art, see [reference] Figure 2As shown, the filter circuit 21 can also be embedded inside the circuit board 5. Although this method can avoid the filter circuit 21 occupying the space of the cavity 8, the cost is higher, and the embedded external capacitor 212 with a large capacitance value is very easy to cause short circuit failure, affecting the product yield of the microphone assembly.

[0051] In view of the technical problems of existing technologies where filter circuits occupy a lot of cavity space when laid out separately and the cost of pre-embedded filter circuits is high, this application proposes a packaging structure for a filter circuit chip, a microphone assembly, and a microphone to overcome the above problems.

[0052] The following description, in conjunction with the accompanying drawings, introduces a filter circuit chip, a microphone assembly packaging structure, and a microphone provided in this application.

[0053] Please see Figure 3 , Figure 4 , Figure 5 This application proposes a filter circuit chip 1, which includes a first conductive layer 11, M dielectric layers 12, M second conductive layers 13, M conductive traces 14, a ground terminal 15, and multiple pads 16; M is a positive integer; wherein, the first conductive layer 11 has a first surface 111 and a second surface 112 opposite to each other; the M dielectric layers 12 are disposed on the first conductive layer 11 and are spaced apart in a direction parallel to the second surface 112; the M second conductive layers 13 are correspondingly disposed on the surfaces of the M dielectric layers 12 away from the first conductive layer 11. Above; the dielectric layer 12 is disposed between the first conductive layer 11 and the second conductive layer 13; the second conductive layer 13, the conductive traces 14, and the ground terminal 15 are all connected to the pad 16; the ground terminal 15 is also connected to the first conductive layer 11; the M second conductive layers 13 are connected one-to-one with the M conductive traces 14; at least a portion of the first conductive layer 11, the dielectric layer 12, and the second conductive layer 13 form a capacitor structure in a direction perpendicular to the second surface 112, and the M conductive traces 14 form a resistor structure.

[0054] It should be noted that the embodiments of this application are illustrated using M=2 as an example. This application may also set M to other positive integers according to the filtering requirements.

[0055] In some embodiments, the filter circuit chip 1 is an integrated passive device (IPD) chip. An IPD chip can integrate discrete passive components (e.g., resistors, capacitors, inductors, conductive layers, etc.) internally. Due to the high precision and high integration of integrated passive device chips, using an IPD chip can effectively reduce the size of passive components compared to directly placing them. In this application, integrating the filter circuit onto an IPD chip reduces the space occupied by the filter circuit in the cavity 8.

[0056] In some embodiments, the projection of the second conductive layer 13 onto the second surface 112 along a direction perpendicular to the second surface 112 is the target projection. The structure obtained by cutting the first conductive layer 11 along the target projection in a direction perpendicular to the second surface 112 is a thin-plate structure. The second conductive layer 13, the dielectric layer 12 connected to the second conductive layer, and the thin-plate structure form a parallel-plate capacitor structure in a direction perpendicular to the second surface 112. The second conductive layer 13 and the thin-plate structure serve as capacitor plates in the parallel-plate capacitor structure. The dielectric layer 12 serves as the insulating layer in the parallel-plate capacitor structure. The capacitance value of the parallel-plate capacitor structure is determined based on the dielectric constant of the dielectric layer 12, the thickness of the dielectric layer 12, and the area of ​​the second conductive layer 13.

[0057] In some embodiments, the first conductive layer 11 may have a deep trench structure, and the dielectric layer 12 and the second conductive layer 13 are backfilled in the deep trench structure. The deep trench structure can increase the area of ​​the capacitor plates in the parallel plate capacitor structure, thereby enabling the parallel plate capacitor structure to have a larger capacitance value.

[0058] In some embodiments, see Figure 5 As shown, the conductive trace 14 includes multiple elongated metal pieces 141 and multiple bends 142; the multiple elongated metal pieces 141 are connected sequentially through the bends 142; the conductive trace 14 is connected to the second conductive layer 13 through the bends 142. The conductive trace 14 serves as a resistor in the filter circuit, wherein the elongated metal pieces 141 can provide a large resistance value and a very small parasitic capacitance value. The second conductive layer 13 is a rectangular thin sheet, which can form a very small parasitic resistance value while providing a large capacitance value.

[0059] In some embodiments, the resistance value of the conductive trace 14 can be determined by configuring the thickness, width, length, and material of the conductive trace 14.

[0060] In some embodiments, the first conductive layer 11 is made of low-resistivity silicon, which is a conductor formed by doping impurities such as boron and phosphorus into a single-crystal silicon material and has good conductivity.

[0061] In some embodiments, the dielectric layer 12 is made of a material with a high dielectric constant, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0062] In some embodiments, the conductive trace 14 is made of metal; specifically, it can be one of copper-aluminum alloy (AlCu), molybdenum (Mo), and titanium (Ti).

[0063] In some embodiments, the second conductive layer 13 is made of metal, specifically, one of copper-aluminum alloy (AlCu), molybdenum (Mo), and titanium (Ti).

[0064] In some embodiments, the grounding terminal 15 is made of metal; specifically, it can be one of copper-aluminum alloy (AlCu), molybdenum (Mo), and titanium (Ti).

[0065] In some embodiments, the pad 16 is made of metal, specifically, it can be one of copper-aluminum alloy (AlCu), molybdenum (Mo), titanium (Ti), titanium-nickel-gold alloy, or titanium-tungsten-gold alloy.

[0066] In some embodiments, see Figure 3 and Figure 4 As shown, the plurality of pads 16 includes 2×M+1 pads; the 2×M+1 pads include: M first pads 161, M second pads 162, and 1 third pad 163; the M first pads 161 are respectively connected to the M second conductive layers 13; the M second pads 162 are respectively connected to the M conductive traces 14; and the third pad 163 is connected to the ground terminal 15.

[0067] In some embodiments, see Figure 4 and Figure 6 As shown, the chip further includes a passivation layer 17, which is disposed on the second surface 112 of the first conductive layer 11. The passivation layer 17 encapsulates the M dielectric layers 12, M second conductive layers 13, M conductive traces 14, and the ground terminal 15. The passivation layer 17 is used to protect the second conductive layers 13, conductive traces 14, and ground terminal 15. The material of the passivation layer 17 can be organic materials such as polyimide (PI), polyethylene terephthalate (PET), and polydimethylsiloxane (PDMS).

[0068] In some embodiments, see Figure 4 As shown, the passivation layer 17 has multiple through holes on the side away from the second surface 112; the pad 16 passes through the through holes and is connected to the M second conductive layers, the M conductive traces 14, and the ground terminal 15.

[0069] In some embodiments, Figure 9This is the equivalent circuit diagram of the filter circuit corresponding to M=2. As a low-pass filter, the filter circuit has a preset cutoff frequency. Signals below the cutoff frequency (e.g., radio frequency signals) entering the filter circuit can pass through, while signals above or equal to the cutoff frequency are filtered out. In the case of M=2, the conductive trace 14 specifically includes a first conductive trace R1 and a second conductive trace R2. The second conductive layer 13 connected to the first conductive trace R1 is denoted as N1. The projection of N1 onto the second surface 112 is called the first target projection. The structure obtained by cutting the first conductive layer 11 along a direction perpendicular to the second surface 112 is the first thin-plate structure P1. The dielectric layer 12 between P1 and N1 is denoted as Q1. N1, Q1, and P1 form the first capacitor C1. The second conductive layer 13 connected to the second conductive trace R2 is denoted as N2. The projection of N2 onto the second surface 112 is called the second target projection. The structure obtained by cutting the first conductive layer 11 along the direction perpendicular to the second surface 112 using the second target projection is called the second thin plate structure P2. The dielectric layer 12 between P2 and N2 is denoted as Q2. N2, Q2, and P2 form the second capacitor C2. Vout1 represents the first output terminal and is connected to the second pad 162 connected to the first conductive trace R1. Vout2 represents the second output terminal and is connected to the second pad 162 connected to the second conductive trace R2. Vin1 represents the first input terminal and is connected to the first pad 161 connected to N1. Vin2 represents the second input terminal and is connected to the first pad 161 connected to N2. The ground terminal 15 is connected to the third pad 163. The first input terminal Vin1, the first conductive trace R1, the first capacitor C1, and the first output terminal Vout1 constitute a first low-pass filter. The capacitance of the first capacitor C1 and the resistance of the first conductive trace R1 together determine the first cutoff frequency of the first low-pass filter. When the target signal is input through the first input terminal Vin1, due to the high impedance of the first capacitor C1, signals in the target signal with frequencies lower than the first cutoff frequency can pass through the first conductive trace R1 and then be output through the first output terminal Vout1. However, for signals in the target signal with frequencies greater than or equal to the first cutoff frequency, the impedance of the first capacitor C1 decreases, effectively shorting the first output terminal Vout1 and the ground terminal 15. Signals in the target signal with frequencies greater than or equal to the first cutoff frequency cannot reach the first output terminal Vout1, thus achieving low-pass filtering. Similarly, the second input terminal Vin2, the second conductive trace R2, the second capacitor C2, and the second output terminal Vout2 constitute a second low-pass filter. The capacitance of the second capacitor C2 and the resistance of the second conductive trace R2 together determine the second cutoff frequency of the second low-pass filter. The second low-pass filter can filter out signals with frequencies greater than or equal to the second cutoff frequency. The resistance value of the conductive trace 14 can be configured between 10Ω and 1kΩ, preferably between 50Ω and 200Ω.The capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be configured between 10pF and 1nF, preferably between 50pF and 200pF. Preferably, the cutoff frequency of the filter circuit is configured between 10MHz and 100MHz.

[0070] Figures 3 to 6 ( Figure 3 , Figure 5 (The passivation layer 17 is not shown) provides the filter circuit chip 1 corresponding to Embodiment 1, with M conductive traces 14 and M second conductive layers 13 disposed on the same layer.

[0071] Figure 7 and Figure 8 ( Figure 7 (Passivation layer 17 not shown) provides a filter circuit chip 1 corresponding to Embodiment 2. The conductive traces 14 are not in contact with the dielectric layer 12. M conductive traces 14 are disposed on the M second conductive layers 13. The second conductive layers 13 and the conductive traces 14 are spaced apart in a direction perpendicular to the second surface 112, that is, the conductive traces 14 and the second conductive layers 13 are arranged on different planes. The filter circuit chip 1 also includes a passivation layer 17, which is disposed on the second surface 112 of the first conductive layer 11. The passivation layer 17 encloses the M dielectric layers 12, the M second conductive layers 13, the M conductive traces 14, and the ground terminal 15. At least a portion of the passivation layer 17 is filled in the gaps between the second conductive layers 13 and the conductive traces 14. In both Embodiment 1 and Embodiment 2, the conductive trace 14 is configured with the same resistance value (i.e., the volume of the conductive trace 14 is fixed), and the capacitor is configured with the same capacitance value. However, in Embodiment 2, the horizontal length of the conductive trace 14 is reduced, and the horizontal length of the filter circuit chip 1 is also reduced, while the thickness is increased by only a few hundred nanometers, which is negligible. Therefore, the filter circuit chip 1 in Embodiment 2 has a smaller volume compared to Embodiment 1. In Embodiment 1, there is still a small amount of parasitic capacitance between the conductive trace 14 and the first conductive layer 11. In Embodiment 2, because the passivation layer 17 is thicker, its parasitic capacitance is greatly reduced. Therefore, the passivation layer 17 in Embodiment 2 can use a material with a lower dielectric constant.

[0072] In some embodiments, an inductor may be integrated into the filter circuit chip 1 according to filtering requirements.

[0073] In some embodiments, when M is a large value, the second conductive layer 13 and the conductive trace 14 can be arranged in two or more layers.

[0074] Please see Figure 10This application proposes a packaging structure for a microphone assembly, comprising a filter circuit chip 1, an ASIC chip 2, a microphone chip 3, a housing 4, a circuit board 5, a first wire 6, and a second wire 7 as described in any of the above embodiments; the housing 4 is disposed on one side of the circuit board 5, and the housing 4 and the circuit board 5 form a cavity 8; the filter circuit chip 1 and the ASIC chip 2 are stacked in the cavity 8 along the thickness direction of the microphone assembly packaging structure; the pads 16 in the filter circuit chip 1 are connected to the circuit board 5, and the first surface 111 in the filter circuit chip 1 is connected to the ASIC chip 2; the microphone chip 3 is disposed on the circuit board 5 and housed in the cavity 8; the ASIC chip 2 is electrically connected to the circuit board 5 through the first wire 6 and to the microphone chip 3 through the second wire 7; the circuit board 5 is provided with a sound inlet hole 9 extending along the thickness direction of the microphone assembly packaging structure, or the housing 4 is provided with a sound inlet hole 9 extending along the thickness direction of the microphone assembly packaging structure.

[0075] Based on the above embodiments, this application uses a filter circuit chip 1. Compared to laying the filter circuit separately inside the cavity 8, this effectively reduces the space occupied in the cavity 8, thereby enabling the microphone assembly's packaging structure to have better sound pickup performance. It also allows the cavity 8 to accommodate more sensors for richer integrated sensing functions. Compared to embedding the filter circuit inside the circuit board 5, this application reduces costs and improves reliability.

[0076] In some embodiments, the ASIC (Application Specific Integrated Circuit) chip 2 refers to an integrated circuit chip used to provide a bias voltage to the microphone chip 3 and amplify electrical signals.

[0077] In some embodiments, the microphone chip 3 is a MEMS (Micro-Electro-Mechanical System) microphone chip, used to input or output voice signals through the sound inlet 9.

[0078] In some embodiments, please refer to Figure 10 The first surface 111 of the filter circuit chip 1 is connected to the ASIC chip 2 by adhesive 10.

[0079] In some embodiments, please refer to Figure 10 When the circuit board 5 has a sound inlet hole 9 that extends through the thickness direction of the microphone assembly's packaging structure, the microphone chip 3 covers the sound inlet hole 9.

[0080] In some embodiments, the circuit board 5 is provided with circuit board pads, one end of which is connected to the first pad 161 and the second pad 162, and the other end of which can be connected to the pins of the microphone chip 3.

[0081] This application proposes a microphone, the microphone including the encapsulation structure of a microphone assembly as described in any of the preceding embodiments.

[0082] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A filter circuit chip, characterized in that, The chip includes a first conductive layer (11), M dielectric layers (12), M second conductive layers (13), M conductive traces (14), a ground terminal (15), and multiple pads (16); M is a positive integer; The first conductive layer (11) has opposing first surfaces (111) and second surfaces (112); The M dielectric layers (12) are disposed between the first conductive layer (11) and the second conductive layer (13), and are spaced apart in a direction parallel to the second surface (112). The M second conductive layers (13) are disposed corresponding to the M dielectric layers (12) and are arranged on the surface of the M dielectric layers (12) away from the first conductive layer (11); The second conductive layer (13), the conductive trace (14), and the ground terminal (15) are all connected to the pad (16); The grounding terminal (15) is also connected to the first conductive layer (11); The M second conductive layers (13) are connected one-to-one with the M conductive traces (14); At least a portion of the first conductive layer (11), the dielectric layer (12), and the second conductive layer (13) form a capacitor structure in a direction perpendicular to the second surface (112), and the M conductive traces (14) form a resistive structure.

2. The chip according to claim 1, characterized in that, The conductive trace (14) includes multiple elongated metal parts (141) and multiple bends (142); the multiple elongated metal parts (141) are connected in sequence through the bends (142); the conductive trace (14) is connected to the second conductive layer (13) through the bends (142).

3. The chip according to claim 1, characterized in that, The first conductive layer (11) is made of low-resistivity silicon.

4. The chip according to claim 1, characterized in that, The plurality of pads (16) includes 2×M+1 pads; the 2×M+1 pads include: M first pads (161), M second pads (162), and one third pad (163); The M first pads (161) are respectively connected to the M second conductive layers (13); the M second pads (162) are respectively connected to the M conductive traces (14); and the third pad (163) is connected to the ground terminal (15).

5. The chip according to claim 1, characterized in that, The chip also includes a passivation layer (17), which is disposed on the second surface (112) of the first conductive layer (11). The passivation layer (17) encapsulates the M dielectric layers (12), the M second conductive layers (13), the M conductive traces (14), and the ground terminal (15).

6. The chip according to claim 5, characterized in that, The passivation layer (17) has multiple through holes on the side away from the second surface (112); the pad (16) passes through the through holes and is connected to the M second conductive layers (13), the M conductive traces, and the ground terminal (15).

7. The chip according to claim 1, characterized in that, The M conductive traces (14) are disposed in the same layer as the M second conductive layers (13).

8. The chip according to claim 1, characterized in that, The M conductive traces (14) are disposed on the M second conductive layers (13); the second conductive layers (13) and the conductive traces (14) are spaced apart in a direction perpendicular to the second surface (112).

9. The chip according to claim 8, characterized in that, The chip also includes a passivation layer (17), and at least a portion of the passivation layer (17) is filled within the interval.

10. A packaging structure for a microphone assembly, characterized in that, The packaging structure of the microphone assembly includes a filter circuit chip (1), an ASIC chip (2), a microphone chip (3), a housing (4), a circuit board (5), a first wire (6), and a second wire (7) as described in any one of claims 1 to 9. The housing (4) is disposed on one side of the circuit carrier plate (5), and the housing (4) and the circuit carrier plate (5) surround each other to form a cavity (8); The filter circuit chip (1) and the ASIC chip (2) are stacked in the cavity (8) along the thickness direction of the microphone assembly's packaging structure; The pads (16) in the filter circuit chip (1) are connected to the circuit carrier board (5), and the first surface (111) in the filter circuit chip (1) is connected to the ASIC chip (2). The microphone chip (3) is disposed on the circuit board (5) and housed in the cavity (8); The ASIC chip (2) is electrically connected to the circuit board (5) via the first wire (6) and to the microphone chip (3) via the second wire (7); The circuit board (5) is provided with a sound inlet hole (9) that extends through the thickness direction of the microphone assembly's encapsulation structure, or the housing (4) is provided with a sound inlet hole (9) that extends through the thickness direction of the microphone assembly's encapsulation structure.

11. The packaging structure of the microphone assembly according to claim 10, characterized in that, When the circuit board (5) has a sound inlet hole (9) that extends through the thickness direction of the microphone assembly's packaging structure, the microphone chip (3) covers the sound inlet hole (9).

12. A microphone, characterized in that, The microphone includes the encapsulation structure of a microphone assembly as described in any one of claims 10 or 11.

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