Display device

Abstract

A display device is provided. The display device includes a pixel including a sub-pixel region, the sub-pixel region including a first sub-pixel region and a second sub-pixel region. The display device includes: a semiconductor wafer including a substrate; bonding a conductive layer on the semiconductor wafer; a reflective conductive layer on the bonding conductive layer; and a light emitting element electrically connected to the reflective conductive layer. The bonding conductive layer includes a first bonding conductive layer in the first sub-pixel region and a second bonding conductive layer in the second sub-pixel region. The first bonding conductive layer and the second bonding conductive layer have different thicknesses. The reliability of an electrical signal provided to the display device is improved, process risks are reduced, and display quality is improved.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0074222, filed on June 7, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the disclosure relate to a display device and a method of manufacturing a display device. BACKGROUND

[0003] In recent years, the increasing interest in information displays has prompted continued research and development of display devices.

[0004] An organic light emitting diode (OLED) is an active light emitting type (class) display element that provides several advantages including a wide viewing angle, high contrast, low voltage operation (i.e., it is capable of being driven at low voltage), a lightweight and thin design, and a fast response time (speed).

[0005] An organic light emitting diode (OLED) can emit light by virtue of (by means of) an electrical signal supplied via a plurality of conductive lines. These conductive lines can have certain electrical characteristics (intended and / or specific electrical characteristics), such as electrical resistance. If these electrical characteristics (of the conductive lines) are altered (distorted), the reliability of the light emitting element can be compromised (and / or the light emitting element can be damaged).

[0006] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and therefore it can contain information that does not constitute prior art. SUMMARY

[0007] The object of the present utility model is to provide a display device in which the reliability of an electrical signal provided to the display device can be improved.

[0008] The object of the present utility model is to provide a display device in which challenges (e.g., complexity or risk of undesirable characteristics) in the manufacturing process can be reduced.

[0009] The object of the present utility model is to provide a display device having excellent or suitable display quality.

[0010] Additional aspects will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following disclosure and may be learned by practice of the disclosed embodiments.

[0011] According to one or more embodiments of the disclosure, a display device includes a pixel including a sub-pixel area, the sub-pixel area including a first sub-pixel area and a second sub-pixel area. The display device includes a semiconductor wafer including a substrate, a bonding conductive layer disposed on the semiconductor wafer, a reflective conductive layer disposed on the bonding conductive layer, and a light emitting element electrically connected to the reflective conductive layer. The bonding conductive layer includes a first bonding conductive layer in the first sub-pixel area and a second bonding conductive layer in the second sub-pixel area. The first bonding conductive layer and the second bonding conductive layer have different thicknesses.

[0012] According to one or more embodiments, the display device can further include an interlayer insulating layer covering the reflective conductive layer and disposed between the reflective conductive layer and the light emitting element. The interlayer insulating layer can have different thicknesses in the sub-pixel areas.

[0013] According to one or more embodiments, the display device can further include a partition wall disposed on the interlayer insulating layer between the sub-pixel areas.

[0014] According to one or more embodiments, the display device can further include a partition wall insulating layer disposed on the partition wall. The partition wall can include silicon.

[0015] According to one or more embodiments, the bonding conductive layer can include copper (Cu). The reflective conductive layer can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and / or an alloy of two or more materials selected from among them. The partition wall insulating layer can include one or more of silicon oxide (SiO x ), silicon nitride (SiN x ), titanium oxide (TiO x ), and aluminum oxide (Al x O y ).

[0016] According to one or more embodiments, the display device can further include a first insulating layer and a second insulating layer disposed between the partition wall and the interlayer insulating layer and having different widths. That is, the display device can further include a first insulating layer and a second insulating layer disposed between the partition wall and the interlayer insulating layer (e.g., disposed between the partition wall and the interlayer insulating layer), and the first insulating layer and the second insulating layer have different widths.

[0017] According to one or more embodiments, the semiconductor wafer can include a pixel circuit on the substrate. The bonding conductive layer can be electrically connected to the pixel circuit. The via layer can not be interposed between the bonding conductive layer and the semiconductor wafer (e.g., the bonding conductive layer and the semiconductor wafer can directly contact each other).

[0018] According to one or more embodiments, the bonding conductive layer and the semiconductor wafer can be bonded to each other by solder bonding or Cu-Cu hybrid bonding.

[0019] According to one or more embodiments, the display device can further include a lower conductive layer disposed between the bonding conductive layer and the reflective conductive layer. The reflective conductive layer can include a first reflective conductive layer in the first sub-pixel area and a second reflective conductive layer in the second sub-pixel area. The first reflective conductive layer and the second reflective conductive layer can have the same thickness.

[0020] According to one or more embodiments, the semiconductor wafer can be a CMOS (Complementary Metal Oxide Semiconductor) wafer.

[0021] According to one or more embodiments, the display device can further include a packaging layer disposed on the light emitting element, a color filter on the packaging layer, and a lens on the color filter. The display device can be an OLEDoS (OLED on Silicon) display device.

[0022] A method of manufacturing a display device according to one or more embodiments of the disclosure includes the steps of: supplying a bonding assembly including a bonding conductive layer; supplying a semiconductor wafer; bonding the semiconductor wafer and the bonding assembly through the bonding conductive layer; and forming a light emitting element.

[0023] According to one or more embodiments, the step of supplying the bonding assembly can include: forming a first substrate insulating layer, a second substrate insulating layer, and a substrate interlayer insulating layer on a substrate; forming the interlayer insulating layer to have different thicknesses in some areas by removing at least a portion of the substrate interlayer insulating layer; and forming a substrate reflective conductive layer on the interlayer insulating layer. The substrate reflective conductive layer can be formed after the interlayer insulating layer is formed.

[0024] According to one or more embodiments, the step of supplying the bonding assembly can further include: forming a first reflective conductive layer and a second reflective conductive layer by removing at least a portion of the substrate reflective conductive layer; forming a lower conductive layer covering the first reflective conductive layer and the second reflective conductive layer; and forming the bonding conductive layer to include a first bonding conductive layer disposed on the first reflective conductive layer and a second bonding conductive layer disposed on the second reflective conductive layer.

[0025] According to one or more embodiments, the step of supplying the bonding assembly can further include: performing a planarization process by removing at least a portion of the first bonding conductive layer and the second bonding conductive layer such that upper surfaces of the first bonding conductive layer and the second bonding conductive layer have planar surfaces coinciding with (e.g., substantially coplanar) each other.

[0026] According to one or more embodiments, in the step of combining the semiconductor wafer and the bonding assembly, the bonding conductive layer and the semiconductor wafer can be combined with each other by solder bonding or Cu-Cu hybrid bonding.

[0027] According to one or more embodiments, the method of manufacturing a display device can further include, after combining the semiconductor wafer and the bonding assembly, supplying a separation wall substrate by performing a back-grinding process on the substrate.

[0028] According to one or more embodiments, the method of manufacturing a display device can further include forming separation walls that are spaced apart and / or separated (e.g., spaced apart or separated) from each other and expose the first substrate insulating layer by removing at least a portion of the separation wall substrate; forming a separation wall substrate insulating layer that covers the separation walls and the first substrate insulating layer; exposing a second substrate insulating layer by etching the separation wall substrate insulating layer and the first substrate insulating layer; and exposing an interlayer insulating layer by etching the second substrate insulating layer.

[0029] According to one or more embodiments, the light emitting element can include an anode electrode, an emission structure, and a cathode electrode. The step of forming the light emitting element can include forming the anode electrode between the separation walls; forming the emission structure on the anode electrode between the separation walls; and forming the cathode electrode that covers the emission structure and the anode electrode.

[0030] According to one or more embodiments, the method of manufacturing a display device can further include forming a color filter on the light emitting element; and forming a lens on the color filter.

[0031] In the present disclosure, by providing the structure of the semiconductor wafer, the bonding conductive layer on the semiconductor wafer, the reflective conductive layer on the bonding conductive layer, and the light emitting element, and by providing the bonding conductive layer in the plurality of pixel regions to have different thicknesses, the reliability of the electrical signal provided to the display device is improved, the process risk is reduced, and the display quality is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure, and together with the description serve to explain the principles of the present disclosure. In the drawings,

[0033] Figure 1 is a plan view schematically showing a display device according to one or more embodiments of the present disclosure;

[0034] Figure 2 is a cross-sectional view schematically showing a display device according to one or more embodiments of the present disclosure;

[0035] Figure 3is a plan view schematically illustrating a pixel according to one or more embodiments of the present disclosure;

[0036] Figure 4 is a plan view schematically illustrating a pixel according to one or more embodiments of the present disclosure;

[0037] Figure 5 is a plan view schematically illustrating a pixel according to one or more embodiments of the present disclosure;

[0038] Figure 6 is a cross-sectional view schematically illustrating a display device according to one or more embodiments of the present disclosure, taken along line A-A' of Figure 1

[0039] Figure 7 and Figure 8 each is a cross-sectional view schematically illustrating a light emitting element according to one or more embodiments of the present disclosure;

[0040] Figures 9 to 22 each is a cross-sectional view schematically illustrating a process step (e.g., a process action or task) of a method of manufacturing a display device according to one or more embodiments of the present disclosure;

[0041] Figure 23 is a block diagram illustrating a display system according to one or more embodiments of the present disclosure;

[0042] Figure 24 is a perspective view of a head-mounted display device illustrating an example of an application of the display system as Figure 23

[0043] Figure 25 is a diagram of a head-mounted display device illustrating the display system as Figure 24 worn by a user according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] The present disclosure can be modified in a number of alternative forms, and as such specific embodiments will be shown and described in the drawings and more particularly described below. It is to be understood, however, that this is not intended to limit the present disclosure to the particular forms disclosed, but on the contrary, it is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

[0045] ​​Hereinafter, example embodiments will be described in greater detail with reference to the accompanying drawings. The present disclosure may, however, be embodied in various different forms, and should not be construed as being limited to only the embodiments set forth herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. As such, processes, elements and techniques that are not necessary for an understanding of the aspects and features of the present disclosure can not be described.

[0046] It will be understood that, although the terms "first", "second", "third", and the like can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0047] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used in this disclosure, specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. Additionally, when a first component is "on" a second component, the first component can be "directly on" the second component, and a third component can be interposed therebetween. Also, in the disclosure, when a first component is formed "on" a second component, a direction in which the first component is formed is not limited to an upward direction of the second component, but can include a side direction or a downward direction of the second component. Conversely, when a first component is "under" a second component, the first component can be "directly under" the second component, and a third component can be interposed therebetween.

[0049] As used herein, the term “and / or,” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” “one or more of,” and “one or more,” when preceding the enumeration of a list, shall be understood to include the at least one of, one or more of, or one of each separately recited member of the list. For example, “at least one of a, b, and c,” “one or more of a, b, and c,” and “one or more of a, b, and c” shall be understood as including a, b, c individually as well as a combination of a and b, a and c, b and c, a, b, and c, as well as any variations thereof.

[0050] It will be understood that when an element such as a layer, film, region, or portion is referred to as being “on” another element, connected to, or coupled to another element, it can be directly on, directly connected to, or directly coupled to the other element or one or more intervening elements can be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent” another element or layer, there are no intervening elements or layers present. It will also be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements or one or more intervening elements can also be present.

[0051] For ease of explanation, spatial relative terms such as “on,” “under,” “below,” “lower,” “above,” “upper,” and the like, can be used herein to describe one element or feature’s relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “under” or “below” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “under” and “below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0052] As used herein, the term “use” and variations thereof can be considered synonymous with the term “utilize” and variations thereof.

[0053] Unless otherwise specified, like drawing reference numerals in the accompanying drawings and written description denote like elements, so that repeated description thereof will be omitted. In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity.

[0054] The present disclosure relates to a display apparatus and a method of manufacturing a display apparatus. Hereinafter, a display apparatus and a method of manufacturing a display apparatus according to one or more embodiments will be described with reference to the accompanying drawings.

[0055] Figure 1 is a plan view schematically showing a display apparatus according to one or more embodiments of the present disclosure.

[0056] Referring to Figure 1 , the display apparatus 100 according to one or more embodiments can be configured to emit light.

[0057] The display apparatus 100 can include a display area DA and a non-display area NDA. The display apparatus 100 can display an image through the display area DA. The non-display area NDA can be disposed around the display area DA.

[0058] The display apparatus 100 can include a substrate SUB, a sub-pixel SP, and a pad PD (also referred to as a "solder pad" or a "soldering pad").

[0059] When the display apparatus 100 is used as a display screen of a head-mounted display (HMD) apparatus, a virtual reality (VR) apparatus, a mixed reality (MR) apparatus, and / or an augmented reality (AR) apparatus, etc., the display apparatus 100 can be positioned very close to a user's eyes. In this case, it can be desirable or necessary to have a sub-pixel SP having a relatively high degree of integration.

[0060] To increase the degree of integration of the sub-pixel SP, the substrate SUB can be provided as a silicon substrate. The sub-pixel SP can be formed on the substrate SUB which is a silicon substrate. The display apparatus 100 including a plurality of layers formed on the substrate SUB which is a silicon substrate can be referred to as an OLED on silicon (OLEDoS) display apparatus.

[0061] The sub-pixel SP can be disposed in the display area DA on the substrate SUB. The sub-pixel SP can be disposed in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto. For example, the sub-pixel SP can be disposed in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixel SP can be disposed in a PENTILE ® shape (PENTILE ® is a registered trademark of Samsung Display Co., Ltd.). The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0062] The plane defined in this specification (e.g., a plan view) may be a plane extending in a first direction DR1 and a second direction DR2, and may be defined based on a plane on which the substrate SUB is disposed. According to one or more embodiments, a third direction DR3 may be the thickness direction of the substrate SUB, and the third direction DR3 may be the direction along which light is emitted from the display device 100.

[0063] Subpixels SP can have one or more suitable shapes in a planar graph, and the shape of subpixels SP is not limited to specific examples.

[0064] Each of the sub-pixels SP may include at least one light-emitting element LD configured to generate light (see example...). Figure 6 Therefore, each subpixel SP can produce light of a specific color (such as red, green, blue, cyan, magenta, or yellow). Within subpixels SP, two or more subpixels SP can constitute a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form pixel PXL.

[0065] In the following description, subpixel SP will include a first subpixel SP1 (see example) that provides light of a first color (e.g., red). Figure 3 ), and the second sub-pixel SP2 that provides light of a second color (e.g., green) (see example) Figure 3 ) and the third sub-pixel SP3 that provides light of a third color (e.g., blue) (see example) Figure 3 One or more embodiments of ) are used as examples.

[0066] According to one or more embodiments, the first sub-pixel SP1 may be a red pixel and may provide light in the wavelength range of 600nm to 750nm. The second sub-pixel SP2 may be a green pixel and may provide light in the wavelength range of 480nm to 560nm. The third sub-pixel SP3 may be a blue pixel and may provide light in the wavelength range of 370nm to 460nm.

[0067] Components for controlling the sub-pixel SP can be arranged on the substrate SUB in the non-display area NDA. For example, wiring connected to the sub-pixel SP (e.g., gate lines and / or data lines for driving the sub-pixel SP, etc.) can be arranged in the non-display area NDA. Additionally, gate drivers, data drivers, voltage generators, controllers, and / or temperature sensors for acquiring the drive signals supplied to the sub-pixel SP can be integrated into the non-display area NDA of the display device 100. However, this disclosure is not limited thereto.

[0068] The pads PD can be disposed in the non-display area NDA on the substrate SUB. The pads PD can be electrically connected to the sub-pixels SP by the wirings. For example, the pads PD can be connected to the sub-pixels SP by the data lines.

[0069] The pads PD can interface components within the display area DA and the non-display area NDA with other components of the display device 100. In one or more embodiments, voltages and signals required for operations of the components included in the display device 100 can be provided from the driver integrated circuit through the pads PD. For example, the data lines can be electrically connected to the driver integrated circuit through the pads PD. For example, a power supply voltage for driving the sub-pixels SP can be received from the driver integrated circuit through the pads PD. For example, a gate control signal for controlling the gate driver can be transmitted from the driver integrated circuit to the gate driver through the pads PD.

[0070] In one or more embodiments, the circuit board can be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. In this case, the circuit board can be a flexible circuit board or a flexible film made of a flexible material. The driver integrated circuit can be mounted on the circuit board and electrically connected to the pads PD.

[0071] In one or more embodiments, the display area DA can have one or more suitable shapes. The display area DA can have a closed loop shape including straight sides and / or curved sides. For example, the display area DA can have a shape such as a polygonal shape, a circular shape, a semi-circular shape, or an elliptical shape.

[0072] In one or more embodiments, the display device 100 can have a flat display surface. In one or more embodiments, the display device 100 can have a display surface that is at least partially rounded. In one or more embodiments, the display device 100 can be bent, folded, or rolled. In these cases, the display device 100 (specifically, the substrate SUB included in the display device 100) can include a material having a flexible property.

[0073] Figure 2 FIG. 1 is a cross-sectional view schematically illustrating a display device according to one or more embodiments of the present disclosure.

[0074] Referring to Figure 2 The display device 100 according to one or more embodiments can include a semiconductor wafer WAF, an intermediate conductive structure layer MCL, a light emitting element layer LEL, and a light function layer LFL.

[0075] The semiconductor wafer WAF can include a substrate SUB. The substrate SUB can form a base on which other components of the display device 100 are disposed. The substrate SUB can include a silicon substrate.

[0076] According to one or more embodiments, the semiconductor wafer WAF can be a CMOS (Complementary Metal Oxide Semiconductor) wafer, and can include a pixel circuit PXC (see, for example, FIG. 1) for driving a sub-pixel SP. Figure 6 ).

[0077] The intermediate conductive structure layer MCL can be disposed on the substrate SUB. A portion of the intermediate conductive structure layer MCL can bind the substrate SUB and the intermediate conductive structure layer MCL. The intermediate conductive structure layer MCL can form a resonance path based on a different resonance distance for each of the sub-pixels SP, thereby improving light emission efficiency of the sub-pixels SP.

[0078] The light emitting element layer LEL can be a layer including a light emitting element LD that provides light. The light provided by the light emitting element LD can be output to the outside along the third direction DR3.

[0079] The light function layer LFL can be disposed on the light emitting element layer LEL. The light function layer LFL can include one or more suitable function layers to more clearly implement a full-color display structure and improve light output efficiency. For example, the light function layer LFL can include a color filter CF (see, for example, FIG. 1), and can further include a lens LS (see, for example, FIG. 1). Figure 6 ). Figure 6 ).

[0080] Figure 3 is a plan view schematically illustrating a pixel according to one or more embodiments of the disclosure.

[0081] Referring to Figure 3 , the pixel PXL can include sub-pixels SP disposed in the first direction DR1. For example, the sub-pixels SP can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 disposed in the first direction DR1. The emission areas EMA can include first to third emission areas EMA1 to EMA3.

[0082] The first sub-pixel SP1 can include the first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second sub-pixel SP2 can include the second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third sub-pixel SP3 can include the third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0083] The sub-pixel SP can include a sub-pixel area SPA in which light of one color is visually recognized. The sub-pixel area SPA can include a first sub-pixel area SPA1 in which light of a first color is visually recognized formed with the first sub-pixel SP1, a second sub-pixel area SPA2 in which light of a second color is visually recognized formed with the second sub-pixel SP2, and a third sub-pixel area SPA3 in which light of a third color is visually recognized formed with the third sub-pixel SP3.

[0084] The first emission area EMA1 can be an area in which light is emitted from a portion of the emission structure EMS (e.g., a first emission structure EMS1) corresponding to the first sub-pixel SP1 (see, e.g., FIG. 1A). Figure 6 The second emission area EMA2 can be an area in which light is emitted from a portion of the emission structure EMS (e.g., a second emission structure EMS2) corresponding to the second sub-pixel SP2 (see, e.g., FIG. 1A). Figure 6 The third emission area EMA3 can be an area in which light is emitted from a portion of the emission structure EMS (e.g., a third emission structure EMS3) corresponding to the third sub-pixel SP3 (see, e.g., FIG. 1A). Figure 6

[0085] Figure 4 is a plan view schematically illustrating a pixel according to one or more embodiments of the disclosure.

[0086] Referring to Figure 4 , the first sub-pixel SP1 and the second sub-pixel SP2 can be arranged in a second direction DR2. The third sub-pixel SP3 can be arranged in a first direction DR1 with respect to each of the first sub-pixel SP1 and the second sub-pixel SP2.

[0087] The second sub-pixel SP2 can have a larger area than the first sub-pixel SP1, and the third sub-pixel SP3 can have a larger area than the second sub-pixel SP2. Accordingly, the second emission area EMA2 can have a larger area than the first emission area EMA1, and the third emission area EMA3 can have a larger area than the second emission area EMA2. However, the disclosure is not limited thereto. For example, the first sub-pixel SP1 and the second sub-pixel SP2 can have substantially the same area, and the third sub-pixel SP3 can have a larger area than each of the first sub-pixel SP1 and the second sub-pixel SP2. As such, the areas of the first sub-pixel SP1 to the third sub-pixel SP3 can vary according to embodiments.

[0088] Figure 5 is a plan view schematically illustrating a pixel according to one or more embodiments of the disclosure.

[0089] Referring to Figure 5 ​The first to third sub-pixels SP1 to SP3 can have a polygonal shape when viewed from the third direction DR3 (e.g., in a plan view). For example, the first to third sub-pixels SP1 to SP3 can have a hexagonal shape as illustrated in FIG. 12B. Figure 5

[0090] The first to third emission areas EMA1 to EMA3 can have a circular shape when viewed from the third direction DR3 (e.g., in a plan view). However, the present disclosure is not limited thereto. For example, each of the first to third emission areas EMA1 to EMA3 can have a polygonal shape.

[0091] The first sub-pixel SP1 and the third sub-pixel SP3 can be arranged in the first direction DR1. The second sub-pixel SP2 can be arranged in a direction inclined at an acute angle (or obliquely) with respect to the second direction DR2 with respect to the first sub-pixel SP1.

[0092] Figures 3 to 5 The arrangement of the sub-pixels SP illustrated in FIG. 12B is merely an example, and the present disclosure is not limited thereto. Each pixel PXL can include two or more sub-pixels SP, and the sub-pixels SP can be arranged in one or more suitable manners. In addition, the sub-pixels SP can have one or more suitable shapes, and their emission areas EMA can also have one or more suitable shapes.

[0093] A display device 100 including an intermediate conductive structure layer MCL, etc., according to one or more embodiments of the present disclosure will be described with reference to Figures 6 to 8

[0094] Figure 6 is a cross-sectional view schematically illustrating a display device according to one or more embodiments of the present disclosure. Figure 6 is a schematic cross-sectional view taken along line A-A' in Figure 1 Figure 6 A cross-sectional structure within a display area DA of the display device 100 is schematically illustrated. Figure 7 and Figure 8 Each of

[0095] With reference to Figures 6 to 8 The sub-pixels SP forming the sub-pixel area SPA within the display area DA can be arranged (e.g., formed) on a semiconductor wafer WAF (or a substrate SUB).

[0096] ​​​According to one or more embodiments, the semiconductor wafer WAF can be a CMOS wafer and can include the pixel circuit PXC. The pixel circuit PXC can include a first pixel circuit PXC1 configured to drive the first sub-pixel SP1 and electrically connected to the light emitting elements LD in the first sub-pixel area SPA1, a second pixel circuit PXC2 configured to drive the second sub-pixel SP2 and electrically connected to the light emitting elements LD in the second sub-pixel area SPA2, and a third pixel circuit PXC3 configured to drive the third sub-pixel SP3 and electrically connected to the light emitting elements LD in the third sub-pixel area SPA3.

[0097] The intermediate conductive structure layer MCL can be disposed on the semiconductor wafer WAF (or the substrate SUB). According to one or more embodiments, the intermediate conductive structure layer MCL can include a bonding conductive layer BO, a lower conductive layer LREL, a reflective conductive layer REL, an intermediate insulating layer MIN, and an interlayer insulating layer ILD.

[0098] The bonding conductive layer BO can be disposed on the semiconductor wafer WAF (or the substrate SUB). The bonding conductive layer BO can be disposed directly on the semiconductor wafer WAF. For example, the bonding conductive layer BO can be in contact with a top surface of the semiconductor wafer WAF.

[0099] The bonding conductive layer BO can include a first bonding conductive layer BO1 included in the first sub-pixel SP1, a second bonding conductive layer BO2 included in the second sub-pixel SP2, and a third bonding conductive layer BO3 included in the third sub-pixel SP3. The first bonding conductive layer BO1 to the third bonding conductive layer BO3 can be spaced apart and / or separated (e.g., spaced apart or separated) from each other.

[0100] The bonding conductive layer BO can bond (e.g., bond) the intermediate conductive structure layer MCL to the semiconductor wafer WAF. The bonding conductive layer BO can be electrically connected to the pixel circuit PXC. For example, the first bonding conductive layer BO1 to the third bonding conductive layer BO3 can be electrically connected to the first pixel circuit PXC1 to the third pixel circuit PXC3.

[0101] The bonding conductive layer BO can be bonded to a conductive pad portion electrically connected to the pixel circuit PXC of the semiconductor wafer WAF. As an example, the semiconductor wafer WAF can include a conductive pad portion electrically connected to the pixel circuit PXC at a top surface, and the bonding conductive layer BO can be bonded to the conductive pad portion. Accordingly, the bonding conductive layer BO can be electrically connected to the pixel circuit PXC while bonding the semiconductor wafer WAF and the intermediate conductive structure layer MCL.

[0102] According to one or more embodiments, the via layer can not be disposed between the bonding conductive layer BO and the semiconductor wafer WAF. For example, the bonding conductive layer BO is not electrically connected to the semiconductor wafer WAF through a via that penetrates the via layer, but the bonding conductive layer BO can form an electrical contact surface with a portion of the semiconductor wafer WAF and can be electrically connected to the pixel circuit PXC. Thus, the risk of excessive increase in electrical resistance due to structures such as vias can be reduced. In addition, because the electrical path is formed based on the bonding conductive layer BO, the electrical resistance in the electrical path between the pixel circuit PXC and the light emitting element LD can be reduced. Thus, the risk of signal distortion for the light emitting element LD to emit light can be reduced, and the reliability of the electrical signal can be improved. In other words, in some embodiments, there can be no via layer between the bonding conductive layer BO and the semiconductor wafer WAF. Instead of being connected through a via, the bonding conductive layer BO directly contacts a portion of the semiconductor wafer WAF and is connected to the pixel circuit PXC. This design reduces the risk of increasing electrical resistance due to vias and similar structures. In addition, because the electrical path is formed by the bonding conductive layer BO, the electrical resistance between the pixel circuit PXC and the light emitting element LD is minimized or reduced. This helps to reduce signal distortion for the light emitting element LD and improves the reliability of the electrical signal.

[0103] The bonding conductive layer BO can be bonded to the semiconductor wafer WAF in one or more suitable ways. For example, the bonding conductive layer BO can be bonded to the semiconductor wafer WAF based on a solder bonding process or the like. The bonding conductive layer BO can be bonded to the semiconductor wafer WAF by Cu-Cu hybrid bonding. According to one or more embodiments, the bonding conductive layer BO can be bonded to the semiconductor wafer WAF based on a fusion bonding process or the like. However, the present disclosure is not limited thereto.

[0104] The bonding conductive layer BO can be patterned by the same (or substantially the same) process and can include the same (or substantially the same) conductive material. According to one or more embodiments, the bonding conductive layer BO can include a conductive material through which a bonding process can be suitably performed. For example, the bonding conductive layer BO can include copper (Cu). However, the present disclosure is not limited thereto.

[0105] The bonding conductive layer BO can have different thicknesses (e.g., the thickness of the bonding conductive layer can vary throughout the bonding conductive layer BO). For example, at least some of the first bonding conductive layer BO1 to the third bonding conductive layer BO3 can have different thicknesses. For example, the first bonding conductive layer BO1 to the third bonding conductive layer BO3 can have different thicknesses. According to one or more embodiments, the thickness of the first bonding conductive layer BO1 can be greater than the thickness of the second bonding conductive layer BO2, and the thickness of the second bonding conductive layer BO2 can be greater than the thickness of the third bonding conductive layer BO3. In this specification, the thickness can be defined based on the third direction DR3 that is the thickness direction of the substrate SUB.

[0106] In such an embodiment, different resonance distances can be defined in each of the sub-pixels SP. Because the resonance distance can be appropriately or suitably defined for each sub-pixel SP, the light output efficiency of the light-emitting element LD can be improved.

[0107] The lower conductive layer LREL can be arranged on the bonding conductive layer BO. The lower conductive layer LREL can be electrically connected to the bonding conductive layer BO.

[0108] The lower conductive layer LREL can include a first lower conductive layer LREL1 included in the first sub-pixel SP1, a second lower conductive layer LREL2 included in the second sub-pixel SP2, and a third lower conductive layer LREL3 included in the third sub-pixel SP3. The first lower conductive layer LREL1 to the third lower conductive layer LREL3 can be spaced apart and / or separated from each other (e.g., spaced apart or separated).

[0109] According to one or more embodiments, the first lower conductive layer LREL1 to the third lower conductive layer LREL3 can have the same (or substantially the same) thickness. According to one or more embodiments, the first lower conductive layer LREL1 to the third lower conductive layer LREL3 can be patterned within the same (or substantially the same) process, and can include the same (or substantially the same) conductive material. For example, the first lower conductive layer LREL1 to the third lower conductive layer LREL3 can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), copper (Cu), and / or copper-manganese alloy, etc. However, the present disclosure is not limited thereto.

[0110] The reflective conductive layer REL can be arranged on the lower conductive layer LREL. The reflective conductive layer REL can be electrically connected to the lower conductive layer LREL.

[0111] The reflective conductive layer REL can include a first reflective conductive layer REL1 included in the first sub-pixel SP1, a second reflective conductive layer REL2 included in the second sub-pixel SP2, and a third reflective conductive layer REL3 included in the third sub-pixel SP3, and the first reflective conductive layer REL1, the second reflective conductive layer REL2, and the third reflective conductive layer REL3 can have the same (or substantially the same) thickness.

[0112] The reflective conductive layer REL can function as a full mirror that reflects light emitted from the emission structure EMS toward the display screen. At least a portion of the reflective conductive layer REL can include a metal material suitable for reflecting light. For example, the metal material can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and / or an alloy of two or more materials selected from among them.

[0113] The intermediate insulating layer MIN can be disposed on the semiconductor wafer WAF (or the substrate SUB) and can be disposed on side surfaces of the bonding conductive layer BO, the lower conductive layer LREL, and the reflective conductive layer REL. The intermediate insulating layer MIN can be disposed on the semiconductor wafer WAF (or the substrate SUB) in an area in which the bonding conductive layer BO, the lower conductive layer LREL, and the reflective conductive layer REL are not disposed.

[0114] A lower surface of the intermediate insulating layer MIN can be disposed in the same plane as a lower surface of the bonding conductive layer BO. For example, the lower surface of the intermediate insulating layer MIN and the lower surface of the bonding conductive layer BO can be disposed by the same (or substantially the same) planarization process (e.g., a chemical mechanical polishing (CMP) process).

[0115] The intermediate insulating layer MIN can include an inorganic material. According to one or more embodiments, the intermediate insulating layer MIN can include silicon nitride (Si x N y wherein x can range from 0 to 3 and y can range from 0 to 4, for example, Si3N4), silicon oxide (SiO x wherein 0 < x ≤ 2, for example, SiO2), silicon oxynitride (SiO x N y wherein x can range from 0 to 2 and y can range from 0 to 4), and aluminum oxide (Al x O y for example, x can range from 0 to 2 and y can range from 0 to 3). However, the present disclosure is not limited thereto.

[0116] An interlayer insulating layer ILD can be disposed on the reflective conductive layer REL and the intermediate insulating layer MIN. The interlayer insulating layer ILD can be disposed throughout the first to third sub-pixel areas SPA1 to SPA3. The interlayer insulating layer ILD can cover at least a portion of the reflective conductive layer REL. The interlayer insulating layer ILD can be disposed between the reflective conductive layer REL and the light emitting element LD.

[0117] The interlayer insulating layer ILD can be a structure for forming a resonance structure. For example, in each of the sub-pixel areas SPA, a distance between an upper surface of the reflective conductive layer REL and the cathode electrode CE can be understood as a resonance distance of each sub-pixel SP. The interlayer insulating layer ILD can have a different thickness for each sub-pixel SP under the emission structure EMS. According to one or more embodiments, the interlayer insulating layer ILD can have a different thickness in each of the sub-pixel areas SPA. Thus, a different resonance distance can be defined for each sub-pixel SP. The resonance distance adjusted in this way can cause light in a specific wavelength range to be amplified effectively and efficiently.

[0118] According to one or more embodiments, a thickness of the interlayer insulating layer ILD in the first sub-pixel area SPA1 can be less than a thickness of the interlayer insulating layer ILD in the second sub-pixel area SPA2. The thickness of the interlayer insulating layer ILD in the second sub-pixel area SPA2 can be less than a thickness of the interlayer insulating layer ILD in the third sub-pixel area SPA3. However, the present disclosure is not limited thereto. The thickness relationship of the interlayer insulating layer ILD between the sub-pixel areas SPA can be appropriately or suitably changed.

[0119] The interlayer insulating layer ILD can include an inorganic material. For example, the interlayer insulating layer ILD can include one or more of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ). According to one or more embodiments, the interlayer insulating layer ILD can include an oxide such as silicon oxide (SiO x ). However, the present disclosure is not limited thereto.

[0120] According to one or more embodiments, the interlayer insulating layer ILD and the intermediate insulating layer MIN can include the same (or substantially the same) material. For example, the interlayer insulating layer ILD and the intermediate insulating layer MIN can include silicon oxide (SiO x ).

[0121] The light emitting element layer LEL can be disposed on the middle conductive structure layer MCL. The light emitting element layer LEL can include the first insulating layer IL1 and the second insulating layer IL2, the partition wall PW, the partition wall insulating layer PINS, the anode electrode AE, the emission structure EMS, the cathode electrode CE, and the encapsulation layer TFE.

[0122] The first insulating layer IL1 and the second insulating layer IL2 can be disposed on the interlayer insulating layer ILD between the sub-pixel areas SPA. The first insulating layer IL1 and the second insulating layer IL2 can be disposed under the partition wall PW.

[0123] The first insulating layer IL1 and the second insulating layer IL2 can include an inorganic material. The first insulating layer IL1 and the second insulating layer IL2 can include one or more of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ). However, the present disclosure is not limited to these specific examples.

[0124] According to one or more embodiments, the first insulating layer IL1 and the second insulating layer IL2 can not overlap the bonding conductive layer BO, the lower conductive layer LREL, or the reflective conductive layer REL in a plan view, and can overlap the partition wall PW.

[0125] The first insulating layer IL1 and the second insulating layer IL2 can include different materials and have different widths. For example, the first insulating layer IL1 can protrude with respect to the second insulating layer IL2 (e.g., can protrude in the first direction DR1 and / or the second direction DR2).

[0126] The partition wall PW can be disposed on the first insulating layer IL1 and the second insulating layer IL2 between the sub-pixel areas SPA.

[0127] The partition wall PW can separate the sub-pixels SP. For example, the partition wall PW can be disposed between adjacent emission structures EMS. For example, each of the first emission structure EMS1 to the third emission structure EMS3 can be disposed between adjacent partition walls PW.

[0128] According to one or more embodiments, the partition wall PW can physically separate the sub-pixels SP. Thus, the risk of color mixing between the sub-pixels SP can be reduced. In other words, in some embodiments, the first insulating layer IL1 and the second insulating layer IL2 do not overlap with the bonding conductive layer BO, the lower conductive layer LREL or the reflective conductive layer REL in a plan view, but the first insulating layer IL1 and the second insulating layer IL2 overlap with the partition wall PW. These insulating layers can be made of different materials and have different widths, and the first insulating layer IL1 protrudes much more than the second insulating layer IL2. The partition wall PW is positioned on these insulating layers between the sub-pixel areas SPA to separate the sub-pixels SP and protect the sub-pixels SP from color mixing, thereby improving the display quality.

[0129] The partition wall PW can be manufactured based on the base SBS for manufacturing the intermediate conductive structure layer MCL (see, for example, FIG. 1A). Figure 9 For example, the partition wall PW can include silicon (Si). However, the material of the partition wall PW is not limited thereto.

[0130] The partition wall insulating layer PINS can be arranged between the sub-pixel areas SPA. The partition wall insulating layer PINS can cover the side surface and the upper surface of the partition wall PW. A portion of the partition wall insulating layer PINS can face the emission structure EMS, and another portion of the partition wall insulating layer PINS can face the cathode electrode CE.

[0131] The partition wall insulating layer PINS can include one or more suitable inorganic materials. For example, the partition wall insulating layer PINS can include one or more of silicon oxide (SiO x ), silicon nitride (SiN x ), titanium oxide (TiO x , where 0 < x ≤ 2, for example, TiO2), and aluminum oxide (Al x O y ). However, the present disclosure is not limited thereto.

[0132] According to one or more embodiments, the partition wall insulating layer PINS can be formed on the partition wall PW arranged between the sub-pixel areas SPA. Thus, the risk of leakage current between adjacent sub-pixels SP can be further reduced. In other words, in some embodiments, the partition wall insulating layer PINS can be formed on the partition wall PW located between the sub-pixel areas SPA. This helps to further reduce the risk of leakage current between adjacent sub-pixels SP.

[0133] According to one or more embodiments, the partition wall insulating layer PINS and the first insulating layer IL1 can include the same (or substantially the same) material. In such embodiments, an etching process for manufacturing the partition wall insulating layer PINS and the first insulating layer IL1 can be performed concurrently (e.g., simultaneously).

[0134] The anode electrode AE can be disposed on the interlayer insulating layer ILD in the sub-pixel area SPA. The anode electrode AE can overlap the reflective conductive layer REL in a plan view. The anode electrode AE can be disposed between adjacent partition walls PW.

[0135] The anode electrode AE can include a first anode electrode AE1 included in the first sub-pixel SP1, a second anode electrode AE2 included in the second sub-pixel SP2, and a third anode electrode AE3 included in the third sub-pixel SP3.

[0136] The anode electrode AE can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO). However, the material of the anode electrode AE is not limited thereto. For example, the anode electrode AE can include titanium nitride.

[0137] The anode electrode AE can be electrically connected to the reflective conductive layer REL through a contact portion CNT that penetrates the interlayer insulating layer ILD. Accordingly, the anode electrode AE can receive an anode voltage from the pixel circuit PXC.

[0138] The emission structure EMS can emit light based on an electrical signal provided from the anode electrode AE and the cathode electrode CE. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE can be transported into a light-emitting layer EML of the emission structure EMS to form an exciton, and light can be generated when the exciton transitions from an excited state to a ground state. The brightness of the light can be determined according to the amount of current flowing through the light-emitting layer EML. According to the configuration of the light-emitting layer EML, the wavelength range of the generated light can be determined.

[0139] A first surface of the emission structure EMS can be electrically connected to the anode electrode AE, and a second surface of the emission structure EMS can be electrically connected to the cathode electrode CE.

[0140] The emission structure EMS can include a first emission structure EMS1 forming the first sub-pixel SP1 and disposed in the first sub-pixel area SPA1, a second emission structure EMS2 forming the second sub-pixel SP2 and disposed in the second sub-pixel area SPA2, and a third emission structure EMS3 forming the third sub-pixel SP3 and disposed in the third sub-pixel area SPA3.

[0141] The emission structure EMS can be disposed between the partition walls PW. The emission structure EMS can be adjacent to the partition walls PW in a planar direction along which the substrate SUB is disposed (e.g., in a plane substantially parallel to a plane in which the substrate SUB is disposed).

[0142] The emission structure EMS can include a multi-layer structure electrically connected between the anode electrode AE and the cathode electrode CE.

[0143] The emission structure EMS can include a light emitting unit EU including a plurality of layers. As shown in, for example, Figure 7 The light emitting unit EU can include a plurality of emission structures including a hole transport unit HTU, a light emitting layer (or a light generating layer) EML, and an electron transport unit ETU, as shown in, for example,

[0144] The hole transport unit HTU can include a multi-layer structure having a plurality of layers each including a different material. As an example, the hole transport unit HTU can include a hole injection layer HIL and a hole transport layer HTL, and according to one or more embodiments, can further include a light emitting auxiliary layer and / or an electron blocking layer, etc.

[0145] The light emitting layer EML can include a material capable of emitting light of one color. The light emitting layer EML can include a host and a dopant. The host of the light emitting layer EML can be a light emitting material that can trap carriers (electrons and holes) for generating light, and can induce efficient generation of excitons. The dopant can include a phosphorescent dopant or a fluorescent dopant. According to one or more embodiments, examples of the dopant are not particularly limited. According to one or more embodiments, the dopant can include an organic material or can include a metal complex, etc.

[0146] The electron transport unit ETU can include a multi-layer structure having a plurality of layers each including a different material. The electron transport unit ETU can include an electron injection layer EIL and an electron transport layer ETL, and according to one or more embodiments, can further include an electron buffer layer and / or a hole blocking layer, etc.

[0147] According to one or more embodiments (see, for example, Figure 7), the emission structure EMS can include a single light emitting unit EU. In such an embodiment, the emission structure EMS can include different materials in each sub-pixel SP. For example, the emission structure EMS can include a first emission structure EMS1 arranged in the first sub-pixel SP1 and including a material for emitting light of a first color, a second emission structure EMS2 arranged in the second sub-pixel SP2 and including a material for emitting light of a second color, and a third emission structure EMS3 arranged in the third sub-pixel SP3 and including a material for emitting light of a third color.

[0148] According to one or more embodiments (see, for example, Figure 8 ), the emission structure EMS can have a series structure. For example, the emission structure EMS can include a plurality of light emitting units EU and a charge generation layer CGL arranged between the plurality of light emitting units EU. The charge generation layer CGL can be arranged between the light emitting units EU to guide the flow of current. In one or more embodiments, the charge generation layer CGL can have a stacked structure of a p-dopant layer and an n-dopant layer. According to one or more embodiments, the light emitting units EU can include a first light emitting unit EU1 providing light of a first color, a second light emitting unit EU2 providing light of a second color, and a third light emitting unit EU3 providing light of a third color. The charge generation layer CGL can include a first charge generation layer CGL1 and a second charge generation layer CGL2. According to one or more embodiments, in the emission structure EMS, the first light emitting unit EU1, the first charge generation layer CGL1, the second light emitting unit EU2, the second charge generation layer CGL2, and the third light emitting unit EU3 can be sequentially arranged.

[0149] The cathode electrode CE can be arranged on the emission structure EMS. The cathode electrode CE can be arranged throughout the first to third sub-pixel areas SPA1 to SPA3 and can be commonly provided to the first to third sub-pixels SP1 to SP3. The cathode electrode CE can function as a half mirror that partially transmits and partially reflects light emitted from the emission structure EMS. However, the present disclosure is not limited thereto.

[0150] According to one or more embodiments, the cathode electrode CE can include at least one of silver (Ag), magnesium (Mg), and a mixture (e.g., any suitable) thereof. However, the material of the cathode electrode CE is not limited thereto. According to one or more embodiments, the cathode electrode CE can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO).

[0151] According to one or more embodiments, one of the first to third anode electrodes AE1 to AE3, one of the first to third emission structures EMS1 to EMS3, and a portion of the cathode electrode CE can be understood to constitute a light emitting element LD of each of the first to third sub-pixels SP1 to SP3.

[0152] As shown in FIG. 1, for example, a sealing layer TFE can be disposed on the cathode electrode CE and can be disposed throughout the first to third sub-pixel areas SPA1 to SPA3. The sealing layer TFE can include a plurality of insulating films covering the light emitting elements LD. According to one or more embodiments, the sealing layer TFE can include an inorganic layer and an organic layer. For example, the sealing layer TFE can have a structure in which a first inorganic layer / organic layer / second inorganic layer are sequentially disposed. However, the present disclosure is not limited thereto. According to one or more embodiments, the sealing layer TFE can be a thin film encapsulation film. Figure 6 A light functional layer LFL can be disposed on the sealing layer TFE. The light functional layer LFL can include a color filter CF and a lens LS.

[0153] The color filter CF can selectively transmit light of one color. For example, the color filter CF can include a first color filter CF1 disposed in the first sub-pixel area SPA1, a second color filter CF2 disposed in the second sub-pixel area SPA2, and a third color filter CF3 disposed in the third sub-pixel area SPA3.

[0154] The first color filter CF1 can include a dye and / or a pigment that selectively transmits light of a first color. The second color filter CF2 can include a dye and / or a pigment that selectively transmits light of a second color. The third color filter CF3 can include a dye and / or a pigment that selectively transmits light of a third color.

[0155] The lens LS can be disposed on the color filter CF. For example, the lens LS can include a first lens LS1 superimposed with the first sub-pixel area SPA1, a second lens LS2 superimposed with the second sub-pixel area SPA2, and a third lens LS3 superimposed with the third sub-pixel area SPA3.

[0156] The lens LS can improve light output efficiency by outputting light emitted from the emission structure EMS through an intended path. The lens LS can include an acrylic material. However, the material of the lens LS is not limited thereto.

[0157] According to one or more embodiments, the display device 100 can further include additional layers in addition to the above-described layers. For example, the display device 100 can further include a cover window or the like.

[0158] Reference will now be made to

[0159] Figures 9 to 22 ​A method of manufacturing the display device 100 according to one or more embodiments will be described. The following can briefly describe or not repeat what can be repeated with the above (e.g., quantities).

[0160] Figures 9 to 22 Each is a cross-sectional view schematically illustrating a process step (e.g., a task or an action) of a method of manufacturing a display device according to one or more embodiments of the disclosure. For ease of description, Figures 9 to 22 Each illustrates a cross-section based on the cross-sectional structure described above with reference to Figure 6

[0161] According to one or more embodiments, the display device 100 can be manufactured by providing a bonding assembly BAS including the intermediate conductive structure layer MCL (see, e.g., FIG. 1A), Figure 15 , providing a semiconductor wafer WAF, bonding the bonding assembly BAS and the semiconductor wafer WAF, and disposing the light-emitting element layer LEL and the light function layer LFL on the bonding assembly BAS.

[0162] According to one or more embodiments, a first process of providing the bonding assembly BAS and a second process of manufacturing the semiconductor wafer WAF can be performed separately. For example, the second process can be performed after the first process is performed, the first process can be performed after the second process is performed, or the first process and the second process can be performed in parallel and concurrently (e.g., simultaneously). Thus, process convenience can be improved and process steps can be simplified.

[0163] According to one or more embodiments, the conductive layer or the insulating layer on the base SBS and the substrate SUB can be formed based on a common process for manufacturing semiconductor devices. For example, the conductive layer or the insulating layer on the base SBS and the substrate SUB can be formed by a photolithography process, can be etched by one or more suitable methods (wet etching and / or dry etching, etc.), and can be deposited by one or more suitable methods (sputtering and / or chemical vapor deposition method, etc.). The disclosure is not necessarily limited thereto.

[0164] First, a method of manufacturing a bonding assembly BAS including an intermediate conductive structure layer MCL will be described with reference to Figures 9 to 15

[0165] With reference to Figure 9 , a first base insulating layer IL1_B, a second base insulating layer IL2_B, and a base interlayer insulating layer ILD_B can be formed on the base SBS.

[0166] ​​According to one or more embodiments, the substrate SBS can be a base for manufacturing the intermediate conductive structure layer MCL. According to one or more embodiments, the substrate SBS can include a silicon resin material. The substrate SBS can be a base for manufacturing the intermediate conductive structure layer MCL, and the partition wall PW can be manufactured by patterning the substrate SBS in a subsequent process. Accordingly, the additional process can be reduced, and the process cost can be reduced.

[0167] Referring to Figure 10 At least part of the substrate interlayer insulation layer ILD_B can be removed (e.g., etched), and the interlayer insulation layer ILD can be manufactured.

[0168] In this step (e.g., action or task), the substrate interlayer insulation layer ILD_B can be patterned so that the interlayer insulation layer ILD has different thicknesses in the plurality of sub-pixel areas SPA. Accordingly, the interlayer insulation layer ILD can have different thicknesses in the plurality of sub-pixel areas SPA to form a resonance structure.

[0169] Referring to Figure 11 The substrate reflective conductive layer REL_B can be formed (e.g., deposited) on the interlayer insulation layer ILD.

[0170] In this step (e.g., action or task), the substrate reflective conductive layer REL_B can be formed throughout the sub-pixel area SPA. The substrate reflective conductive layer REL_B can be formed to have a substantially uniform thickness throughout the area on the substrate SBS.

[0171] Referring to Figure 12 At least part of the substrate reflective conductive layer REL_B can be removed (e.g., etched) to provide the first to third reflective conductive layers REL1 to REL3. The substrate lower conductive layer LREL_B can be formed to cover part of the interlayer insulation layer ILD and the first to third reflective conductive layers REL1 to REL3.

[0172] In this step (e.g., action or task), the first to third reflective conductive layers REL1 to REL3 can be patterned to have a substantially uniform thickness.

[0173] According to one or more embodiments, in the display device 100, the first to third reflective conductive layers REL1-3 that are formed below the resonant structure to form the light recycling structure can be patterned after a step difference for forming the resonant structure is formed in the interlayer insulating layer ILD. In other words, the first to third reflective conductive layers REL1-3 reflect light back toward the emission structure EMS through the interlayer insulating layer ILD above the first to third reflective conductive layers REL1-3. The first to third reflective conductive layers REL1-3 can be patterned after the interlayer insulating layer ILD is formed. The interlayer insulating layer ILD has different thicknesses at different subpixels SP, such that it forms a resonant structure for light (e.g., light of a particular color) for each subpixel, resulting in constructive interference that improves light output.

[0174] According to one or more embodiments, the interlayer insulating layer ILD can include an oxide material. For example, because the interlayer insulating layer ILD including an oxide material is formed before the first to third reflective conductive layers REL1-3 are formed, the risk of forming an oxide film on the first to third reflective conductive layers REL1-3 can be reduced. If an unintended structure such as an oxide film is formed in a portion of a path through which an anode voltage is supplied, there can be a risk of anode voltage information distortion. However, according to one or more embodiments, because the first to third reflective conductive layers REL1-3 are patterned after the interlayer insulating layer ILD is formed, as described above, the above-described risk can be reduced. In other words, in some embodiments, the interlayer insulating layer ILD can include an oxide material. Forming this layer before the first to third reflective conductive layers REL1-3 are formed helps reduce the risk of forming an oxide film on these layers. Because the reflective conductive layers REL are patterned after the interlayer insulating layer ILD is formed, this minimizes or reduces the opportunity for anode voltage distortion due to unintended structures such as oxide films.

[0175] Referring to Figure 13 A photoresist layer PR can be formed, and the first to third bonding conductive layers BO1-3 can be formed based on the photoresist layer PR.

[0176] In this step (e.g., action or task), the photoresist layer PR can be formed between the subpixel areas SPA. According to one or more embodiments, if (e.g., when) this step (e.g., action or task) is performed, the first to third bonding conductive layers BO1-3 can have a substantially uniform thickness.

[0177] In this step (e.g., action or task), the first to third bonding conductive layers BO1 to BO3 can be formed based on an electroplating method according to one or more embodiments. However, the present disclosure is not limited thereto.

[0178] Referring to Figure 14 The photoresist layer PR can be removed based on a lift-off process or the like, and at least a portion of the substrate lower conductive layer LREL_B can be removed (e.g., etched) to form the first to third lower conductive layers LREL1 to LREL3.

[0179] Referring to Figure 15 The intermediate insulating layer MIN can be arranged in the region between the sub-pixel areas SPA.

[0180] In this step (e.g., action or task), an insulating layer for planarization can be formed to fill the region between the sub-pixel areas SPA, and the insulating layer for planarization and the first to third bonding conductive layers BO1 to BO3 can be planarized. The intermediate insulating layer MIN can be provided by removing at least a portion of the insulating layer for planarization. Thus, the first to third bonding conductive layers BO1 to BO3 and the intermediate insulating layer MIN can form a planar surface that substantially coincides with each other.

[0181] In this step (e.g., action or task), the first to third bonding conductive layers BO1 to BO3 can have different thicknesses as the planarization process is performed. Thus, the bonding assembly BAS including the intermediate conductive structure layer MCL can be provided.

[0182] Referring to Figure 15 vertically inverted Figure 16 The semiconductor wafer WAF including the substrate SUB and the pixel circuit PXC can be provided, and the manufactured bonding assembly BAS can be arranged on the semiconductor wafer WAF (see, e.g., Figure 15 ).

[0183] In this step (e.g., action or task), the bonding assembly BAS can be arranged on the semiconductor wafer WAF such that the first to third bonding conductive layers BO1 to BO3 face the semiconductor wafer WAF. In this step (e.g., action or task), the semiconductor wafer WAF and the intermediate conductive structure layer MCL can be bonded using the first to third bonding conductive layers BO1 to BO3. According to one or more embodiments, the bonding conductive layers BO and the semiconductor wafer WAF can be bonded to each other by solder bonding or Cu-Cu hybrid bonding as described above.

[0184] According to one or more embodiments, because the first bonding conductive layer BO1 to the third bonding conductive layer BO3 and the upper surface of the intermediate insulating layer MIN form a substantially flat surface, the bonding assembly BAS can be appropriately or suitably disposed on the semiconductor wafer WAF. Therefore, the first reflective conductive layer REL1 to the third reflective conductive layer REL3 and the interlayer insulating layer ILD for forming a resonant structure can be formed on the semiconductor wafer WAF.

[0185] In this step (e.g., an action or a task), the first bonding conductive layer BO1 to the third bonding conductive layer BO3 can be electrically connected to the first pixel circuit PXC1 to the third pixel circuit PXC3.

[0186] Referring to Figure 17 At least a portion of the base substrate SBS can be removed, and a partition wall base substrate SBS_G having a reduced thickness can be provided.

[0187] In this step (e.g., an action or a task), at least a portion of the base substrate SBS can be removed so that the base substrate SBS has a thickness of the partition wall PW to be manufactured. Therefore, a separate process for forming the partition wall PW can not be further performed, and the thickness of the partition wall PW can be appropriately or suitably defined.

[0188] In this step (e.g., an action or a task), a backgrinding process for the base substrate SBS can be performed. However, the disclosure is not limited thereto. A polishing process or the like can be performed on the base substrate SBS.

[0189] Referring to Figure 18 The partition wall PW can be formed by removing at least a portion of the partition wall base substrate SBS_G, and a partition wall base insulating layer PINS_B can be formed.

[0190] In this step (e.g., an action or a task), at least a portion of the partition wall base substrate SBS_G can be etched, and the partition wall PW exposing the first base insulating layer IL1_B can be formed. Therefore, the partition wall PW can be formed between the sub-pixel areas SPA.

[0191] In this step (e.g., an action or a task), the partition wall base insulating layer PINS_B can be deposited to cover the sub-pixel areas SPA, and the partition wall PW and the first base insulating layer IL1_B can be covered by the partition wall base insulating layer PINS_B.

[0192] Referring to Figure 19 At least a portion of the partition wall base insulating layer PINS_B and the first base insulating layer IL1_B can be removed (e.g., etched), and the first insulating layer IL1 and the partition wall insulating layer PINS not disposed in the sub-pixel areas SPA can be formed.

[0193] In this step (e.g., action or task), as at least part of the separation wall base insulating layer PINS_B and the first base insulating layer IL1_B is removed, the second base insulating layer IL2_B can be exposed. According to one or more embodiments, the separation wall base insulating layer PINS_B and the first base insulating layer IL1_B can include the same (or substantially the same) material, and can be etched concurrently (e.g., simultaneously).

[0194] Referring to Figure 20 At least part of the second base insulating layer IL2_B can be removed (e.g., etched), and the second insulating layer IL2 can be formed.

[0195] In this step (e.g., action or task), as at least part of the second base insulating layer IL2_B is removed, the interlayer insulating layer ILD can be exposed. According to one or more embodiments, the second base insulating layer IL2_B and the interlayer insulating layer ILD can include different (substantially different) materials, and an etching process for the second base insulating layer IL2_B can be performed until the interlayer insulating layer ILD is exposed.

[0196] According to one or more embodiments, the first insulating layer IL1 and the second insulating layer IL2 can include different materials. Accordingly, as the etching process is performed, the first insulating layer IL1 and the second insulating layer IL2 can be patterned to have different widths.

[0197] Referring to Figure 21 The anode electrode AE can be formed on the interlayer insulating layer ILD, the emission structure EMS can be disposed and / or arranged on the anode electrode AE, and the cathode electrode CE can be formed to cover the emission structure EMS. In addition, the encapsulation layer TFE can be formed on the cathode electrode CE.

[0198] In this step (e.g., action or task), the contact portion CNT that penetrates the interlayer insulating layer ILD and exposes the reflective conductive layer REL can be formed, and the anode electrode AE can be formed. Accordingly, the first to third anode electrodes AE1 to AE3 can be electrically connected to the first to third reflective conductive layers REL1 to REL3, respectively, through the contact portion CNT.

[0199] In this step (e.g., action or task), the emission structure EMS can be formed by one or more suitable methods. For example, the emission structure EMS can be disposed and / or arranged by one or more suitable processes, such as deposition and coating. However, the present disclosure is not limited thereto.

[0200] In this step (e.g., action or task), the emission structure EMS can be provided and / or arranged between the partition walls PW. According to one or more embodiments, the emission structure EMS for each sub-pixel SP can be separated by the partition walls PW. Thus, the risk of a leakage current between adjacent sub-pixels SP can be reduced.

[0201] In this step (e.g., action or task), the cathode electrode CE can be provided and / or arranged throughout the first sub-pixel area SPA1 to the third sub-pixel area SPA3. Thus, the cathode electrode CE can form a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0202] In this step (e.g., action or task), the encapsulation layer TFE can be formed on the cathode electrode CE, and a plurality of layers forming the encapsulation layer TFE can be sequentially provided and / or arranged.

[0203] Referring to Figure 22 The light functional layer LFL can be provided and / or arranged on the encapsulation layer TFE.

[0204] In this step (e.g., action or task), the first color filter CF1 to the third color filter CF3 can be formed to overlap the first sub-pixel area SPA1 to the third sub-pixel area SPA3, and the first lens LS1 to the third lens LS3 can be formed to overlap the first sub-pixel area SPA1 to the third sub-pixel area SPA3.

[0205] Thereafter, according to one or more embodiments, an additional component such as a cover window can be further formed on the lens LS, and the display apparatus 100 according to one or more embodiments can be provided.

[0206] Figure 23 is a block diagram illustrating a display system according to one or more embodiments of the disclosure.

[0207] Referring to Figure 23 , the display system 1000 can include a processor 1100 and one or more display apparatuses 1210 and 1220.

[0208] The processor 1100 can perform one or more suitable tasks and calculations. In one or more embodiments, the processor 1100 can include an application processor, a graphic processor, a microprocessor, and / or a central processing unit (CPU), etc. The processor 1100 can be connected to and control other components of the display system 1000 through a bus system.

[0209] In Figure 23In the middle, the display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1 and to the second display device 1220 through a second channel CH2.

[0210] Through the first channel CH1, the processor 1100 can transmit first image data IMG1 and first control signals CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signals CTRL1. The first display device 1210 can be configured similarly to the display device 100 described with reference to Figure 1

[0211] Through the second channel CH2, the processor 1100 can transmit second image data IMG2 and second control signals CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signals CTRL2. The second display device 1220 can be configured similarly to the display device 100 described with reference to Figure 1

[0212] The display system 1000 can include a computing system (such as a portable computer, a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a portable multimedia player (PMP), a navigation, and / or an ultra-mobile personal computer (UMPC)) that provides an image (and / or video) display function. In addition, the display system 1000 can include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0213] Figure 24 is a perspective view of a head-mounted display device showing an example of an application of a display system according to one or more embodiments of the present disclosure. Figure 23

[0214] Referring to Figure 24 , Figure 23 The display system 1000 of

[0215] ​​​The head-mounted display device 2000 can include a head-mounted band 2100 and a display device storage case 2200. The head-mounted band 2100 can be connected to the display device storage case 2200. The head-mounted band 2100 can include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the head of a user. The horizontal band can be configured to go around (e.g., surround) the sides of the head of the user, and the vertical band can be configured to go around (e.g., surround) the top of the head of the user. However, the present disclosure is not limited thereto. For example, the head-mounted band 2100 can be implemented in the form of a glasses frame and / or a helmet, etc.

[0216] The display device storage case 2200 can accommodate the first display device 1210 and the second display device 1220 of Figure 23 The display device storage case 2200 can further accommodate the processor 1100 of Figure 23

[0217] Figure 25 is a diagram illustrating a head-mounted display device worn by a user according to one or more embodiments of the present disclosure. Figure 24

[0218] Referring to Figure 25 , within the head-mounted display device 2000, a first display panel DP1 of the first display device 1210 and a second display panel DP2 of the second display device 1220 can be disposed. The head-mounted display device 2000 can further include one or more lenses LLNS and RLNS.

[0219] Within the display device storage case 2200, the right-eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user. Within the display device storage case 2200, the left-eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user.

[0220] An image output from the first display panel DP1 can be displayed to the right eye of the user through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 to be directed toward the right eye of the user. The right-eye lens RLNS can perform an optical function to adjust a viewing distance between the first display panel DP1 and the right eye of the user.

[0221] An image output from the second display panel DP2 can be displayed to the left eye of the user through the left-eye lens LLNS. The left-eye lens LLNS can refract light from the second display panel DP2 to be directed toward the left eye of the user. The left-eye lens LLNS can perform an optical function to adjust a viewing distance between the second display panel DP2 and the left eye of the user.

[0222] ​​In one or more embodiments, each of the right eye lens RLNS and the left eye lens LLNS can include an optical lens having a pancake-shaped (e.g., convex) profile. In one or more embodiments, each of the right eye lens RLNS and the left eye lens LLNS can include a multi-channel lens including sub-regions having different optical properties. In such embodiments, each display panel can output an image corresponding to a sub-region of the multi-channel lens, and the output image can pass through the corresponding sub-region and can be displayed to the user.

[0223] According to aspects of one or more embodiments of the present disclosure, a display device that can improve reliability of an electrical signal provided to the display device and a method of manufacturing the display device can be provided.

[0224] Aspects of embodiments of the present disclosure relate to a display device that can reduce risks in a manufacturing process and a method of manufacturing the display device.

[0225] Aspects of embodiments of the present disclosure relate to a display device having excellent or suitable display quality and a method of manufacturing the display device.

[0226] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0227] Also, in describing embodiments of the present disclosure, the use of “may” indicates “one or more embodiments of the present disclosure.”

[0228] As used herein, the terms “substantially,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, “substantially” includes the recited value and means that considering the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system), the value is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “substantially” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0229] Also, any numerical ranges recited herein are intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of 1.0 to 10.0 is intended to include all sub-ranges, both including and

[0230] The display device, processing device, electronic device, apparatus or method for manufacturing a display device, or any other related device or component according to embodiments of the disclosure described herein can be implemented utilizing any suitable hardware, firmware (e.g., application specific integrated circuit), software, or combination of software, firmware, and hardware. For example, various components of the device can be formed on one integrated circuit (IC) chip or on separate IC chips. Also, various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, various components of the device can be processes or threads running on one or more processors in one or more computing devices and executing computer program instructions and interacting with other system components for performing various functions described herein. The computer program instructions are stored in a memory that can be implemented in the computing device using a standard memory device, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, a flash drive, etc. Also, those skilled in the art will appreciate that functions of various computing devices can be combined or integrated into a single computing device, or functions of a particular computing device can be distributed across one or more other computing devices, without departing from the scope of embodiments of the disclosure.

[0231] In view of the overall disclosure, those of ordinary skill in the art will appreciate that each suitable feature of various embodiments of the disclosure can be combined, in part or in whole, with each other, and can be interlocked and operated in various suitable manners in technology, and unless otherwise stated or implied, each embodiment can be implemented independently of each other, or in combination with each other in any suitable manner.

[0232] It will be understood that the description of features or aspects of each embodiment is generally applicable to other similar features or aspects of other embodiments unless specifically described otherwise. Thus, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in connection with a particular embodiment can be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically noted otherwise. It will be understood that the foregoing is a description of various example embodiments and that the disclosure is not to be interpreted in a limiting sense. Various modifications to the disclosed embodiments and other example embodiments will be apparent to persons of ordinary skill in the art, and are intended to be included.

Claims

1. A display device, characterized by comprising: The display device includes a pixel including a sub-pixel region, the sub-pixel region including a first sub-pixel region and a second sub-pixel region, The display device includes: a semiconductor wafer including a substrate; a bonding conductive layer on the semiconductor wafer; a reflective conductive layer on the bonding conductive layer; and a light emitting element electrically connected to the reflective conductive layer, wherein the bonding conductive layer includes a first bonding conductive layer in the first sub-pixel region and a second bonding conductive layer in the second sub-pixel region, and wherein the first bonding conductive layer and the second bonding conductive layer have different thicknesses.

2. The display device of claim 1, wherein, The display device further includes: an interlayer insulating layer covering the reflective conductive layer and between the reflective conductive layer and the light emitting element, wherein the interlayer insulating layer has different thicknesses in the sub-pixel regions.

3. The display device of claim 2, wherein, The display device further includes: a partition wall on the interlayer insulating layer between the sub-pixel regions.

4. The display device of claim 3, wherein, The display device further includes: a partition wall insulating layer on the partition wall, wherein the partition wall is composed of silicon.

5. The display device of claim 4, wherein, The bonding conductive layer is composed of copper, wherein the reflective conductive layer is composed of one of aluminum, silver, magnesium, platinum, palladium, gold, nickel, neodymium, iridium, chromium, titanium, and wherein the partition wall insulating layer is composed of one of silicon oxide, silicon nitride, titanium oxide, and aluminum oxide.

6. The display device of claim 4, wherein, The display device further includes: first and second insulating layers between the partition wall and the interlayer insulating layer and having different widths.

7. The display device of claim 1, wherein The semiconductor wafer includes a pixel circuit on the substrate, wherein the bonding conductive layer is electrically connected to the pixel circuit, and wherein the bonding conductive layer and the semiconductor wafer are in direct contact with each other.

8. The display device of claim 1, wherein, The bonding conductive layer and the semiconductor wafer are bonded to each other by solder bonding or Cu-Cu hybrid bonding.

9. The display device of claim 1, wherein The display device further includes: a lower conductive layer between the bonding conductive layer and the reflective conductive layer, wherein the reflective conductive layer includes a first reflective conductive layer in the first sub-pixel region and a second reflective conductive layer in the second sub-pixel region, and wherein the first reflective conductive layer and the second reflective conductive layer have the same thickness.

10. The display device of claim 1, wherein The semiconductor wafer is a CMOS wafer.

11. The display device of claim 1, wherein The display device further includes: an encapsulation layer on the light emitting element; a color filter on the encapsulation layer; and a lens on the color filter, wherein the display device is an OLEDoS display device.

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