Electronic load ripple acquisition test module based on peak sampling

Abstract

The utility model discloses an electronic load ripple acquisition test module based on peak value sampling, and the module is characterized in that a blocking circuit is connected with the output end of a tested power supply, and an AC signal is obtained; the zero calibration circuit is connected with two output ends of the blocking circuit; the first amplification circuit is connected with the output end of the zero calibration circuit and used for extracting a positive half cycle signal of an alternating current signal, the output of the first amplification circuit is connected with the first peak value extraction circuit, and the output of the first peak value extraction circuit is connected with the input end of an ADC1 in the main DSP controller; the second amplification circuit is connected with the output end of the zero calibration circuit and used for extracting a negative half-cycle signal of the alternating current signal, the output of the second amplification circuit is connected with the second peak value extraction circuit, and the output of the second peak value extraction circuit is connected with the input end of an ADC2 in the main DSP controller; and the main DSP controller is connected with the electronic load module.

Description

TECHNICAL FIELD

[0001] The utility model relates to power electronics technical field especially relates to a kind of electronic load ripple collection test module based on peak sampling. BACKGROUND

[0002] At present, the test of power supply ripple is mainly realized by oscilloscope, and it is a component of power output characteristics. In the test of power output characteristics, electronic load is an indispensable device. If the ripple test function is added to the electronic load device, the oscilloscope device can be discarded, the cost and volume of the test equipment can be reduced, the connection of the equipment can be simplified, and the test efficiency can be greatly improved.

[0003] Another difficulty of oscilloscope test ripple is the interference of time base selection and trigger technology. The operation of oscilloscope needs to manually adjust the time base size to cope with different ripple frequencies. The ripple frequency usually includes three wave bands: the first is the power frequency ripple of low frequency band, the second is the switching ripple of medium frequency band, and the third is the switching pulse of high frequency band. It is difficult for oscilloscope to simultaneously present the information of the above three frequency bands.

[0004] Another difficulty of oscilloscope test ripple is the occasional ripple. Oscilloscope can directly present regular periodic signals. When the ripple presents occasional state, it usually needs to use the trigger function of oscilloscope to capture the occasional ripple with artificial intervention trigger technology. However, this trigger capture usually cannot meet the needs of automatic test. UTILITY MODEL CONTENT

[0005] Technical purpose: In view of the defects in the prior art, the utility model discloses an electronic load ripple collection test module based on peak sampling, which realizes ripple collection.

[0006] Technical scheme: In order to achieve the above technical purpose, the utility model adopts the following technical scheme.

[0007] An electronic load ripple collection test module based on peak sampling includes a direct-current isolation circuit, a zero calibration circuit, a first amplification circuit, a first peak extraction circuit, a second amplification circuit, a second peak extraction circuit, a main DSP controller, and an electronic load module.

[0008] The direct-current isolation circuit is connected with the output end of the measured power supply, and is used for isolating the direct-current output of the measured power supply to obtain an alternating-current signal. The zero calibration circuit is connected with the two output ends of the direct-current isolation circuit. The first input end of the zero calibration circuit is connected with the main DSP controller, and the two output ends of the zero calibration circuit are connected with the first amplification circuit and the second amplification circuit, respectively.

[0009] The output end of the first amplification circuit is connected with the output end of the zero calibration circuit, and is used for extracting the positive half cycle signal of the alternating current signal; the output of the first amplification circuit is connected with the first peak value extraction circuit, and is used for extracting the peak value signal of the alternating current signal; the output of the first peak value extraction circuit is connected with the input end of ADC1 in the main DSP controller, and ADC1 performs analog-digital conversion on the peak value of the alternating current signal; and the conversion result is read by the main DSP controller.

[0010] The output end of the second amplification circuit is connected with the output end of the zero calibration circuit, and is used for extracting the negative half cycle signal of the alternating current signal; the output of the second amplification circuit is connected with the second peak value extraction circuit, and is used for extracting the valley value signal of the alternating current signal; the output of the second peak value extraction circuit is connected with the input end of ADC2 in the main DSP controller, and ADC2 performs analog-digital conversion on the valley value of the alternating current signal; and the conversion result is read by the main DSP controller; and the main DSP controller is connected with the electronic load module.

[0011] Preferably, the direct current isolation circuit comprises a capacitor C1, a capacitor C2 and a resistor R1; one end of the capacitor C1 is used as a first input end of the direct current isolation circuit, and is used for connecting the positive output end of the measured power supply; the other end of the capacitor C1 is connected with one end of the resistor R1, and is used as a first output end of the direct current isolation circuit; one end of the capacitor C2 is used as a second input end of the direct current isolation circuit, and is used for connecting the negative output end of the measured power supply; the other end of the capacitor C2 is connected with the other end of the resistor R1, and is used as a second output end of the direct current isolation circuit.

[0012] Preferably, the zero calibration circuit comprises a relay S1, a transistor Q1 and a diode D1; the pin 1 of the relay S1 is connected with the first output end of the direct current isolation circuit; the pin 8 of the relay S1 is connected with the second output end of the direct current isolation circuit; the pin 4 of the relay S1 is connected with the collector of the transistor Q1; the collector of the transistor Q1 is connected with the positive end of the diode D1; the emitter of the transistor Q1 is grounded; the base of the transistor Q1 is used as a first input end of the zero calibration circuit, and is connected with the CLR signal end of the main DSP controller; the pin of the relay S1 is connected with the positive end of the diode D1; the negative end of the diode D1 is connected with the pin 5 of the relay S1; the pin 2 of the relay S1 is used as a first output end of the zero calibration circuit; and the pin 7 of the relay S1 is used as a second output end of the zero calibration circuit.

[0013] Preferably, the first amplification circuit comprises resistors R2, R3, R4, R5 and an amplification chip U1A, one end of the resistor R2 is connected to the positive terminal of the amplification chip U1A, the other end of the resistor R2 is connected to the first output terminal of the zero calibration circuit; one end of the resistor R3 is connected to the negative terminal of the amplification chip U1A, the other end of the resistor R3 is connected to the second output terminal of the zero calibration circuit; the positive terminal of the amplification chip U1A is grounded through the resistor R4, the negative terminal of the amplification chip U1A is connected to the output terminal of the amplification chip U1A through the resistor R5, and the output terminal of the amplification chip U1A serves as the output terminal of the first amplification circuit and is used to extract the positive half cycle signal of the alternating current signal.

[0014] Preferably, the second amplification circuit comprises resistors R6, R7, R8, R9 and an amplification chip U1B, one end of the resistor R6 is connected to the positive terminal of the amplification chip U1B, the other end of the resistor R6 is connected to the first output terminal of the zero calibration circuit; one end of the resistor R7 is connected to the negative terminal of the amplification chip U1B, the other end of the resistor R7 is connected to the second output terminal of the zero calibration circuit; the positive terminal of the amplification chip U1B is grounded through the resistor R8, the negative terminal of the amplification chip U1B is connected to the output terminal of the amplification chip U1B through the resistor R9, and the output terminal of the amplification chip U1B serves as the output terminal of the second amplification circuit and is used to extract the negative half cycle signal of the alternating current signal.

[0015] Preferably, the first peak extraction circuit and the second peak extraction circuit have the same structure.

[0016] Preferably, the first peak extraction circuit comprises operational amplifier chips U2A, U2B, a transistor Q2 and a rectifier diode D2; pin 3 of the operational amplifier chip U2A serves as the input terminal of the first peak extraction circuit and is connected to the output terminal of the first amplification circuit, used to receive the positive half cycle signal of the alternating current signal, i.e. the V_AC signal; pin 2 of the operational amplifier chip U2A is connected to pin 7 of the operational amplifier chip U2B through the resistor R13, pin 1 of the operational amplifier chip U2A is connected to the positive terminal of the rectifier diode D2 through the resistor R10, the negative terminal of the rectifier diode is connected to pin 5 of the operational amplifier chip U2B, the negative terminal of the rectifier diode D2 is connected to the collector of the transistor Q2, the base of the transistor Q2 is connected to the RST signal, i.e. the RST signal output by the main DSP controller, the emitter of the transistor Q2 is grounded, pin 5 of the operational amplifier chip U2B is grounded through the capacitor C3, pin 6 of the operational amplifier chip U2B is connected to pin 7 of the operational amplifier chip U2B through the resistor R11, pin 7 of the operational amplifier chip U2B is grounded through the resistor R12 and the capacitor C4, and pin 7 of the operational amplifier chip U2B outputs the V_PK signal through the resistor R12, which serves as the output signal of the first peak extraction circuit and is connected to the input terminal of the ADC1 in the main DSP controller.

[0017] Beneficial effects: the utility model discloses a direct current separation circuit, zero calibration circuit, first amplifier circuit, first peak extraction circuit, second amplifier circuit, second peak extraction circuit, main DSP controller realizes ripple collection process, and high -frequency switching pulse, medium -frequency switching ripple, low -frequency power frequency ripple are all converted into the peak signal of the nearly direct current, and then do not need like oscilloscope measurement as artificial adjustment time size, and then greatly save the test time, provide the more optimal automation test option. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is total structure schematic diagram of the utility model;

[0019] Figure 2 It is peak extraction circuit structure schematic diagram of the utility model;

[0020] Figure 3 It is ripple definition schematic diagram of the utility model. DETAILED DESCRIPTION

[0021] The utility model is further explained and described below in combination with the drawings and embodiments.

[0022] As attached Figure 1 The electronic load ripple collection test module based on peak sampling of the embodiment includes: direct current separation circuit, zero calibration circuit, first amplifier circuit, first peak extraction circuit, second amplifier circuit, second peak extraction circuit, main DSP controller and electronic load module.

[0023] The direct current separation circuit is connected with the output end of the measured power supply and is used for isolating the direct current output of the measured power supply and extracting pure alternating current signal.

[0024] The direct current separation circuit includes capacitor C1, capacitor C2 and resistor R1, one end of the capacitor C1 is used as the first input end of the direct current separation circuit and is connected with the output positive end of the measured power supply, the other end of the capacitor C1 is connected with one end of the resistor R1 and is used as the first output end of the direct current separation circuit, one end of the capacitor C2 is used as the second input end of the direct current separation circuit and is connected with the output negative end of the measured power supply, the other end of the capacitor C2 is connected with the other end of the resistor R1 and is used as the second output end of the direct current separation circuit.

[0025] Among them, the capacitor C1 and the capacitor C2 are direct current separation capacitors and are used for isolating direct current signal, the resistor R1 is used for reducing the output impedance of the direct current separation circuit to suppress the high frequency interference signal on the signal, the value of the resistor R1 should not be too small, and the resistor R1 is too small to reduce the flatness of the amplitude-frequency characteristic of the direct current separation circuit, the value of the resistor R1 should not be too large, and the resistor R1 is too large to weaken the suppression ability of the high frequency interference.

[0026] The two output ends of the zero calibration circuit are connected with the two output ends of the direct current isolation circuit, the first input end of the zero calibration circuit is connected with the main DSP controller, and the two output ends of the zero calibration circuit are connected with the first amplification circuit and the second amplification circuit respectively.

[0027] The zero calibration circuit comprises a relay S1, a transistor Q1 and a diode D1. The model of the relay S1 is G6K-2G, and the model of the transistor Q1 is MUN2232. The base of the transistor Q1 is connected with the main DSP controller as the first input end of the zero calibration circuit.

[0028] The pin 1 of the relay S1 is connected with the first output end of the direct current isolation circuit, i.e. the other end of the capacitor C1, the pin 8 of the relay S1 is connected with the second output end of the direct current isolation circuit, i.e. the other end of the capacitor C2, the pin 3 and the pin 6 of the relay S1 are grounded, the pin 4 of the relay S1 is connected with the collector of the transistor Q1, the collector of the transistor Q1 is connected with the positive end of the diode D1, the emitter of the transistor Q1 is grounded, the base of the transistor Q1 is connected with the main DSP controller as the first input end of the zero calibration circuit, specifically, the base of the transistor Q1 is connected with the CLR signal end of the main DSP controller, the pin of the relay S1 is connected with the positive end of the diode D1, the negative end of the diode D1 is connected with the pin 5 of the relay S1, and the pin 5 of the relay S1 is connected with a 12V voltage signal, the pin 2 of the relay S1 is the first output end of the zero calibration circuit, and the pin 7 of the relay S1 is the second output end of the zero calibration circuit.

[0029] The zero calibration circuit switches signals by controlling the level of the CLR signal of the main DSP controller. When the system is in the ripple measurement state, the zero calibration circuit transmits the output of the direct current isolation circuit. When the system is in the zero calibration mode, the two outputs of the zero calibration circuit are directly grounded to provide an absolute zero reference value for the system, so as to correct the zero deviation caused by the drift of the electrical parameters of the circuit and improve the reliability of the ripple measurement. The relay S1 is used for signal switching, the diode D1 is used for inhibiting the reverse excitation voltage in the switching process, and the digital transistor Q1 is used for converting the TTL level and the 12V level of the CLR signal to ensure the normal work of the relay.

[0030] The first amplification circuit is connected with the output end of the zero calibration circuit and is used for extracting the positive half cycle signal of the alternating current signal. The output of the first amplification circuit is connected with the first peak value extraction circuit and is used for extracting the peak value signal of the alternating current signal. The output of the first peak value extraction circuit is connected with the input end of ADC1 in the main DSP controller. ADC1 performs analog-digital conversion on the peak value of the alternating current signal, and the conversion result is read by the main DSP controller.

[0031] The first amplification circuit comprises resistors R2, R3, R4, R5 and an amplification chip U1A. The positive terminal of the amplification chip U1A is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with the first output terminal of the zero calibration circuit. The negative terminal of the amplification chip U1A is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the second output terminal of the zero calibration circuit. The positive terminal of the amplification chip U1A is grounded through the resistor R4, and the negative terminal of the amplification chip U1A is connected with the output terminal of the amplification chip U1A through the resistor R5. The output terminal of the amplification chip U1A serves as the output terminal of the first amplification circuit and is used for extracting the positive half cycle signal of the alternating current signal.

[0032] The first amplification circuit is a standard differential amplifier. The resistance and temperature characteristics of the resistors R2 and R3 are as consistent as possible. The resistance and temperature characteristics of the resistors R4 and R5 are as consistent as possible. Such consistency affects the ability of the first amplification circuit to suppress common-mode signal interference. The gain of the first amplifier is G1 = R4 / R2.

[0033] The second amplification circuit is connected with the output terminals of the zero calibration circuit and is used for extracting the negative half cycle signal of the alternating current signal. The output of the second amplification circuit is connected with the second peak value extraction circuit and is used for extracting the valley value signal of the alternating current signal. The output of the second peak value extraction circuit is connected with the input terminal of ADC2 in the main DSP controller. ADC2 performs analog-to-digital conversion on the valley value of the alternating current signal. The conversion result is read by the main DSP controller.

[0034] The second amplification circuit comprises resistors R6, R7, R8, R9 and an amplification chip U1B. The positive terminal of the amplification chip U1B is connected with one end of the resistor R6, and the other end of the resistor R6 is connected with the first output terminal of the zero calibration circuit. The negative terminal of the amplification chip U1B is connected with one end of the resistor R7, and the other end of the resistor R7 is connected with the second output terminal of the zero calibration circuit. The positive terminal of the amplification chip U1B is grounded through the resistor R8, and the negative terminal of the amplification chip U1B is connected with the output terminal of the amplification chip U1B through the resistor R9. The output terminal of the amplification chip U1B serves as the output terminal of the second amplification circuit and is used for extracting the negative half cycle signal of the alternating current signal.

[0035] The second amplification circuit is a standard differential amplifier. The resistance and temperature characteristics of the resistors R6 and R7 are as consistent as possible. The resistance and temperature characteristics of the resistors R8 and R9 are as consistent as possible. Such consistency affects the ability of the second amplification circuit to suppress common-mode signal interference. The gain of the second amplifier is G2 = -R8 / R6.

[0036] The operational amplifier chips U1A and U1B come from the same operational amplifier chip U1. U1 is a 5V-powered high-speed dual operational amplifier with the model number ADA4891.

[0037] As shown in the accompanying drawings Figure 2 and the accompanying drawings Figure 3 As shown in the accompanying drawings, the first peak extraction circuit and the second peak extraction circuit are the same structure, taking the first peak extraction circuit as an example, including operational amplifier chip U2A, operational amplifier chip U2B, transistor Q2, rectifier diode D2; the model of transistor Q2 is MUN2232; pin 3 of operational amplifier chip U2A is used as the input end of the first peak extraction circuit, connected with the output end of the first amplification circuit, used for receiving the positive half cycle signal of the alternating current signal, i.e. V_AC signal; pin 2 of operational amplifier chip U2A is connected with pin 7 of operational amplifier chip U2B through resistor R13, pin 1 of operational amplifier chip U2A is connected with the positive electrode end of rectifier diode D2 through resistor R10, the negative electrode end of the rectifier diode is connected with pin 5 of operational amplifier chip U2B, the negative electrode end of rectifier diode D2 is connected with the collector of transistor Q2, the base of transistor Q2 is connected with RST signal, i.e. RST signal output by the main DSP controller, the emitter of transistor Q2 is grounded, pin 5 of operational amplifier chip U2B is grounded through capacitor C3, pin 6 of operational amplifier chip U2B is connected with pin 7 of operational amplifier chip U2B through resistor R11, pin 7 of operational amplifier chip U2B is grounded through resistor R12 and capacitor C4, pin of operational amplifier chip U2B outputs V_PK signal through resistor R12, V_PK signal is used as the output signal of the first peak extraction circuit, connected with the input end of ADC1 in the main DSP controller. Operational amplifier chip U2A and operational amplifier chip U2B come from the same operational amplifier chip U2, U2 is a 5V power supply high-speed dual operational amplifier, the model is ADA4891; operational amplifier chip U2A works in the comparator state, capacitor C3 is a peak holding capacitor, rectifier diode D2 and capacitor C3 constitute a rectification filtering network, the voltage on capacitor C3 highly approximates the maximum value of the output level of operational amplifier chip U2A, operational amplifier chip U2B works in the emitter follower state, which transmits the voltage on capacitor C3 to the negative input end of operational amplifier chip U2A, i.e. pin 2 of operational amplifier chip U2A, to reduce the leakage current on capacitor C3 and maintain the stable work of the peak holding circuit. V_AC signal is input to the positive input end of operational amplifier chip U2A, pin 7 of operational amplifier chip U2B outputs Vp+ signal, Vp+ is fed back to the negative input end of operational amplifier chip U2B, when V_AC>Vp+, operational amplifier chip U2A charges capacitor C3, forcing Vp+ to rise, when V_AC<Vp+, because of the influence of rectifier diode D2, the voltage on capacitor C3 remains unchanged, finally, under the stable condition, Vp+ infinitely approximates the historical maximum value of V_AC, until the main DSP controller applies a positive pulse signal to RST signal, forcing transistor Q2 to discharge capacitor C3, and then resetting the peak Vp+ to zero.

[0038] The main DSP controller takes the analog-digital conversion result of ADC1 as the peak value of the alternating current signal, takes the analog-digital conversion result of ADC2 as the valley value of the alternating current signal, adds the peak value and the valley value to obtain the peak-to-peak value of the alternating current signal, and the peak-to-peak value is the measurement result of the voltage ripple. The main DSP controller controls the level of the RST signal to reset the first peak value extraction circuit and the second peak value extraction circuit. When the reset operation starts, the output of the peak value extraction circuit is zeroed, and a new peak value is automatically extracted. The reset frequency of the RST signal determines the length of the time window of the ripple measurement. The main DSP controller is connected with the electronic load module and transmits information through the CAN bus. The electronic load module sets the length of the time window of the ripple measurement and the working mode of the ripple measurement or zero calibration according to the external input of the man-machine interface or the upper computer software. The electronic load module transmits the above information to the main DSP controller. The main DSP controller controls the pin level of RST and CLR according to the above parameters and transmits the measured ripple result to the electronic load module to complete the ripple detection. The model of the main DSP controller is STM32F373. The adjustable window length of the utility model can ensure the effective measurement of the occasional ripple, and the test trigger capture function does not need to be artificially controlled like the oscilloscope measurement, thereby greatly saving the test time and providing a better automatic test option.

[0039] The utility model discloses a kind of based on peak value sampling electronic load ripple acquisition test module, including electronic load module, and electronic load is the necessary component of power output characteristic test, so it can save oscilloscope equipment, simplify equipment demand, reduce equipment cost.

[0040] The utility model discloses a kind of based on peak value sampling electronic load ripple acquisition test module, including electronic load module, and electronic load is the necessary component of power output characteristic test, so it can save oscilloscope equipment, simplify equipment demand, reduce equipment cost.

[0041] The above-mentioned is only preferred implementation mode of the utility model, it should be pointed out: for ordinary skilled person in the prior art, on the premise of not departing from the principle of the utility model, can make some improvements and refinements, these improvements and refinements also should be regarded as the protection range of the utility model.

Claims

1. An electronic load ripple acquisition test module based on peak sampling, characterized by: The application relates to a power supply testing device, which comprises a direct-current isolation circuit, a zero calibration circuit, a first amplification circuit, a first peak extraction circuit, a second amplification circuit, a second peak extraction circuit, a main DSP controller and an electronic load module. The direct-current isolation circuit is connected with the output end of the measured power supply and is used for isolating the direct-current output of the measured power supply to obtain an alternating-current signal; the zero calibration circuit is connected with the two output ends of the direct-current isolation circuit; the first input end of the zero calibration circuit is connected with the main DSP controller, and the two output ends of the zero calibration circuit are connected with the first amplification circuit and the second amplification circuit respectively. The first amplification circuit is connected with the output end of the zero calibration circuit and is used for extracting the positive half-cycle signal of the alternating-current signal; the output of the first amplification circuit is connected with the first peak extraction circuit and is used for extracting the peak signal of the alternating-current signal; the output of the first peak extraction circuit is connected with the input end of ADC1 in the main DSP controller, ADC1 carries out analog-digital conversion on the peak value of the alternating-current signal, and the conversion result is read by the main DSP controller; The second amplification circuit is connected with the output end of the zero calibration circuit and is used for extracting the negative half-cycle signal of the alternating-current signal; the output of the second amplification circuit is connected with the second peak extraction circuit and is used for extracting the valley signal of the alternating-current signal; the output of the second peak extraction circuit is connected with the input end of ADC2 in the main DSP controller, ADC2 carries out analog-digital conversion on the valley value of the alternating-current signal, and the conversion result is read by the main DSP controller; the main DSP controller is connected with the electronic load module.

2. The peak sample based electronic load ripple acquisition test module of claim 1, wherein: The direct-current isolation circuit comprises capacitors C1 and C2 and a resistor R1; one end of the capacitor C1 is used as the first input end of the direct-current isolation circuit and is used for connecting the positive output end of the measured power supply; the other end of the capacitor C1 is connected with one end of the resistor R1 and is used as the first output end of the direct-current isolation circuit; one end of the capacitor C2 is used as the second input end of the direct-current isolation circuit and is used for connecting the negative output end of the measured power supply; the other end of the capacitor C2 is connected with the other end of the resistor R1 and is used as the second output end of the direct-current isolation circuit.

3. The peak sample based electronic load ripple acquisition test module of claim 1, wherein: The zero calibration circuit comprises a relay S1, a transistor Q1 and a diode D1; the pin 1 of the relay S1 is connected with the first output end of the direct-current isolation circuit, the pin 8 of the relay S1 is connected with the second output end of the direct-current isolation circuit, the pin 4 of the relay S1 is connected with the collector of the transistor Q1, and the collector of the transistor Q1 is connected with the positive end of the diode D1; the emitter of the transistor Q1 is grounded, the base of the transistor Q1 is used as the first input end of the zero calibration circuit and is connected with the CLR signal end of the main DSP controller; the pin of the relay S1 is connected with the positive end of the diode D1, the negative end of the diode D1 is connected with the pin 5 of the relay S1, the pin 2 of the relay S1 is used as the first output end of the zero calibration circuit, and the pin 7 of the relay S1 is used as the second output end of the zero calibration circuit.

4. The peak sample based electronic load ripple acquisition test module of claim 1, wherein: The first amplification circuit comprises resistors R2, R3, R4, R5 and an amplification chip U1A, a positive terminal of the amplification chip U1A is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with the first output terminal of the zero calibration circuit; a negative terminal of the amplification chip U1A is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the second output terminal of the zero calibration circuit; the positive terminal of the amplification chip U1A is grounded through the resistor R4, the negative terminal of the amplification chip U1A is connected with the output terminal of the amplification chip U1A through the resistor R5, and the output terminal of the amplification chip U1A serves as the output terminal of the first amplification circuit and is used for extracting the positive half cycle signal of the alternating current signal.

5. The peak value sampling based electronic load ripple acquisition test module of claim 1, wherein: The second amplification circuit comprises resistors R6, R7, R8, R9 and an amplification chip U1B, a positive terminal of the amplification chip U1B is connected with one end of the resistor R6, and the other end of the resistor R6 is connected with the first output terminal of the zero calibration circuit; a negative terminal of the amplification chip U1B is connected with one end of the resistor R7, and the other end of the resistor R7 is connected with the second output terminal of the zero calibration circuit; the positive terminal of the amplification chip U1B is grounded through the resistor R8, the negative terminal of the amplification chip U1B is connected with the output terminal of the amplification chip U1B through the resistor R9, and the output terminal of the amplification chip U1B serves as the output terminal of the second amplification circuit and is used for extracting the negative half cycle signal of the alternating current signal.

6. The peak sample based electronic load ripple acquisition test module of claim 1, wherein: The first peak extraction circuit and the second peak extraction circuit have the same structure.

7. A peak sample based electronic load ripple acquisition test module according to claim 6, characterized by: The first peak extraction circuit comprises operational amplifier chips U2A, U2B, a transistor Q2 and a rectifier diode D2; pin 3 of the operational amplifier chip U2A serves as the input terminal of the first peak extraction circuit and is connected with the output terminal of the first amplification circuit and is used for receiving the positive half cycle signal of the alternating current signal, i.e. the V_AC signal; pin 2 of the operational amplifier chip U2A is connected with pin 7 of the operational amplifier chip U2B through the resistor R13, pin 1 of the operational amplifier chip U2A is connected with the positive terminal of the rectifier diode D2 through the resistor R10, the negative terminal of the rectifier diode is connected with pin 5 of the operational amplifier chip U2B, the negative terminal of the rectifier diode D2 is connected with the collector of the transistor Q2, the base of the transistor Q2 is connected with the RST signal, i.e. the RST signal output by the main DSP controller, the emitter of the transistor Q2 is grounded, pin 5 of the operational amplifier chip U2B is grounded through the capacitor C3, pin 6 of the operational amplifier chip U2B is connected with pin 7 of the operational amplifier chip U2B through the resistor R11, pin 7 of the operational amplifier chip U2B is grounded through the resistor R12 and the capacitor C4, and pin 6 of the operational amplifier chip U2B outputs the V_PK signal through the resistor R12, and the V_PK signal serves as the output signal of the first peak extraction circuit and is connected with the input terminal of the ADC1 in the main DSP controller.

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