Image data processing device and visual positioning system

Abstract

The utility model relates to an image data processing device and a visual positioning system. The device comprises a main control chip, a first digital processing chip, a second digital processing chip and a video data transceiving module, wherein the first digital processing chip and the second digital processing chip are connected with each other and are respectively connected to the main control chip; the main control chip is connected with the video data transceiving module; the video data transceiver module accesses video image data and sends the video image data to the main control chip; the main control chip distributes the video image data to the first digital processing chip and the second digital processing chip for target positioning calculation; the main control chip sends tracking video data returned by the first digital processing chip and the second digital processing chip to the video data transceiving module; the video data receiving and transmitting module outputs the tracking video data; according to the technical scheme, the processing efficiency of the video image data is improved, and the accuracy of the visual positioning system is improved.

Description

TECHNICAL FIELD

[0001] The application relates to the positioning technical field, in particular to an image data processing device and a visual positioning system. BACKGROUND

[0002] In the visual positioning system, the positioning navigation system based on image recognition and computer vision technology, the image processing board calculates the target position from the input video image after receiving the control command in the system, and outputs the tracking video and the position deviation, so that the positioning function of the visual positioning system is realized. The image processing board used in the visual positioning system on the market has low image data processing efficiency, so that the visual positioning system cannot be quickly and accurately positioned. CONTENT OF THE UTILITY MODEL

[0003] The application aims to solve one of the above technical defects, and provides an image data processing device and a visual positioning system, which improve the image data processing efficiency.

[0004] An image data processing device comprises a main control chip, a first digital processing chip, a second digital processing chip and a video data transceiver module; wherein the first digital processing chip and the second digital processing chip are connected to each other and connected to the main control chip respectively; and the main control chip is connected to the video data transceiver module.

[0005] The video data transceiver module accesses video image data and sends the video image data to the main control chip.

[0006] The main control chip distributes the video image data to the first digital processing chip and the second digital processing chip for target positioning calculation.

[0007] The main control chip sends the tracking video data returned by the first digital processing chip and the second digital processing chip to the video data transceiver module.

[0008] The video data transceiver module outputs the tracking video data.

[0009] In an embodiment, the image data processing device further comprises a PCB backboard.

[0010] The main control chip, the first digital processing chip, the second digital processing chip and the video data transceiver module are arranged on the PCB backboard.

[0011] In an embodiment, the main control chip comprises an FPGA chip and the memory and flash memory connected thereto.

[0012] The first digital processing chip comprises a first DSP chip and the memory and flash memory connected thereto.

[0013] The second digital processing chip comprises a second DSP chip and its connected memory and flash memory;

[0014] The first DSP chip and the second DSP chip are connected through an SRIO interface; the FPGA chip is connected with the first DSP chip and the second DSP chip through an EMIF interface, an SRIO interface and a GPIO interface respectively.

[0015] In one embodiment, the video data transceiver module comprises a PAL video encoder and a plurality of PAL video decoders.

[0016] The PAL video encoder receives video image data of a video signal source for A / D conversion and inputs the main control chip.

[0017] The PAL video decoder decodes the tracking video data and outputs the D / A converted data.

[0018] In one embodiment, the video data transceiver module further comprises a Camera Link video encoder and a Camera Link video decoder.

[0019] The Camera Link video encoder converts the input video image data into an LVDS data stream and inputs the FPGA chip.

[0020] The Camera Link video decoder decodes the tracking video data LVDS serial data stream into RGB video data and control data and outputs the same.

[0021] In one embodiment, the video data transceiver module further comprises a VGA video encoder connected with the main control chip, which is used to convert the RGB digital signal of the tracking video data into a VGA format differential current signal.

[0022] In one embodiment, the image data processing device further comprises a clock circuit connected with the main control chip, which is used to provide a plurality of clock signals.

[0023] In one embodiment, the image data processing device further comprises an Ethernet PHY chip connected with the first DSP chip, which is used to connect to a network port.

[0024] In one embodiment, the image data processing device further comprises a secondary power supply connected with the power supply interface, which is used to convert the power supply.

[0025] The power supply interface is connected with a power supply.

[0026] The visual positioning system comprises a plurality of cameras and the image data processing device; the camera is used for shooting video image data and inputting the image data processing device; the image data processing device is used for outputting tracking video data.

[0027] The technical scheme of the present application has the following technical effects:

[0028] The core control function is provided by the main control chip, the video image data accessed by the video data transceiver module is distributed to the first digital processing chip and the second digital processing chip for operation processing, and the tracking video data is output through the video data transceiver module; the technical scheme can use the main control chip, the first digital processing chip and the second digital processing chip to operate and process the video image, can quickly calculate the target position, and output the tracking video data and the position deviation, thereby improving the processing efficiency of the video image data and improving the accuracy of the visual positioning system.

[0029] The additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description or be understood by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 FIG. 1 is a circuit structure diagram of an image data processing device of an embodiment;

[0032] Figure 2 FIG. 1 is a circuit structure diagram of an image data processing device of an embodiment;

[0033] Figure 3 FIG. 1 is a circuit structure diagram of an image data processing device of an embodiment; DETAILED DESCRIPTION

[0034] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, in which the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as a limitation of the present application.

[0035] As will be understood by persons skilled in the art of the present technology, the singular forms "a," "an," "said," and "the" include plural referents unless the context clearly dictates otherwise. It should be further understood that the terms "comprise," "comprises," and "comprising," when used in this specification, specify the presence of stated features, integers, steps, or components but do not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

[0036] As will be understood by persons skilled in the art of the present technology, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0037] Reference Figure 1 As shown, Figure 1 is a circuit structure diagram of an image data processing device of an embodiment, comprising: a main control chip, a first digital processing chip, a second digital processing chip, and a video data transceiver module; wherein the first digital processing chip and the second digital processing chip are connected to each other and to the main control chip; the main control chip is connected to the video data transceiver module; the video data transceiver module accesses video image data and sends the video image data to the main control chip; the main control chip distributes the video image data to the first digital processing chip and the second digital processing chip for target positioning calculation; the main control chip sends the tracking video data returned by the first digital processing chip and the second digital processing chip to the video data transceiver module; the video data transceiver module outputs the tracking video data.

[0038] For example, the main control chip can include an FPGA (Field Programmable Gate Array) chip and its connected memory DDR3 and flash memory FLASH; the first digital processing chip includes a first DSP (Digital Signal Processing) chip DSP0 and its connected memory DDR3 and flash memory FLASH; the second digital processing chip includes a second DSP chip DSP1 and its connected memory DDR3 and flash memory FLASH.

[0039] As the scheme of the above embodiment, the core control function is provided by the main control chip, the video image data accessed by the video data transceiver module is distributed to the first digital processing chip and the second digital processing chip for operation processing, and the tracking video data is output through the video data transceiver module; the technical scheme can utilize the main control chip, the first digital processing chip and the second digital processing chip to perform operation processing on the video image, can quickly calculate the target position, and output the tracking video data and the position deviation, thereby improving the processing efficiency of the video image data and improving the accuracy of the visual positioning system.

[0040] Reference Figure 2 As shown in the figure, Figure 2 is a schematic diagram of the circuit board structure of the image data processing device of an embodiment. As shown in the figure, Figure 2 The image data processing device of the present application further comprises a PCB backboard and a backboard interface; wherein the main control chip FPGA, the first digital processing chip DSP0, the second digital processing chip DSP1 and the video data transceiver module are arranged on the PCB backboard; the first DSP chip and the second DSP chip are connected through an SRIO (Serial Rapid IO, Serial Rapid IO) interface; the FPGA chip is connected with the first DSP chip and the second DSP chip through an EMIF (External Memory Interface, External Memory Interface) interface, an SRIO interface and a GPIO (General-purpose input / output, General-purpose input / output) interface, respectively; for example, the main control chip FPGA, the first digital processing chip DSP0 and the second digital processing chip DSP1 are respectively connected with a JTAG (Joint Test Action Group, Joint Test Action Group) interface for testing.

[0041] For example, the FPGA chip can be a JFM7K325T FPGA chip, which integrates programmable resources that can be flexibly configured and combined, is used to realize input / output interfaces, general digital logic, memory, digital signal processing, clock management and other functions, and provides rich special clock and wiring resources, is suitable for realizing complex and high-speed digital logic circuits, has 326k logic units, has 840 DSP Slices, supports a maximum of 16Mbit Block RAM, has 10 clock management CMTs, has 16 GTXs, and supports DDR3 DRAM and other performance and characteristics.

[0042] Exemplarily, the FPGA chip uses the SPI interface FLASH to store the starting program, for example, the GD25Q256EYIG chip can be used, which has a 256Mbit storage space; supports the SPI interface, and simultaneously supports Dual-SPI, Quad-SPI and QPI; supports a 133MHz clock signal, and the Quad-SPI supports a 532Mhz communication baud rate; supports online starting through the SPI interface; is powered by a single 3.3V power supply, and adopts a WSON8 small package.

[0043] Exemplarily, the first DSP chip and the second DSP chip can both use the FT-M6678N chip with a multi-core floating point, which has fixed-point and floating-point operation capabilities, for example, the fixed-point operation performance is 256GMAC / s@1GHz and 320GMAC / s@1.25GHz, and the floating-point operation performance is 128GFLOPS@1GHz and 160GFLOPS@1.25GHz; a single chip contains 8 high-performance DSP cores; the highest working frequency is not less than 1GHz when the core voltage is 0.9V, and is not less than 1.25GHz when the core voltage is 0.95V; each core has a 32K byte L1P, a 32K byte L1D and a 512K byte local L2; 8 cores share a 4096K byte shared SRAM; a 64bit DDR3 interface reaches an available memory space of 8GB; 2-way Serial RapidIO high-speed serial link, each Serial RapidIO: 4Lane, transmission rate of each Lane is 1.25Gbps, 2.5Gbps or 3.125Gbps; 1-way PCIE (PCI Express, high-speed serial computer bus) high-speed serial link: 4Lane, transmission rate of each Lane is 2.5Gbps or 5Gbps; 1-way SGMII Ethernet interface: transmission rate is 1000Mbps, 100Mbps or 10Mbps.

[0044] Exemplarily, the DSP chip can use the GD25LB256EYIG chip, which has a 256Mbit storage space; an SPI interface, which simultaneously supports Dual-SPI, Quad-SPI and QPI; a 133MHz clock signal, and the Quad-SPI supports a 532Mhz communication baud rate; supports online starting through the SPI interface; is powered by a single 1.8V power supply; and has the performance and characteristics of a WSON8 small package.

[0045] Exemplary, the memory of the DSP chip, namely the internal memory and the flash memory can adopt two FT-M6678N externally expanded 4 pieces of DDR3 chip SCB15H2G160AF-13KI chip, to form 128M*64bit, a total of 1GB capacity space; the SCB15H2G160AF-13KI chip has 16bit data width, 128M byte capacity; VDD=VDDQ=1.35V, while backward compatible support 1.5V application, suitable for VDD=VDDQ=1.5V working condition; differential bidirectional data strobe; 8n-bit data prefetch architecture; differential clock input; internally contains 8 banks; the data, strobe, mask signal has a rated dynamic ODT (ON-DIE termination); industrial grade (-40℃≤TC≤+95℃) product and the like functions and features.

[0046] In one embodiment, as shown in Figure 2 The video data transceiver module includes a PAL (Phase Alteration Line, also known as PAL system, progressive line inversion format) video encoder (i.e. PAL encoder in the figure) and a plurality of PAL video decoders (i.e. PAL decoder 1-3 in the figure); the PAL video encoder receives the video image data of the video signal source for A / D conversion and inputs the main control chip; the PAL video decoder decodes the tracking video data and outputs after D / A conversion.

[0047] Exemplary, the PAL video encoder can adopt GM7121-D chip as the PAL interface video encoding chip, to realize receiving 8bit CCIR656 format YUV data, (such as MPEG decoding data), and encoding into CVBS signal, and output after D / A conversion. The basic encoding functions include subcarrier generation, chroma signal modulation, synchronization signal interpolation; the device is packaged as LQFP44, the wide power voltage range is 3.1~3.3V, and the working temperature range is -40~+85℃. The PAL video decoder can adopt GM7150A chip as the PAL interface video decoding chip, the chip adopts CMOS process, and is connected with the PC or the DSP to form an application system through the I2C bus. It internally contains 1 analog processing channel, can realize CVBS, S-Video video signal source selection, A / D conversion, automatic clamping, automatic gain control (AGC), clock generation (CGC), multi-standard decoding, brightness / contrast / saturation control (BCS); the device is packaged as CLCC32, and the working temperature range is -40~+85℃.

[0048] In one embodiment, as shown in Figure 2As shown, the video data transceiving module further comprises a Camera Link video encoder (i.e., C-Link encoder in the figure) and a Camera Link video decoder (i.e., C-Link decoder in the figure); the Camera Link video encoder converts the input video image data into an LVDS data stream inputting the FPGA chip; and the Camera Link video decoder decodes the tracking video data LVDS serial data stream into RGB video data and control data for output.

[0049] For example, the Camera Link video encoder uses GM8283 chip as the Camera Link video encoding chip, which can convert 28bits LVTTL / LVCMOS data input in parallel into 4-way serial LVDS data stream. After phase-locked internally, the input clock is output at the same frequency, and is converted into LVDS differential form while maintaining synchronization with the output serial data stream; the clock frequency is 10MHz-85MHz; in each clock cycle, 24bits of RGB data and 3bits of control data are transmitted in 4 LVDS serial channels, and the single-channel data rate can be up to 630Mbps. The device is packaged in LQFP44, with a wide power voltage range of 3.0-3.6V and a working temperature range of -55-+125℃.

[0050] The Camera Link video decoder can use GM8284 chip as the Camera Link video decoding chip, which can convert 4-way LVDS data stream input in series into 28bits LVTTL / LVCMOS data; the input LVDS clock is output at the same frequency in LVCMOS form after phase-locked internally, and maintains synchronization with the output parallel data; the clock frequency is 10MHz-90MHz; in each clock cycle, the serial data stream received in 4 LVDS channels is decompressed into 24bits of RGB data and 3bits of control data, and the receiving port channel data rate can be up to 525Mbps. The device is packaged in LQFP44, with a wide power voltage range of 3.0-3.6V and a working temperature range of -55-+125℃.

[0051] In one embodiment, as shown in Figure 2 The video data transceiving module further comprises a VGA (Video Graphics Array, a video transmission standard) video encoder (i.e., VGA encoder in the figure) connected to the main control chip, for converting the RGB digital signal of the tracking video data into VGA format differential current signal.

[0052] Exemplarily, the VGA video encoder can adopt GMG7123 chip as the VGA video encoding chip, has 3 channels of high-speed DAC chip, the DAC adopts segmented current steering structure, and can realize the conversion rate of 330MSPS at most; the chip adopts 3.3V single power supply, inputs 30-bit RGB digital signal, and outputs differential current signal after digital-to-analog conversion; when the external adjustable resistor is 560Ω, the maximum output current is 17.62mA; when the adjustable resistor is 4933Ω, the maximum output current is 2mA. The integrated internal bandgap reference circuit can self-build 1.23V voltage. The typical power consumption is 220mW, with power saving mode, the power consumption is less than 1mW when the power saving is turned on; the shell adopts CQFP48 package. The working temperature range is-55~+125℃.

[0053] In one embodiment, as shown in Figure 2 The image data processing device of the application further comprises: an Ethernet PHY chip connected to the first DSP chip, used for connecting to a network port, and the first DSP chip is further connected to a PCIe interface.

[0054] Exemplarily, the Ethernet PHY chip can adopt JXYI8211QFN chip, connected to the DSP1SGMII interface, can be output to the backplane connector through the on-board network transformer, has the composite 1000 / 100 / 10Base-T IEEE 802.3 standard, the RGMII interface supports the characteristics of being configured as 1.8V, 2.5V, 3.3V level signal, the JCX8211QFN chip supports SerDes interface, the SerDes interface can be configured as SGMII, 1000Base-X or 100Base-FX, the shell adopts QFN48 package, and the working temperature range is-55~+125℃. Among them, the network transformer can select HR682434E transformer, and the working temperature range is-40~+85℃.

[0055] In one embodiment, as shown in Figure 2 The image data processing device of the application further comprises: a clock circuit connected to the main control chip, used for providing a plurality of clock signals.

[0056] Exemplarily, the clock circuit can include the following:

[0057]

[0058]

[0059] As shown in the above table, in the case that the image data processing device circuit is complex and a plurality of clocks are required, a rich clock source is provided, so that accurate clock sources can be provided for each component.

[0060] In one embodiment, the PCB backboard of the image data processing device can adopt a CPCI-E backboard, and each component is connected to the PCB backboard through a connector; for example, the backboard interface can be provided as 8 interface modules of XP1-XP8, wherein

[0061] XP1 includes: 1 12V power supply interface, providing 12V DC power supply;

[0062] XP2 includes: 1 Ethernet interface (gigabit Ethernet interface output) and 1 PCIe interface;

[0063] XP3 includes: 1 Camera Link input port, PAL video encoder input port and 3 composite PAL video decoder output ports;

[0064] XP4-XP6 includes: 4 RS-422 communication interfaces (including 2 system communication interfaces and 2 board communication interfaces), 1 RS-422 system reset signal interface, 1 RS-422 timing signal interface, 5 GPIO interfaces and 1 VGA output; wherein each RS-422 communication realizes data communication through an RS-422 transceiver.

[0065] XP7 includes: 1 PCIe interface (connected to the second DSP chip), 4 SRIO interfaces;

[0066] XP8 includes: 1 composite Cameralink Base video output port.

[0067] In one embodiment, the image data processing device further includes: a secondary power supply connected to the power supply interface, for converting the power supply; wherein the power supply interface accesses the power supply.

[0068] For example, the input voltage 12V DC can adopt LYM4644IY micro module DC-DC converter and TPL51200-DF8R linear regulator, the DC-DC input voltage range is 4-14V, the output voltage range is 0.6-5.5V, the single continuous output maximum current is 4A, the maximum output current of 4-way parallel connection is 16A, and the overall efficiency is not less than 85%, with high transient response and low output voltage ripple. The device is packaged as BGA77, and the working temperature range is -40-+125℃; the linear regulator input voltage range is 2.375-5.5V, supporting the VTT voltage of DDR-DDR4 output, supporting the maximum 3A sinking current capability; the device is packaged as DFN-10, and the working temperature range is -40-+125℃.

[0069] The embodiments of the visual positioning system are described below.

[0070] ReferenceFigure 3 is shown, Figure 3 is a schematic diagram of an example visual positioning system structure, which comprises a plurality of cameras and the image data processing device of any of the above embodiments; wherein the cameras are configured to capture video image data and input the video image data to the image data processing device; and the image data processing device is configured to output tracking video data.

[0071] According to the above-mentioned embodiments, the video image can be processed by the main control chip, the first digital processing chip and the second digital processing chip of the image data processing device, the target position can be quickly calculated, and the tracking video data and the position deviation can be output, thereby improving the processing efficiency of the video image data and improving the accuracy of the visual positioning system.

[0072] The above only describes some embodiments of the present application. It should be noted that those skilled in the art can make some improvements and refinements without departing from the principles of the present application, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. An image data processing apparatus characterized by comprising: The image data processing device comprises: a main control chip, a first digital processing chip, a second digital processing chip and a video data transceiver module; wherein the first digital processing chip and the second digital processing chip are connected to each other and to the main control chip; the main control chip is connected to the video data transceiver module; the video data transceiver module receives video image data and sends the video image data to the main control chip; the main control chip distributes the video image data to the first digital processing chip and the second digital processing chip for target positioning calculation; the main control chip sends the tracking video data returned by the first digital processing chip and the second digital processing chip to the video data transceiver module; the video data transceiver module outputs the tracking video data.

2. The image data processing apparatus according to claim 1, characterized by Further comprising: a PCB backplane; the main control chip, the first digital processing chip, the second digital processing chip and the video data transceiver module are arranged on the PCB backplane.

3. The image data processing apparatus according to claim 2, characterized by The main control chip comprises an FPGA chip and its connected memory and flash memory; The first digital processing chip comprises a first DSP chip and its connected memory and flash memory; The second digital processing chip comprises a second DSP chip and its connected memory and flash memory; The first DSP chip and the second DSP chip are connected through an SRIO interface; the FPGA chip is connected to the first DSP chip and the second DSP chip through an EMIF interface, an SRIO interface and a GPIO interface respectively.

4. The image data processing apparatus according to claim 3, characterized by The video data transceiver module comprises a PAL video encoder and a plurality of PAL video decoders; The PAL video encoder receives video image data from a video signal source for A / D conversion and inputs the video image data to the main control chip; The PAL video decoder decodes the tracking video data and outputs the tracking video data after D / A conversion.

5. The image data processing apparatus according to claim 4, characterized by The video data transceiver module further comprises a Camera Link video encoder and a Camera Link video decoder; The Camera Link video encoder converts the input video image data into LVDS data stream and inputs the LVDS data stream to the FPGA chip; The Camera Link video decoder decodes the tracking video data LVDS serial data stream into RGB video data and control data and outputs the RGB video data and the control data.

6. The image data processing apparatus according to claim 5, characterized by The video data transceiver module further comprises a VGA video encoder connected to the main control chip, which is used to convert the RGB digital signal of the tracking video data into a VGA format differential current signal.

7. The image data processing apparatus according to claim 1, characterized by Further comprising: a clock circuit connected to the main control chip, which is used to provide multiple clock signals.

8. The image data processing apparatus according to claim 3, characterized by Further comprising: an Ethernet PHY chip connected to the first DSP chip, which is used to connect to a network port.

9. The image data processing apparatus according to claim 1, characterized by Further comprising: a secondary power supply connected to a power supply interface, which is used to convert a power supply; wherein the power supply interface is connected to a power supply.

10. A vision positioning system characterized by, The image data processing device comprises: a plurality of cameras and the image data processing device of any one of claims 1-9; wherein the cameras are used to capture video image data and input the video image data to the image data processing device; the image data processing device is used to output tracking video data.

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