Storage and calculation integrated server and data center

Abstract

The utility model provides a storage and calculation integrated server and a data center, and relates to the technical field of server architecture design, and the storage and calculation integrated server comprises a calculation resource module and at least one storage resource module; the storage resource module comprises a first data processor, a second data processor, a backboard assembly and a plurality of storage units. The first data processor and the second data processor are both connected with the computing resource module, the first data processor and the second data processor are further connected with the backboard assembly, and the backboard assembly is further connected with the multiple storage units. And the first data processor accesses part or all of the storage units according to a storage instruction sent by the computing resource module. And the second data processor accesses part or all of the storage units according to a storage instruction sent by the computing resource module. The first data processor and the second data processor are arranged to form a double-control double-active high-availability architecture, so that the problem of single-point failure of storage resources in the server is solved, and the reliability of storage node levels is improved.

Description

Technical Field

[0001] This application relates to the field of server architecture design technology, and more specifically, to a storage-and-computing server and data center. Background Technology

[0002] With the rapid development of AI (Artificial Intelligence) technology, the efficient synergy of computing and storage capabilities of AI servers has become key to improving overall performance.

[0003] However, to meet the demands of edge AI computing, current AI servers (such as intelligent computing all-in-one machines) are typically designed with computing resources at their core, treating storage resources as secondary, lacking node-level storage reliability guarantees. This server architecture exposes storage resources to single points of failure, potentially impacting system stability and data security.

[0004] Therefore, how to solve the single point of failure problem of storage resources in servers and improve the reliability of storage nodes is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] The purpose of this application is to provide a storage-computing server and data center to solve the single point of failure problem of storage resources in the server and improve the reliability of storage nodes.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0007] On one hand, this application provides a storage-computing server, including: a computing resource module and at least one storage resource module; the storage resource module includes: a first data processor, a second data processor, a backplane assembly, and multiple storage units;

[0008] Both the first data processor and the second data processor are connected to the computing resource module, and both the first data processor and the second data processor are also connected to the backplane assembly, which is also connected to a plurality of the storage units respectively.

[0009] The first data processor is used to access some or all of the storage units according to the storage instructions sent by the computing resource module;

[0010] The second data processor is used to access some or all of the storage units according to the storage instructions sent by the computing resource module.

[0011] Furthermore, the plurality of storage units include a plurality of dual-channel storage units, and the backplane assembly includes a plurality of dual-control backplanes;

[0012] Each of the dual-control backplanes is connected to the first data processor and the second data processor respectively, and each of the dual-control backplanes is also connected to a plurality of dual-channel storage units; each of the dual-channel storage units is connected to the first data processor and the second data processor respectively through the corresponding dual-control backplane;

[0013] The first data processor is used to access all the dual-channel storage units according to the storage instructions sent by the computing resource module;

[0014] The second data processor is used to access all the dual-channel storage units according to the storage instructions sent by the computing resource module.

[0015] Furthermore, the plurality of storage units include a plurality of first single-channel storage units and a plurality of second single-channel storage units, and the backplane assembly includes a plurality of first single-control backplanes and a plurality of second single-control backplanes;

[0016] Each of the first single-control backplanes is connected to the first data processor, and each of the first single-control backplanes is also connected to a plurality of first single-channel storage units; each of the second single-control backplanes is connected to the second data processor, and each of the second single-control backplanes is also connected to a plurality of second single-channel storage units;

[0017] The first data processor is used to access all the first single-channel storage units according to the storage instructions sent by the computing resource module;

[0018] The second data processor is used to access all the second single-channel storage units according to the storage instructions sent by the computing resource module.

[0019] Furthermore, the plurality of storage units include a plurality of first single-channel storage units, a plurality of second single-channel storage units, and a plurality of dual-channel storage units, and the backplane assembly includes a plurality of first single-control backplanes, a plurality of second single-control backplanes, and a plurality of dual-control backplanes;

[0020] Each of the first single-control backplanes is connected to the first data processor, and each of the first single-control backplanes is also connected to a plurality of first single-channel storage units; each of the second single-control backplanes is connected to the second data processor, and each of the second single-control backplanes is also connected to a plurality of second single-channel storage units; each of the dual-control backplanes is connected to the first data processor and the second data processor respectively, and each of the dual-control backplanes is also connected to a plurality of dual-channel storage units;

[0021] The first data processor is used to access all the first single-channel storage units and all the dual-channel storage units according to the storage instructions sent by the computing resource module;

[0022] The second data processor is used to access all the second single-channel storage units and all the dual-channel storage units according to the storage instructions sent by the computing resource module.

[0023] Furthermore, the computing resource module includes a motherboard, and a central processing unit, a switch, and multiple first graphics processors disposed on the motherboard;

[0024] Multiple first graphics processors are connected to the switch, which is also connected to the central processing unit; the first data processor and the second data processor are both pluggably connected to the motherboard via PCIe links.

[0025] Furthermore, the storage resource module also includes a first power supply and a second power supply;

[0026] The first power supply is connected to the first data processor, the second data processor, and the backplane assembly, respectively; the second power supply is connected to the first data processor, the second data processor, and the backplane assembly, respectively.

[0027] Furthermore, the storage resource module also includes a second graphics processor and a third graphics processor;

[0028] The first data processor is also connected to the second graphics processor, and the second data processor is also connected to the third graphics processor;

[0029] The first data processor is further configured to access some or all of the storage units according to the storage instructions sent by the second graphics processor;

[0030] The second data processor is also configured to access some or all of the storage units according to storage instructions sent by the third graphics processor.

[0031] Furthermore, the first data processor is connected to the computing resource module, the second graphics processor, and the backplane assembly via PCIe links;

[0032] The second data processor is connected to the computing resource module, the third graphics processor, and the backplane assembly via PCIe links.

[0033] Furthermore, the storage unit is a CXL storage device or an SSD.

[0034] On the other hand, this application also provides a data center, which includes a storage-computing server as described in any of the foregoing embodiments.

[0035] Compared with the prior art, this application has the following advantages:

[0036] This application provides a storage-computing server and data center. The storage-computing server includes a computing resource module and at least one storage resource module. The storage resource module includes a first data processor, a second data processor, a backplane assembly, and multiple storage units. Both the first and second data processors are connected to the computing resource module, and both are also connected to the backplane assembly, which in turn is connected to the multiple storage units. The first data processor accesses some or all of the storage units according to storage instructions sent by the computing resource module. The second data processor accesses some or all of the storage units according to storage instructions sent by the computing resource module. This application establishes a dual-controller, dual-active high-availability architecture by configuring the first and second data processors. Specifically, under normal operating conditions, both data processors operate simultaneously, each capable of accessing some or all of the storage units, achieving both load balancing and redundancy. When one data processor fails (i.e., a single point of failure occurs), the other data processor can still independently maintain operation and continue accessing the corresponding storage units, ensuring the continuity of storage services. This dual-controller, dual-active server architecture effectively solves the single point of failure problem of storage resources in servers, greatly improving the reliability at the storage node level. Attached Figure Description

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0038] Figure 1 This is one of the structural schematic diagrams of a storage-computing server provided in an embodiment of this application;

[0039] Figure 2 This is a second schematic diagram of the structure of a storage-computing server provided in an embodiment of this application;

[0040] Figure 3 This is the third schematic diagram of the structure of an in-memory computing server provided in the embodiments of this application;

[0041] Figure 4 This is the fourth schematic diagram of the structure of an in-memory computing server provided in the embodiments of this application;

[0042] Figure 5 This is the fifth schematic diagram of the structure of an in-memory computing server provided in the embodiments of this application.

[0043] Icons: 10 - In-Storage Computing Server; 100 - Computing Resource Module; 110 - Motherboard; 120 - Central Processing Unit; 130 - Switch; 140 - First Graphics Processor; 200 - Storage Resource Module; 210 - First Data Processor; 220 - Second Data Processor; 230 - Backplane Assembly; 231 - Dual-Control Backplane; 232 - First Single-Control Backplane; 233 - Second Single-Control Backplane; 240 - Storage Unit; 241 - Dual-Channel Storage Unit; 242 - First Single-Channel Storage Unit; 243 - Second Single-Channel Storage Unit; 250 - First Power Supply; 260 - Second Power Supply; 270 - Second Graphics Processor; 280 - Third Graphics Processor. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0045] In the description of this application, it should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be interpreted broadly, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0046] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0047] As described in the background section, to meet the demands of edge AI computing, current AI servers (such as intelligent computing all-in-one machines) are typically designed with computing resources at their core, treating storage resources as secondary, lacking node-level storage reliability guarantees. This server architecture exposes storage resources to single-point-of-failure risks, potentially impacting system stability and data security. Therefore, addressing the single-point-of-failure problem of storage resources in servers and improving the reliability of storage nodes is a crucial technical challenge for those skilled in the art.

[0048] To resolve the above technical issues, please refer to Figure 1 This application provides a storage-in-memory server 10, which includes a computing resource module 100 and at least one storage resource module 200. The storage resource module 200 includes a first data processor 210, a second data processor 220, a backplane assembly 230, and multiple storage units 240.

[0049] The first data processor 210 and the second data processor 220 are both connected to the computing resource module 100, and the first data processor 210 and the second data processor 220 are also connected to the backplane assembly 230, which is also connected to a plurality of storage units 240.

[0050] The first data processor 210 is used to access some or all of the storage units 240 according to the storage instructions sent by the computing resource module 100.

[0051] The second data processor 220 is used to access some or all of the storage units 240 according to the storage instructions sent by the computing resource module 100.

[0052] It should be noted that, in this embodiment, both the first data processor 210 and the second data processor 220 are DPUs (Data Processing Units). Furthermore, the access operations of the first data processor 210 and the second data processor 220 include, but are not limited to, data reading, writing, erasing, and other storage operations. In addition, the storage unit 240 in this embodiment is a storage medium with persistent or temporary data storage capabilities, such as a CXL (Compute ExpressLink) storage device or an SSD (Solid State Drive).

[0053] Based on the above design, this application embodiment adopts a highly reliable storage architecture design, wherein the number of storage resource modules 200 can be configured to be one or more as needed. Each storage resource module 200 adopts a dual data processor design (i.e., a first data processor 210 and a second data processor 220), forming a dual-controller, dual-active high-availability architecture. Specifically, under normal operating conditions, both data processors work simultaneously, each having the ability to access some or all of the storage units 240, achieving both load balancing and redundancy protection. When one data processor fails (i.e., a single point of failure occurs), the other data processor can still independently maintain operation and continue to access the corresponding storage unit 240, ensuring the continuity of storage services. This dual-controller, dual-active server architecture design effectively solves the single point of failure problem of storage resources in the server, greatly improving the reliability at the storage node level.

[0054] In addition, to adapt to different application scenarios, the storage unit 240 in this application embodiment can be divided into two types: dual-channel storage unit and single-channel storage unit.

[0055] The dual-channel storage unit adopts an independent dual-data-channel design (PCIE 2x2), which can support parallel access from two data processors simultaneously, significantly improving data processing speed and making it suitable for scenarios with high bandwidth and high performance requirements.

[0056] A single-channel storage unit is equipped with only a single data channel (PCIe 1x4), allowing only one data processor to access it at a time. It is suitable for scenarios with lower memory bandwidth requirements, lower cost, and better compatibility.

[0057] For different types of storage units 240, this application provides the following various implementation methods:

[0058] As an optional implementation, please refer to Figure 2 The multiple storage units 240 include: multiple dual-channel storage units 241 (i.e., all multiple storage units 240 are dual-channel storage units), and the backplane assembly 230 includes: multiple dual-controller backplanes 231.

[0059] Each dual-control backplane 231 is connected to the first data processor 210 and the second data processor 220 respectively, and each dual-control backplane 231 is also connected to multiple dual-channel storage units 241. That is, each dual-channel storage unit 241 is connected to the first data processor 210 and the second data processor 220 respectively through the corresponding dual-control backplane 231.

[0060] The first data processor 210 is used to access all dual-channel storage units 241 (i.e. all storage units 240) according to the storage instructions sent by the computing resource module 100.

[0061] The second data processor 220 is used to access all dual-channel storage units 241 (i.e., all storage units 240) according to the storage instructions sent by the computing resource module 100.

[0062] Under normal operating conditions, the first data processor 210 and the second data processor 220 can simultaneously access all dual-channel memory units 241 (i.e., all memory units 240). When the first data processor 210 fails, the second data processor 220 can still continue to access all dual-channel memory units 241 (its access path is as follows). Figure 2 (As indicated by the white double arrows in the diagram). Similarly, when the second data processor 220 fails, the first data processor 210 can still continue to access all dual-channel memory units 241 (its access path is as follows). Figure 2 (As shown by the black double arrows in the image), thereby solving the single point of failure problem of storage resources in the server and improving the reliability at the storage node level.

[0063] As another alternative implementation, please refer to Figure 3 The multiple storage units 240 include: multiple first single-channel storage units 242 and multiple second single-channel storage units 243 (i.e., all multiple storage units 240 are single-channel storage units), and the backplane assembly 230 includes: multiple first single-control backplanes 232 and multiple second single-control backplanes 233.

[0064] Each first single-control backplane 232 is connected to the first data processor 210, and each first single-control backplane 232 is also connected to multiple first single-channel storage units 242. Each second single-control backplane 233 is connected to the second data processor 220, and each second single-control backplane 233 is also connected to multiple second single-channel storage units 243.

[0065] The first data processor 210 is used to access all first single-channel storage units 242 (i.e., a portion of storage units 240) according to storage instructions sent by the computing resource module 100.

[0066] The second data processor 220 is used to access all second single-channel storage units 243 (i.e., a portion of storage units 240) according to storage instructions sent by the computing resource module 100.

[0067] Under normal operating conditions, the first data processor 210 can access all first single-channel storage units 242 (the access paths are as follows). Figure 3 (As shown by the black double arrows in the image), the second data processor 220 can access all the second single-channel storage units 243 (its access path is as follows). Figure 3(As indicated by the white double arrows in the diagram). When the first data processor 210 fails, the second data processor 220 can only access all the second single-channel storage units 243, but cannot access all the first single-channel storage units 242 (i.e., the second data processor 220 can only access a portion of the storage units 240). Similarly, when the second data processor 220 fails, the first data processor 210 can only access all the first single-channel storage units 242, but cannot access all the second single-channel storage units 243 (i.e., the first data processor 210 can only access a portion of the storage units 240). This design ensures storage continuity while still addressing the single point of failure problem of storage resources in the server, thereby improving the reliability at the storage node level.

[0068] As another alternative implementation, please refer to Figure 4 The multiple storage units 240 include: multiple first single-channel storage units 242, multiple second single-channel storage units 243 and multiple dual-channel storage units 241 (that is, the multiple storage units 240 adopt a hybrid design, some of which are single-channel storage units and some of which are dual-channel storage units), and the backplane assembly 230 includes: multiple first single-control backplanes 232, multiple second single-control backplanes 233 and multiple dual-control backplanes 231.

[0069] Each first single-control backplane 232 is connected to a first data processor 210, and each first single-control backplane 232 is also connected to multiple first single-channel storage units 242. Each second single-control backplane 233 is connected to a second data processor 220, and each second single-control backplane 233 is also connected to multiple second single-channel storage units 243. Each dual-control backplane 231 is connected to both the first data processor 210 and the second data processor 220, and each dual-control backplane 231 is also connected to multiple dual-channel storage units 241.

[0070] The first data processor 210 is used to access all first single-channel storage units 242 and all dual-channel storage units 241 (i.e., some storage units 240) according to the storage instructions sent by the computing resource module 100.

[0071] The second data processor 220 is used to access all second single-channel storage units 243 and all dual-channel storage units 241 (i.e., some storage units 240) according to the storage instructions sent by the computing resource module 100.

[0072] Under normal operating conditions, the first data processor 210 and the second data processor 220 can simultaneously access all dual-channel memory units 241, and the first data processor 210 can also access all first single-channel memory units 242, while the second data processor 220 can also access all second single-channel memory units 243. When the first data processor 210 malfunctions, it cannot access all first single-channel memory units 242, but the second data processor 220 can still access all dual-channel memory units 241 and all second single-channel memory units 243 (its access path is as follows). Figure 4 (As indicated by the white double arrows in the diagram). Similarly, when the second data processor 220 malfunctions, it cannot access all second single-channel memory cells 243, but the first data processor 210 can still access all dual-channel memory cells 241 and all first single-channel memory cells 242 (its access path is as follows). Figure 4 (As shown by the white double arrows in the image), ensuring uninterrupted storage access solves the single point of failure problem of storage resources in the server, thereby improving the reliability at the storage node level.

[0073] Further, please refer to Figure 5 In this embodiment, the computing resource module 100 includes a motherboard 110, a central processing unit 120, a switch 130, and a plurality of first graphics processors 140 disposed on the motherboard 110. Optionally, the switch 130 is a PCIe switch chip.

[0074] Multiple first graphics processors 140, serving as computing resources, are connected to a switch 130, which in turn is connected to a central processing unit 120. First data processors 210 and second data processors 220 are both pluggably connected to the motherboard 110 via PCIe links.

[0075] The first data processor 210 and the second data processor 220 interact with the first graphics processor 140 and the central processing unit 120 on the motherboard 110 via independent PCIe links, and at the same time obtain power supply from the motherboard 110 via PCIe links.

[0076] In addition, to ensure that the storage resources can continue to provide services when the motherboard 110 restarts due to a fault (i.e., the motherboard 110 loses power), in an optional implementation, the storage resource module 200 also includes a first power supply 250 and a second power supply 260.

[0077] The first power supply 250 is connected to the first data processor 210, the second data processor 220 and the backplane assembly 230 respectively, and the second power supply 260 is connected to the first data processor 210, the second data processor 220 and the backplane assembly 230 respectively.

[0078] Based on the above design, the first data processor 210 and the second data processor 220 not only obtain power through the PCIe link of the motherboard 110, but are also connected to independent first power supplies 250 and second power supplies 260 respectively. This multi-power supply design ensures that even if the motherboard 110 loses power, the first data processor 210 and the second data processor 220 can continue to operate, ensuring uninterrupted storage services and improving the reliability at the storage node level. Furthermore, through a dual-power independent redundant design (i.e., the first power supply 250 supplies power to the first data processor 210, the second data processor 220, and the backplane assembly 230 respectively, and the second power supply 260 supplies power to the first data processor 210, the second data processor 220, and the backplane assembly 230 respectively), it is ensured that when any one power supply fails, the other power supply can still continuously supply power to the first data processor 210, the second data processor 220, and the backplane assembly 230. In other words, this application achieves seamless switching in the event of a single power supply failure through a redundant power supply architecture design, further ensuring storage continuity and high availability.

[0079] In addition, it should be noted that the first graphics processor 140 in the computing resource module 100 needs to go through the switch 130 and the central processing unit 120 in sequence before it can access the storage unit 240 through the data processor. This long physical link (which requires cross-network communication) will cause a significant increase in the latency of computing resources accessing storage.

[0080] To reduce the latency of acquiring storage resources from computing resources, in this embodiment, the storage resource module 200 further includes a second graphics processor 270 and a third graphics processor 280. The first data processor 210 is also connected to the second graphics processor 270, and the second data processor 220 is also connected to the third graphics processor 280.

[0081] The first data processor 210 is also used to access some or all of the memory units 240 according to the storage instructions sent by the second graphics processor 270.

[0082] The second data processor 220 is also used to access some or all of the memory units 240 according to the storage instructions sent by the third graphics processor 280.

[0083] It should be noted that the first graphics processor 140, the second graphics processor 270, and the third graphics processor 280 are all GPUs (Graphics Processing Units). Furthermore, this application does not limit the specific number of the first graphics processor 140, the second graphics processor 270, and the third graphics processor 280; the number of each graphics processor can be flexibly configured according to actual needs to meet the scalability requirements of different computing scenarios.

[0084] Furthermore, the first data processor 210 is connected to the computing resource module 100, the second graphics processor 270, and the backplane assembly 230 via PCIe links. The second data processor 220 is connected to the computing resource module 100, the third graphics processor 280, and the backplane assembly 230 via PCIe links.

[0085] Based on the above design, this application utilizes the built-in PCIESWITCH device access capabilities of the first data processor 210 and the second data processor 220 to directly connect the second graphics processor 270 to the first data processor 210 and the third graphics processor 280 to the second data processor 220, without needing to go through the central processing unit 120. This direct-connect architecture shortens the physical link between computing resources and storage resources, thereby reducing the latency of computing resources accessing storage resources. For large model training and inference scenarios, it can further reduce latency and improve overall system performance.

[0086] Optionally, embodiments of this application also provide a data center, which includes a storage-computing server 10 as described in any of the foregoing embodiments.

[0087] In summary, this application provides a storage-computing server and data center. The storage-computing server includes a computing resource module and at least one storage resource module. The storage resource module includes a first data processor, a second data processor, a backplane assembly, and multiple storage units. Both the first and second data processors are connected to the computing resource module, and both are also connected to the backplane assembly, which in turn is connected to the multiple storage units. The first data processor accesses some or all of the storage units according to storage instructions sent by the computing resource module. The second data processor accesses some or all of the storage units according to storage instructions sent by the computing resource module. This application forms a dual-controller, dual-active high-availability architecture by configuring the first and second data processors. Specifically, under normal operating conditions, both data processors operate simultaneously, each capable of accessing some or all of the storage units, achieving both load balancing and redundancy. When one data processor fails (i.e., a single point of failure occurs), the other data processor can still independently maintain operation and continue accessing the corresponding storage units, ensuring the continuity of storage services. This dual-controller, dual-active server architecture effectively solves the single point of failure problem of storage resources in the server, and greatly improves the reliability at the storage node level.

[0088] Furthermore, by directly connecting the second graphics processor to the first data processor and the third graphics processor to the second data processor, this application shortens the electrical link distance between computing and storage resources, thereby effectively reducing storage access latency. Moreover, the in-memory computing server provided by this application saves more rack space and has a higher chassis density compared to ordinary servers.

[0089] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0090] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A storage-computing integrated server, characterized in that, The application relates to a storage resource module and a computing resource module. The storage resource module comprises a first data processor, a second data processor, a backplane assembly and a plurality of storage units. The first data processor and the second data processor are connected with the computing resource module, and the first data processor and the second data processor are also connected with the backplane assembly, and the backplane assembly is also connected with the plurality of storage units respectively. The first data processor is used for accessing part or all of the storage units according to the storage instruction sent by the computing resource module. The second data processor is used for accessing part or all of the storage units according to the storage instruction sent by the computing resource module. The plurality of storage units comprise a plurality of double-channel storage units, and the backplane assembly comprises a plurality of double-control backplanes.

2. The in-memory computing server of claim 1, wherein, Each double-control backplane is connected with the first data processor and the second data processor respectively, and each double-control backplane is also connected with a plurality of double-channel storage units. The first data processor is used for accessing all of the double-channel storage units according to the storage instruction sent by the computing resource module. The second data processor is used for accessing all of the double-channel storage units according to the storage instruction sent by the computing resource module. The plurality of storage units comprise a plurality of first single-channel storage units and a plurality of second single-channel storage units, and the backplane assembly comprises a plurality of first single-control backplanes and a plurality of second single-control backplanes.

3. The in-memory computing server of claim 1, wherein, Each first single-control backplane is connected with the first data processor, and each first single-control backplane is also connected with a plurality of first single-channel storage units; each second single-control backplane is connected with the second data processor, and each second single-control backplane is also connected with a plurality of second single-channel storage units. The first data processor is used for accessing all of the first single-channel storage units according to the storage instruction sent by the computing resource module. The second data processor is used for accessing all of the second single-channel storage units according to the storage instruction sent by the computing resource module. The plurality of storage units comprise a plurality of first single-channel storage units, a plurality of second single-channel storage units and a plurality of double-channel storage units, and the backplane assembly comprises a plurality of first single-control backplanes, a plurality of second single-control backplanes and a plurality of double-control backplanes.

4. The in-memory computing server of claim 1, wherein, Each first single-control backplane is connected with the first data processor, and each first single-control backplane is also connected with a plurality of first single-channel storage units; each second single-control backplane is connected with the second data processor, and each second single-control backplane is also connected with a plurality of second single-channel storage units; and each double-control backplane is connected with the first data processor and the second data processor respectively, and each double-control backplane is also connected with a plurality of double-channel storage units. ​ The first data processor is configured to access all the first single-channel storage units and all the double-channel storage units according to storage instructions sent by the computing resource module. The second data processor is configured to access all the second single-channel storage units and all the double-channel storage units according to storage instructions sent by the computing resource module. 5.The in-memory computing server of claim 1, wherein, The computing resource module comprises a mainboard, a central processing unit, a switch and a plurality of first graphic processing units arranged on the mainboard. The plurality of first graphic processing units are connected with the switch, and the switch is further connected with the central processing unit. 6.The in-memory computing server of claim 1, wherein, The first data processor and the second data processor are pluggably connected with the mainboard through PCIE links. The storage resource module further comprises a first power supply and a second power supply.

7. The in-memory computing server of claim 1, wherein, The first power supply is connected with the first data processor, the second data processor and the backboard assembly respectively. The storage resource module further comprises a second graphic processing unit and a third graphic processing unit. The first data processor is further connected with the second graphic processing unit, and the second data processor is further connected with the third graphic processing unit. The first data processor is further configured to access part or all of the storage units according to storage instructions sent by the second graphic processing unit. 8.The server of claim 7, wherein, The second data processor is further configured to access part or all of the storage units according to storage instructions sent by the third graphic processing unit. The first data processor is connected with the computing resource module, the second graphic processing unit and the backboard assembly through PCIE links respectively. 9.The in-memory computing server of claim 1, wherein, The second data processor is connected with the computing resource module, the third graphic processing unit and the backboard assembly through PCIE links respectively.

10. A data center, characterized by, The storage unit is a CXL storage device or an SSD. The data center comprises the storage-computing integrated server according to any one of claims 1-9.

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