Image acquisition system and camera shooting equipment

Abstract

The utility model provides an image acquisition system and a camera device, and the image acquisition system comprises a trinocular camera group which is used for acquiring images; the trinocular camera group comprises three cameras; the data cache circuit is used for storing images acquired by the trinocular camera unit; the FPGA main control circuit is used for storing images acquired by the trinocular camera unit into a data cache circuit, processing the images, outputting the processed images to an upper computer and outputting light source control signals; the light source control circuit is used for driving the light-emitting device to emit light. According to the utility model, the FPGA master control circuit is used as a control core of the trinocular camera and is combined with the data cache circuit, so that the image data processing speed of the trinocular camera is improved, low-delay data processing and low energy consumption are realized, and meanwhile, the requirement of high storage space is met. Meanwhile, the camera is provided with the light source control circuit, so that an auxiliary light source can be provided for the camera at night or in a dark environment, and the camera can capture clearer images.

Description

TECHNICAL FIELD

[0001] The utility model relates to image acquisition technical field, especially relate to an image acquisition system and camera equipment. BACKGROUND

[0002] With the rapid progress of virtual technology, its use in the sports field is more and more extensive, especially in the simulation of ball games, which has shown extraordinary value. At present, the speed, trajectory route, etc. of the whole ball can be simulated by capturing the initial motion of the real ball, calculating the subsequent motion by computer according to physics, so as to create a real ball game environment and use it in various virtual environments.

[0003] However, the traditional image acquisition system still has certain limitations in some aspects. For example, monocular cameras have poor recognition effect in complex environments, and in this background, three-camera cameras have emerged. However, due to the different structure of three-camera cameras and traditional monocular cameras, higher computing resources and storage space are required.

[0004] At present, most of the traditional data acquisition schemes use ARM (Advanced RISC Machine) or digital signal processors as the control core. When processing the massive data generated by the three-camera camera, it may encounter bottlenecks and cannot effectively meet the needs of high performance, real-time and low power consumption. Therefore, an image acquisition system that can meet the strong data processing capability and high storage space requirement of the three-camera camera is needed. UTILITY MODEL CONTENT

[0005] The main purpose of the utility model is to provide an image acquisition system and camera equipment, which aims to solve the problem that the traditional data acquisition scheme cannot meet the strong data processing capability and high storage space requirement of the three-camera camera.

[0006] In view of the above problems, the utility model provides an image acquisition system, which comprises:

[0007] A three-camera camera group is used for image acquisition; the three-camera camera group comprises three cameras;

[0008] A data cache circuit is used for storing the images collected by the three-camera camera group;

[0009] An FPGA master control circuit is connected with the three-camera camera group and the data cache circuit respectively, and is used for storing the images collected by the three-camera camera group in the data cache circuit, performing image processing on the images collected by the three-camera camera group and / or the images stored by the data cache circuit, and outputting to the upper computer and outputting the light source control signal;

[0010] A light source control circuit is connected with the output end of the FPGA master control circuit and the controlled end of the light emitting device respectively; the light source control circuit is used for driving the light emitting device to emit light according to the light source control signal sent by the FPGA master control circuit.

[0011] Optionally, the FPGA master control circuit comprises a logic control circuit, a cache control circuit, a camera control circuit and an external interface circuit which are electrically connected with the logic control circuit.

[0012] The logic control circuit is electrically connected with a data cache circuit through the cache control circuit.

[0013] The cache control circuit is used for reading data from the data cache circuit or writing data into the data cache circuit according to the instruction sent by the logic control circuit.

[0014] The logic control circuit is electrically connected with a three-eye camera group through the camera control circuit.

[0015] The camera control circuit is used for converting the image captured by the camera into a digital signal and transmitting the digital signal to the logic control circuit.

[0016] The logic control circuit is electrically connected with a light source control circuit through the external interface circuit.

[0017] Optionally, the camera control circuit is provided with three groups, and the input end of each group of the camera control circuit is electrically connected with one camera of the three-eye camera group.

[0018] Optionally, the FPGA master control circuit further comprises an Ethernet interface circuit, a storage circuit and a first power supply circuit which are electrically connected with the logic control circuit, and the Ethernet interface circuit is electrically connected with an on-camera position.

[0019] The Ethernet interface circuit is used for realizing data transmission between the logic control circuit and the on-camera position.

[0020] The first power supply circuit is used for supplying power to the FPGA master control circuit.

[0021] The storage circuit is used for storing the collected image.

[0022] Optionally, the storage circuit comprises a Flash storage circuit and an SD card storage circuit.

[0023] Optionally, the Ethernet interface circuit adopts a gigabit network interface chip.

[0024] Optionally, the data cache circuit adopts a DDR3-SDRAM storage chip, and the cache control circuit is a DDR3-SDRAM cache control circuit.

[0025] Optionally, the light source control circuit comprises a second power supply circuit, a light source master control circuit and a light source driving circuit, the second power supply circuit is electrically connected to the power input end of the light source master control circuit and the power input end of the light source driving circuit, and the output end of the light source master control circuit is electrically connected to the light source driving circuit.

[0026] The second power supply circuit is configured to supply power to the light source control circuit.

[0027] The light source master control circuit is configured to receive and respond to the signal sent by the FPGA master control circuit, and send corresponding instructions to the driving circuit according to the signal sent by the FPGA master control circuit.

[0028] The light source master control circuit is configured to receive and respond to the signal sent by the FPGA master control circuit, and send corresponding instructions to the driving circuit according to the signal sent by the FPGA master control circuit.

[0029] The light source driving circuit is configured to drive the light emitting device to emit light according to the instructions sent by the light source master control circuit.

[0030] Optionally, the light source driving circuit comprises a light board, and the light emitting device is arranged on the light board, and the output end of the light source driving circuit is electrically connected to the light board.

[0031] The utility model also proposes a kind of camera equipment, including the image acquisition system as above.

[0032] The utility model uses FPGA master control circuit as the control core of three cameras and combines data cache circuit, improves the image data processing speed of three cameras, realizes low-delay data processing and low-energy consumption, while meeting the demand of high storage space.At the same time, the utility model is provided with light source control circuit, can provide auxiliary light source for camera in night or light relatively dark environment, so that camera can capture more clear image. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, the following will briefly introduce the drawings needed to be used in embodiment or prior art description, obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained according to the structure shown in these drawings without creative labor.

[0034] Figure 1 It is the circuit framework drawing of the image acquisition system of the utility model;

[0035] Figure 2 It is the circuit framework drawing of an embodiment of the image acquisition system of the utility model.

[0036]

[0037] The purposes, functional features and advantages of the utility model will be further explained in combination with embodiments with reference to the drawings. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the utility model will be clearly and completely described below in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0039] It should be noted that if the embodiments of the utility model involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directional indications also change accordingly.

[0040] In addition, if the embodiments of the utility model involve descriptions of "first", "second", etc., the descriptions of "first", "second", etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first" and "second" can explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing throughout the text is that it includes three parallel schemes, taking "A and / or B" as an example, which includes A scheme, or B scheme, or A and B schemes. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the utility model.

[0041] The utility model provides a kind of image acquisition system, as shown in Figure 1 It includes:

[0042] Three cameras of three cameras of camera group 01, for collecting image;Three cameras of camera group 01 includes three cameras;

[0043] Data buffer circuit 02 is used to store the image collected by three cameras of camera group 01;

[0044] FPGA master control circuit 03 is connected with three cameras of camera group 01 and data buffer circuit 02 respectively, for storing the image collected by three cameras of camera group 01 in data buffer circuit 02, carrying out image processing to the image collected by three cameras of camera group 01 and / or the image stored in data buffer circuit 02, and outputting to host computer and outputting light source control signal;

[0045] The light source control circuit 04 is connected with the output end of the FPGA master control circuit 03 and the controlled end of the light emitting device respectively; the light source control circuit 04 is used for driving the light emitting device to emit light according to the light source control signal sent by the FPGA master control circuit 03.

[0046] More specifically, compared with traditional monocular cameras, three-camera systems have more advantages in sports field virtual technology. Through the cooperative work of multiple cameras, three-camera systems can capture more comprehensive and three-dimensional scene information, effectively solving the problem of poor recognition effect of monocular cameras in complex environments.

[0047] At the same time, three-camera systems can provide image data of multiple perspectives, providing more abundant information sources for subsequent host computer simulation and data analysis. Based on the data captured by the three-camera system, the host computer can more accurately simulate the subsequent motion trajectory and speed of the ball, thereby improving the accuracy and authenticity of the simulation.

[0048] Although three-camera systems have significant advantages in sports field virtual technology, the massive data generated by them also poses challenges to data processing. The amount of data generated by three-camera systems is much larger than that of monocular cameras, so higher computing resources are needed to process these data. In order to store the massive data generated by three-camera systems, larger storage space is needed. In sports field virtual technology, the real-time requirement for data is very high.

[0049] To this end, the utility model provides an image acquisition system and a camera equipment, which aims to solve the problem that the traditional data acquisition scheme cannot meet the strong data processing capability and high storage space requirement of three-camera systems.

[0050] Among them, the image acquisition system includes a three-camera system 01, the camera includes a lens and an image sensor, the lens is to converge light to the image sensor, the image sensor surface has several hundred or several million photodiodes, the photodiode will have photoelectric effect after being irradiated by light, and the light signal is converted into an electrical signal.

[0051] The utility model adopts CMOS (complementary metal oxide semiconductor) image sensor, which has the characteristics of high resolution, global shutter, high sensitivity, etc. The three-camera system 01 includes three cameras, each camera has different focal length and field of view, so as to capture more abundant scene information. After the three-camera system 01 collects image data, it outputs the image data to the circuit for data processing.

[0052] The image acquisition system further includes a data cache circuit 02 and an FPGA master control circuit 03. In order to solve the demand of three-camera systems for high performance, real-time and low power consumption, the utility model adopts the FPGA master control circuit 03 as the control core.

[0053] FPGA (Field-Programmable Gate Array), also known as field programmable gate array, is a kind of semi-custom circuit, which can be configured by users after manufacturing. FPGA does not need to determine the specific circuit logic before manufacturing, but provides programmable logic blocks and reconfigurable interconnections, so that users can define the function of the circuit according to their own needs.

[0054] Its characteristics include: strong parallel processing capability, can handle multiple tasks at the same time, to meet the demand of three camera for high performance; Through hardware logic to realize image processing algorithm, without like software as waiting for CPU scheduling and execution, therefore has higher real-time performance; Can reduce power consumption by optimizing hardware logic and clock frequency.

[0055] And in the image acquisition and processing, FPGA can receive the raw image data output by the three camera, and carry out pretreatment such as denoising, color correction, etc.; Can realize image fusion algorithm, fuse the image data of three cameras, generate more comprehensive and detailed scene information; When a large amount of image data does not need to be processed, FPGA can enter low power consumption mode to save energy.

[0056] In the utility model for the image of three camera group 01 collection is stored in data buffer circuit 02, three camera group 01 collection image and / or data buffer circuit 02 storage image carries out image processing, and exports to host computer and exports light source control signal.

[0057] At the same time, in order to solve the demand of three camera for high storage space, the utility model adopts FPGA main control circuit 03 in combination with data buffer circuit 02, and data buffer circuit 02 provides a buffer before data is processed or transmitted. When FPGA main control circuit 03 needs to read image data, it will first check whether the required image data exists in data buffer circuit 02, if the image data exists in data buffer circuit 02, FPGA main control circuit 03 can access these data immediately without waiting to read from its own storage space.

[0058] If the image data is not in data buffer circuit 02, FPGA main control circuit 03 must read the image data from its own storage space and store it in data buffer circuit 02 for future use. By buffering image data through data buffer circuit 02, the system can access frequently used or recently used data faster without reading from slower own storage space every time.

[0059] The data cache circuit 02 can be implemented by SDRAM, and the SDRAM comprises a dual-port RAM structure, the dual-port RAM has two sets of completely independent data lines, address lines and read-write control lines, and allows two independent systems to simultaneously perform random access to the memory.

[0060] The image acquisition system of the utility model includes light source control circuit 04, for according to FPGA main control circuit 03 sent light source control signal, drive light emitting device light. Light source control circuit 04 needs including control circuit and drive circuit, control circuit is used to receive the signal of FPGA main control circuit 03, and sends the signal that needs drive light emitting device to drive circuit, drive circuit receives the signal of control circuit after, provide stable current or voltage output, and adjust the brightness of light emitting device etc.

[0061] The utility model adopts FPGA main control circuit 03 as the control core of three eye camera and combines data cache circuit 02, improves the image data processing speed of three eye camera, realizes low delay data processing and low energy consumption, and meets the demand of high storage space.Simultaneously, the utility model is equipped with light source control circuit 04, can provide auxiliary light source for camera in night or light relatively dark environment, makes camera can capture more clear image.

[0062] In an embodiment, as shown in Figure 2 The FPGA main control circuit 03 comprises a logic control circuit, a cache control circuit, a camera control circuit and an external interface circuit electrically connected with the logic control circuit.

[0063] The logic control circuit is the core part of the system, is responsible for processing and controlling various input signals to generate the required output signal.It realizes the control and processing of input signal through logic gate circuit and flip-flop, and outputs the signal meeting the requirement, and utilizes controller and timer and other elements to realize the accurate control of system time sequence, ensures that each part of the system works according to the predetermined order and time interval.

[0064] The logic control circuit is electrically connected with the data cache circuit 02 through the cache control circuit; the cache control circuit is used for reading data from the data cache circuit 02 or writing data into the data cache circuit 02 according to the instruction issued by the logic control circuit. The cache control circuit is a key part connecting the logic control circuit and the data cache circuit 02, which temporarily stores the signal output by the logic control circuit in the cache, so as to output to the data cache circuit 02 when needed.

[0065] The logic control circuit is electrically connected with the three-camera group 01 through the camera control circuit; the camera control circuit is used for converting the image captured by the camera into a digital signal and transmitting it to the logic control circuit. The image captured by the camera exists in the form of an analog signal, which contains the brightness, color and other information of the image. The analog-digital converter in the camera control circuit is responsible for converting these analog signals into digital signals, and the converted digital signals are transmitted to the logic control circuit, thereby realizing the digitization and intelligent processing of the image.

[0066] The logic control circuit is electrically connected with the light source control circuit 04 through the external interface circuit. The output signal of the logic control circuit is transmitted to the light source control circuit 04 through the external interface circuit, and then the light source control circuit 04 receives the control signal from the external interface circuit and drives the light emitting device to work. It is worth noting that necessary buffering and driving capability is provided in the signal transmission process to ensure the integrity and reliability of the signal.

[0067] In an embodiment, the camera control circuit is provided with three groups, and the input end of each group of camera control circuit is electrically connected with one camera of the three-camera group 01. The three groups of camera control circuits mean that the system can process image data from three different cameras, can simultaneously receive and process images captured by three cameras at different angles, different fields of view or different spectra, improve the efficiency of image acquisition and processing, and at the same time help to reduce processing delay and improve the real-time response capability of the system

[0068] In an embodiment, the FPGA master control circuit 03 further comprises an Ethernet interface circuit, a storage circuit and a first power circuit electrically connected with the logic control circuit, and the Ethernet interface circuit is electrically connected with the on-machine position;

[0069] The Ethernet interface circuit is used for realizing data transmission between the logic control circuit and the on-machine position; the Ethernet interface circuit supports high-speed and stable data transmission, ensuring smooth communication between the logic control circuit and the on-machine position. At the same time, the Ethernet interface circuit supports multiple network protocols such as TCP / IP, which enables the system to communicate with different types of network devices.

[0070] The first power supply circuit is used to supply power to the FPGA master control circuit 03; the first power supply circuit can provide stable and reliable power output, ensuring that the FPGA master control circuit 03 can work normally. The first power supply circuit should include multiple voltage conversion circuits to obtain multiple different voltages to meet the power supply needs of multiple circuits in the FPGA master control circuit 03.

[0071] The storage circuit is used to store the collected images. The storage circuit can accommodate a large amount of image data, ensuring that the system can continuously and uninterruptedly collect and store images. It usually uses high-speed and large-capacity storage to meet the system's demand for storage speed and capacity. The storage circuit supports high-speed data read and write operations to ensure that image data can be read and written in a timely manner. It is connected to the logic control circuit through appropriate interfaces (such as parallel bus, serial communication, etc.) to realize data transmission and exchange.

[0072] In an embodiment, the storage circuit includes a Flash storage circuit and an SD card storage circuit.

[0073] Flash memory is a non-volatile memory that can retain stored data without power supply, suitable for scenarios that require long-term data storage. At the same time, it allows multiple erasing and reprogramming of data, with high flexibility, suitable for the image acquisition system of the three-camera camera of the present embodiment.

[0074] The data read and write of the SD storage card is based on bytes, organized into blocks and sectors, and supports write protection function. Its pin design allows dynamic configuration of the number of data lines to balance hardware cost and performance. In addition, the SD bus allows dynamic configuration of the number of data lines, balancing hardware overhead and system performance.

[0075] In an embodiment, the Ethernet interface circuit uses a Gigabit Network Interface Chip. The Gigabit Network Interface Chip is an integrated circuit specially used for Ethernet communication, which supports a data transmission rate of up to 1000Mbps (1Gbps). This chip is usually integrated in network cards, switches, routers and other network devices, and is a key component for high-speed network communication.

[0076] In one embodiment, the data cache circuit 02 uses a DDR3-SDRAM memory chip, and the cache control circuit is a DDR3-SDRAM cache control circuit. DDR3-SDRAM (Double Data Rate 3 Synchronous Dynamic Random Access Memory) is a third-generation double data rate synchronous dynamic random access memory. It has several improvements over DDR2, and features higher data transfer rates, lower power consumption, and better compatibility.

[0077] During a read operation, the cache control circuit sends a read command and address signal to the DDR3-SDRAM, and then waits for the data to be read and transmitted to the output. During a write operation, the cache control circuit sends the data to be written and the address signal to the DDR3-SDRAM, and waits for the write operation to complete.

[0078] In one embodiment, such as Figure 2 As shown, the light source control circuit 04 includes a second power supply circuit, a light source main control circuit, and a light source driving circuit. The second light source circuit is electrically connected to the power input terminal of the light source main control circuit and the power input terminal of the light source driving circuit. The output terminal of the light source main control circuit is electrically connected to the light source driving circuit.

[0079] Light-emitting devices typically require specific voltages and currents to function properly and emit stable light. These electrical characteristics may not match the output characteristics of an FPGA's I / O pins. FPGA I / O pins are generally designed for digital signal transmission, not for directly driving the current required by the LED; therefore, a light source control circuit (04) is needed to drive the light-emitting device.

[0080] The second power supply circuit supplies power to the light source control circuit 04, ensuring its proper operation. This second power supply circuit includes multiple power supply circuits to provide power at different voltage levels or with varying characteristics to the light source main control circuit and the light source drive circuit.

[0081] The light source main control circuit receives and responds to signals sent by the FPGA main control circuit 03, and issues corresponding instructions to the drive circuit based on these signals. The light source main control circuit receives signals from the FPGA main control circuit 03 and, based on the signal content, issues instructions to the light source drive circuit to control the brightness, color, and flicker mode of the light source. The light source main control circuit needs to be able to quickly respond to signals from the FPGA main control circuit 03 and issue different instructions based on different signals from the FPGA main control circuit 03.

[0082] The light source driving circuit is used for driving the light emitting device to emit light according to the instruction sent by the light source master control circuit.

[0083] In an embodiment, the image acquisition system further comprises a lamp plate 05, and the light emitting device is arranged on the lamp plate 05, and an output end of the light source driving circuit is electrically connected to the lamp plate 05. The light emitting device is arranged on the lamp plate 05, so that heat generated by the light emitting device during operation does not affect the normal operation of the FPGA master control circuit 03 or the light source control circuit 04.

[0084] The utility model further provides a kind of camera equipment, including the image acquisition system as above. For the virtual technology in sports field, the subsequent motion track and speed of ball are simulated more accurately by the cooperation of multiple cameras, so as to improve the precision and authenticity of simulation.

[0085] The above embodiments are only preferred embodiments of the utility model, and do not limit the patent scope of the utility model, and any equivalent structure or equivalent process transformation using the contents of the utility model specification and drawings, or direct or indirect application in other related technical fields are also included in the patent protection scope of the utility model.

Claims

1. An image acquisition system, characterized by, The application relates to a three-camera group for image acquisition; the three-camera group comprises three cameras. A data buffer circuit is arranged for storing images acquired by the three-camera group. An FPGA master control circuit is connected with the three-camera group and the data buffer circuit respectively, and is arranged for storing images acquired by the three-camera group in the data buffer circuit, performing image processing on the images acquired by the three-camera group and / or the images stored in the data buffer circuit, and outputting the images to an upper computer and outputting a light source control signal. A light source control circuit is connected with the output end of the FPGA master control circuit and the controlled end of a light emitting device respectively; the light source control circuit is arranged for driving the light emitting device to emit light according to the light source control signal sent by the FPGA master control circuit. The FPGA master control circuit comprises a logic control circuit, a buffer control circuit, a camera control circuit and an external interface circuit which are electrically connected with the logic control circuit.

2. The image acquisition system of claim 1, wherein, The logic control circuit is electrically connected with the data buffer circuit through the buffer control circuit. The buffer control circuit is arranged for reading data from the data buffer circuit or writing data into the data buffer circuit according to the instruction sent by the logic control circuit. The logic control circuit is electrically connected with the three-camera group through the camera control circuit. The camera control circuit is arranged for converting the images captured by the cameras into digital signals and transmitting the digital signals to the logic control circuit. The logic control circuit is electrically connected with the light source control circuit through the external interface circuit. The camera control circuit is provided with three groups, and the input end of each group of the camera control circuit is electrically connected with one camera of the three-camera group.

3. The image acquisition system of claim 2, wherein, The FPGA master control circuit further comprises an Ethernet interface circuit, a storage circuit and a first power supply circuit which are electrically connected with the logic control circuit, and the Ethernet interface circuit is electrically connected with the upper computer.

4. The image acquisition system of claim 2, wherein, The Ethernet interface circuit is arranged for realizing data transmission between the logic control circuit and the upper computer. The first power supply circuit is arranged for supplying power to the FPGA master control circuit. The storage circuit is arranged for storing the acquired images. The storage circuit comprises a Flash storage circuit and an SD card storage circuit.

5. The image acquisition system of claim 4, wherein, The Ethernet interface circuit adopts a gigabit network interface chip.

6. The image acquisition system of claim 4, wherein, The data buffer circuit adopts a DDR3-SDRAM storage chip, and the buffer control circuit is a DDR3-SDRAM buffer control circuit.

7. The image acquisition system of any of claims 2-6, wherein, The light source control circuit comprises a second power supply circuit, a light source master control circuit and a light source driving circuit, the second power supply circuit is electrically connected with the power input end of the light source master control circuit and the power input end of the light source driving circuit, and the output end of the light source master control circuit is electrically connected with the light source driving circuit.

8. The image acquisition system of claim 1, wherein, The second power supply circuit is arranged for supplying power to the light source control circuit. The light source master control circuit is arranged for receiving and responding to the signal sent by the FPGA master control circuit, and sending corresponding instructions to the driving circuit according to the signal sent by the FPGA master control circuit. The light source driving circuit is arranged for driving the light emitting device to emit light according to the instruction sent by the light source master control circuit. A lamp plate is further arranged, the light emitting device is arranged on the lamp plate, and the output end of the light source driving circuit is electrically connected with the lamp plate. ​ 9. The image acquisition system of claim 8, wherein, ​ 10. An image pickup apparatus characterized by comprising: An image acquisition system comprising the image acquisition system according to any one of claims 1 to 9.

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