Semiconductor device structure

Abstract

The embodiment of the utility model provides a semiconductor device structure. The semiconductor device structure includes a first gate electrode layer disposed over the substrate, and the first gate electrode layer extends in a first direction. The structure also includes a second gate electrode layer disposed over the substrate, and the second gate electrode layer extends in the first direction. The structure also includes a first source / drain region disposed on a first side of the first gate electrode layer, and the first source / drain region has a first constant width along a second direction substantially perpendicular to the first direction. The structure also includes a second source / drain region disposed on a second side of the first gate electrode layer opposite the first side, and the second source / drain region has a varying width along the second direction.

Description

Technical Field

[0001] This utility model relates to a semiconductor device structure, and more particularly to a semiconductor device structure with a hard mask fin structure having a convex geometry. Background Technology

[0002] The semiconductor integrated circuit (IC) industry is experiencing exponential growth. Technological advancements in IC materials and design have led to multiple IC generations, each with smaller and more complex circuits than the previous one. During IC development, the geometric dimensions achievable through manufacturing processes (e.g., the smallest component (or line)) decrease, while functional density (e.g., the number of connected components per chip area) typically increases. This miniaturization offers advantages through increased production efficiency and reduced costs. However, this miniaturization also increases the complexity of IC processes and manufacturing.

[0003] Therefore, improvements are needed in IC manufacturing processes. Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor device structure to solve at least one of the above-mentioned problems.

[0005] This invention provides a semiconductor device structure. The semiconductor device structure includes a first gate electrode layer, a second gate electrode layer, a first source / drain region, and a second source / drain region. The first gate electrode layer is disposed above a substrate. The first gate electrode layer extends in a first direction. The second gate electrode layer is disposed above the substrate. The second gate electrode layer extends in the first direction. The first source / drain region is disposed on a first side of the first gate electrode layer. The first source / drain region has a first constant width along a second direction substantially perpendicular to the first direction. The second source / drain region is disposed on a second side of the first gate electrode layer opposite to the first side. The second source / drain region has a varying width along the second direction.

[0006] According to one embodiment of the present invention, the second source / drain region is disposed on a first side of the second gate electrode layer.

[0007] According to one embodiment of the present invention, a third source / drain region is further provided on a second side of the second gate electrode layer opposite to the first side.

[0008] According to one embodiment of the present invention, the third source / drain region has a second constant width along the second direction.

[0009] According to one embodiment of the present invention, the second constant width is approximately greater than the first constant width.

[0010] According to one embodiment of the present invention, the second source / drain region includes a first portion on the second side of the first gate electrode layer, a second portion on the first side of the second gate electrode layer, and a transition portion between the first portion and the second portion.

[0011] According to one embodiment of the present invention, the transition portion of the second source / drain region has a linearly inclined taper.

[0012] According to one embodiment of the present invention, the first portion of the second source / drain region has the first constant width, and the second portion of the second source / drain region has the second constant width.

[0013] According to one embodiment of the present invention, the transition portion of the second source / drain region intersects the first portion of the second source / drain region at an obtuse angle.

[0014] According to one embodiment of the present invention, the transition portion of the second source / drain region intersects with the second portion of the second source / drain region at an acute angle. Attached Figure Description

[0015] This utility model embodiment can be understood in more detail by reading the following detailed description and examples in conjunction with the corresponding drawings. It should be noted that, in accordance with industry standard practice, the various feature components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various feature components can be arbitrarily increased or decreased.

[0016] Figure 1 , Figure 2A , Figure 2B , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14A , Figure 14B , Figure 15 , Figure 16A , Figure 16BThis is a schematic diagram of various sites for manufacturing a semiconductor device structure according to some embodiments.

[0017] Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E This is a top view of various types of jug geometry according to some embodiments.

[0018] The attached figures are labeled as follows:

[0019] 100: Semiconductor Device Structure

[0020] 101:Substrate

[0021] 104: Semiconductor layer stacking

[0022] 106: First semiconductor layer

[0023] 108: Second semiconductor layer

[0024] 109: Hard Mask

[0025] 110: Oxide layer

[0026] 111: Nitride layer

[0027] 113: First photoresist layer

[0028] 115: Hard mask fin structure

[0029] 121: Hard mask trench

[0030] 123: Second photoresist layer

[0031] 115': Hard mask fin structure

[0032] 121': Modified hard mask trench

[0033] w1: First width

[0034] w2: Second width

[0035] FP: Part 1

[0036] TP: Transition section

[0037] SP: Part Two

[0038] 114: Trench

[0039] 116: Well section

[0040] a1: angle

[0041] a2: Angle

[0042] 117: Insulation layer

[0043] 130: Sacrificial gate structure

[0044] 132: Sacrificial gate dielectric layer

[0045] 134: Sacrificial gate electrode layer

[0046] 135: Oxide layer

[0047] 136: Mask layer

[0048] 137: Nitride layer

[0049] 138: Spacer layer

[0050] 140: Spacer

[0051] 140a: Part 1

[0052] 140b: Part Two

[0053] 116t: Top surface

[0054] 116t1: Top surface

[0055] 117t: Top surface

[0056] 144: Dielectric spacer

[0057] 146: Source / Drain Region

[0058] 162: Contact Etching Stop Layer

[0059] 163: Interlayer dielectric layer

[0060] w3: Third width

[0061] w4: Fourth width

[0062] FP': Part 1

[0063] TP': Transition section

[0064] SP': Part Two

[0065] a3: Angle

[0066] a4: Angle

[0067] 168: Interface Layer

[0068] 170: Gate dielectric layer

[0069] 172: Gate electrode layer

[0070] 174: Gate Structure

[0071] 200, 210, 220, 230, 240: Semiconductor device structure

[0072] 202,212,222,232,242: Hard mask fin structure

[0073] 204, 214, 224, 234, 244: Photoresist

[0074] 206: Symmetrical convex part

[0075] 216: Internal convex part

[0076] 226:External convex part

[0077] 236: Asymmetrical convex part

[0078] 246: Interlaced protrusions Detailed Implementation

[0079] This utility model provides many different embodiments or examples to implement the various features of this invention. The following disclosure describes specific embodiments of the various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this utility model describes a first feature formed on or above a second feature, it means that it may include embodiments where the first feature and the second feature are in direct contact, or it may include embodiments where an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the same reference numerals and / or markings may be used repeatedly in different embodiments of this utility model below. These repetitions are for simplification and clarity and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0080] Furthermore, spatially related terms, such as "below," "below," "lower," "above," "above," "top," "higher," and similar terms, are used to facilitate the description of the relationship between one element or feature and another element(s) in the illustration. In addition to the orientations shown in the accompanying drawings, these spatially related terms are intended to encompass different orientations of the device in use or operation. Furthermore, the device may be rotated to different orientations (90 degrees or other orientations), and the spatially related terms used herein can be interpreted in the same way.

[0081] Although the embodiments of this invention are discussed in relation to nanostructured channel FETs, such as gate all around (GAA) FETs (e.g., horizontal gate all around (HGAA) FETs or vertical gate all around (HGAA) FETs), While this invention pertains to Gate All-Around (GAA), some aspects of its implementation can be used in other processes and / or other devices, such as FinFETs and other suitable devices. Those skilled in the art will readily understand that other modifications are contemplated within the scope of this invention. In the case of a Gate All-Around transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including dual patterning or multiple patterning processes) can be used to pattern the structure. Generally, dual patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the production of patterns with a smaller pitch than that achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0082] This invention provides a semiconductor device structure and a method for forming the same. Problems related to the width variation of active regions (e.g., fin structures) exist in the semiconductor IC industry. In some embodiments, the term "active region" discussed herein is also referred to as an oxide definition (OD) region. For example, the OD width transition along the longitudinal direction (which may also be referred to herein as "OD jog rounding") is too gradual and not sharp enough. If the gradual transition of the OD width extends from one gate to an adjacent gate, the sloping portion may cause dielectric spacer peeling, potentially leading to gate leakage. Furthermore, the gradual transition of the OD width creates a non-active transition region that cannot be used for active features (e.g., by continuous poly on oxide definition (CPODE) processes, which remove portions of the gradual transition with the OD width). Additionally, the OD jog rounding can limit flexible wafer widths through design technology co-optimization (DTCO). The chamfering of OD (Obstacle Development) bumps can be limited by photolithography and etching processes (e.g., low resolution of photolithography and / or plasma damage leading to pattern distortion). For example, photoresist curing and / or reflow can reduce line width roughness (LWR) and / or line edge roughness (LER). These issues are characteristic of methods that simultaneously define OD width and bumps (e.g., using a single photoresist) (which may also be referred to herein as the "bump-first method").

[0083] In some embodiments of this invention, the OD bump chamfer can match the miniaturization of the transistor gate pitch or contacted polypitch (CPP), a measurement of the pitch between two parallel gates, as described in more detail below. In other words, as the CPP is miniaturized (reduced), the OD bump chamfer can be reduced by a corresponding amount, allowing the OD bump to fit between two adjacent gates. The area of ​​the active region increases without the need to cut the transition region (e.g., via CPODE). Furthermore, improved control of the OD width in a specific region can reduce transistor power consumption. Additionally, the fin portion spanning the active region can be straight and non-tilted, preventing dielectric spacer stripping and gate leakage problems. The aforementioned benefits are achieved through the semiconductor device structures and methods described below. For example, methods that define the OD width and bump at different sites in the manufacturing process (e.g., using multiple photoresists) (also referred to herein as the "jog last approach") can solve the various problems described above.

[0084] Figures 1 to 16B An exemplary process for manufacturing a semiconductor device structure 100 is shown according to an embodiment of the present invention. It should be understood that for additional embodiments of the method, [further details may be needed]. Figures 1 to 16B Additional operations are provided before, during, and after the processes shown, and some of the operations described below can be substituted or eliminated. The order of operations / processes is not restricted and can be interchanged.

[0085] Figure 1 This is a schematic diagram of a site for manufacturing a semiconductor device structure 100 according to some embodiments. For example... Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials such as (but not limited to) silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. On one hand, the insulating layer is an oxygen-containing layer.

[0086] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0087] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels, such as nanostructured channel FETs, in multi-gate devices. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0088] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0089] The first semiconductor layer 106, or portions thereof, may form nanostructured channels of the semiconductor device structure 100 in subsequent process sites. The term "nanostructure" is used herein to refer to any material portion having nanoscale or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of this portion. Thus, the term refers to elongated material portions with circular or substantially circular cross-sections, as well as beam or bar material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0090] Each first semiconductor layer 106 may have a thickness in the range of about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range of about 2 nm to about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged as follows... Figure 1 The alternating arrangement shown is for illustrative purposes and is not intended to limit the scope beyond what is specifically described in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100. Figure 1 As shown, a hard mask 109 is formed on the topmost first semiconductor layer 106. For example, the hard mask 109 may include an oxide layer 110 formed on the topmost first semiconductor layer 106 and a nitride layer 111 formed on the oxide layer 110. The oxide layer 110 may be silicon oxide and may have different etch selectivity compared to the nitride layer 111. The nitride layer 111 may include any suitable nitride material, such as silicon nitride. In some other embodiments, the hard mask 109 may include one or more layers formed of silicon, nitride, oxide, dielectric, metal, metal oxide, other suitable materials, and / or combinations thereof.

[0091] Figure 2A and Figure 2B Individually, these are top and side views of another site of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 2A and Figure 2B In this process, a first photoresist layer 113 is formed over a hard mask 109 (e.g., over a nitride layer 111 of the hard mask 109). The first photoresist layer 113 is configured (e.g., by photolithography) to define a first pattern to be transferred to the hard mask 109 (e.g., defining the width of the hard mask 109 corresponding to an OD region in the Y direction, without defining any protrusions of the hard mask 109 (e.g., variations in width)). The photolithography process may include forming the first photoresist layer 113 over the hard mask 109, exposing the first photoresist layer 113 to the pattern, performing a post-exposure baking process, and developing the first photoresist layer 113 to form a photomask element including the first photoresist layer 113. In some embodiments, an electron beam lithography process may be used to pattern the first photoresist layer 113 to form the mask element. Figure 2A and Figure 2B As shown, the first photoresist layer 113 is a patterned photoresist layer or a patterned mask, which is defined to correspond to the openings of a plurality of portions of the hard mask 109 to be etched.

[0092] Figure 3 This is a schematic diagram of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 3 In the first step, the first pattern of the first photoresist layer 113 is transferred to the hard mask 109 to define the hard mask fin structure 115. The hard mask fin structure 115 can be constructed using photolithography (...). Figure 2A and Figure 2B The hard mask 106 is formed through multiple patterning operations involving etching and etching processes. In some embodiments, the etching process may include etching both the oxide layer 110 and the nitride layer 111 to expose the topmost first semiconductor layer 106. In some other embodiments, the etching process may include etching only the nitride layer 111, such that the oxide layer 110 is exposed and the topmost first semiconductor layer 106 is not exposed. The etching process includes etching or trimming unprotected portions of the hard mask 109 to define the hard mask fin structure 115 separated by hard mask trenches 121. Figure 3 As shown, the hard mask fin structure 115 and the hard mask trench 121 extend longitudinally in the X direction. In some embodiments, the etching process described herein may include plasma etching, dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes or combinations thereof. When using electro-etching, the plasma type may include inductively coupled plasma (ICP), capacitively coupled plasma (CCP), electron cyclotron resonance (ECR) plasma, other suitable plasma types, and / or combinations thereof. In some embodiments, the etching gas may include fluorine, chlorine, bromine, other suitable etching gases, and / or combinations thereof. In some embodiments, the etching process temperature may be in the range of about 50°C to about 350°C. In some embodiments, the etching process pressure may be in the range of about 1 mTorr to about 10 Torr. In some embodiments, the source power may be in the range of about 50 W to about 1200 W. In some embodiments, the source power frequency may be in the range of about 13.56 MHz or greater. In some embodiments, the bias power can be in the range of about 0V to about 1200V. In some embodiments, the bias power frequency can be in the range of about 13.56MHz or less. The first photoresist layer 113 is removed after the hard mask fin structure 115 is formed.

[0093] Figure 4A and Figure 4B Individually, these are top and side views of another site of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 4A and Figure 4B In this process, a second photoresist layer 123 is formed above the hard mask fin structure 115 and above the hard mask trench 121 (e.g., above the top surface of the hard mask 109 of the hard mask fin structure 115 and above the topmost first semiconductor layer 106 exposed by the etching process that forms the hard mask trench 121, such as...). Figure 3 (As shown). The second photoresist layer 123 is configured (e.g., by photolithography) to define a second pattern (e.g., to define a protrusion (e.g., a variation in the width of the hard mask 109 in the Y direction)) to be transferred to the remaining portion of the hard mask 109. The second pattern depicts a first portion of the hard mask fin structure 115 to be etched and a second portion of the hard mask fin structure 115 not to be etched. The photolithography process may include forming the second photoresist layer 123 over the hard mask fin structure 115, exposing the second photoresist layer 123 to the pattern, performing a post-exposure baking process, and developing the second photoresist layer 123 to form a mask element including the second photoresist layer 123. In some embodiments, an electron beam lithography process may be used to perform patterning of the second photoresist layer 123 to form the mask element. Figure 4A and Figure 4B As shown, the second photoresist layer 123 is a patterned photoresist layer or a patterned mask, the definition of which corresponds to the opening of the hard mask fin structure 115 to be etched.

[0094] Figures 5A to 5C Individually, these are schematic diagrams, top views, and side views of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figures 5A to 5C In the process, the second pattern of the second photoresist layer 123 is transferred to the hard mask fin structure 115 to form the modified hard mask fin structure 115'. Photolithography can be used to... Figure 4A and Figure 4B The modified hard mask fin structure 115' is formed by multiple patterning operations of etching and etching processes. The etching process may include dry etching, wet etching, reactive ion etching, and / or other suitable processes or combinations thereof. In some embodiments, the etching process is a selective etching process that reduces the size of a first exposed portion of the hard mask fin structure 115, while the second photoresist layer 123 and the first semiconductor layer 106 are largely unaffected. For example, the etching process reduces the height in the Z direction and the width in the Y direction of the portion of the hard mask structure 115 not covered by the second photoresist layer 123. After forming the modified hard mask fin structure 115', the second photoresist layer 123 is removed. The etching process forms modified hard mask trenches 121' to define the modified hard mask fin structure 115'. Figure 5BAs shown, the modified hard mask fin structure 115' includes a first portion FP defining a first width w1 and a second portion SP defining a second width w2 greater than the first width w1, with a transition portion TP between the first portion FP and the second portion SP. In some embodiments, the modified hard mask fin structure 115' has a varying width along the longitudinal direction (X direction), such as... Figure 5B As shown. In some embodiments, the second width w2 is not changed by etching of the first portion of the hard mask fin structure 115. In some embodiments, the difference between the first width w1 and the second width w2 (which may also be referred to herein as the “protrusion dimension”) can be in the range of about 1 nm to about 20 nm. A transition portion TP is configured to transition between the first width w1 and the second width w2, as described in more detail below. In some embodiments, the length of the transition portion TP (which may also be referred to herein as the “protrusion chamfer”) in the X direction can be less than 1 CPP, for example in the range of about 20 nm or less, for example about 0 nm to about 20 nm, for example about 0 nm to about 15 nm, for example about 0 nm to about 10 nm, for example about 0 nm to about 5 nm nanometers.

[0095] Figures 6A to 6C Individually, these are schematic diagrams, top views, and side views of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figures 6A to 6C In this configuration, multiple fin structures 112 are formed from a semiconductor layer stack 104 (e.g., a pattern / outline (top view) corresponding to a modified hard mask fin structure 115'). Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed by a substrate 101. The fin structures 112 can be formed by an etching process. The etching process can include dry etching, wet etching, reactive ion etching, and / or other suitable processes or combinations thereof. The etching process forms trenches 114 in unprotected areas, penetrating the semiconductor layer stack 104 and extending into the substrate 101, to define the plurality of fin structures 112 separated by the trenches 114. Figure 6A and Figure 6B As shown, the fin structure 112 and the groove 114 extend longitudinally in the X direction. In some embodiments, the fin structure 112 has a varying width along the longitudinal direction (X direction), such as... Figure 6A As shown. Figure 6BAs shown, the fin structure 112 has a shape corresponding to the modified hard mask fin structure 115'. For example, compared to the modified hard mask fin structure 115', the first portion FP of the fin structure 112 may have the same first width w1, and the second portion SP of the fin structure 112 may have the same second width w2. In some other embodiments, as a tolerance characteristic of the etching process, the widths of the first portion FP, the second portion SP, and the transition portion TP of the fin structure 112 may be slightly larger or slightly smaller than the corresponding widths of the modified hard mask fin structure 115'. Figure 6B As shown, the transition portion TP of the fin structure 112 may intersect the first portion FP at an angle a1 ranging from about 90 degrees to about 180 degrees, for example from about 140 degrees to about 170 degrees, or for example from about 150 degrees to about 160 degrees. Similarly, the transition portion TP of the fin structure 112 may intersect the second portion SP at an angle a2 ranging from about 0 degrees to about 90 degrees, for example from about 20 degrees to about 70 degrees, or for example from about 30 degrees to about 60 degrees. In some embodiments, angle a1 is an obtuse angle and angle a2 is an acute angle.

[0096] Figure 7A and Figure 7B Individually, these are schematic diagrams and top views of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 7A and Figure 7B In this process, insulating layer 117 is deposited in trenches 114 between adjacent fin structures 112. For example, insulating layer 117 can be shallow trench isolation (STI). Insulating layer 117 can be deposited above substrate 101. Insulating layer 117 can be deposited from bottom to top, such as... Figure 7A As shown. In some embodiments, the insulating layer 117 is deposited using a flowable chemical vapor deposition (FCVD) process. The insulating layer 117 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, plasma-enhanced oxide (PEOX), and / or any suitable dielectric material.

[0097] Figure 8A and Figure 8B Individually, these are schematic diagrams and top views of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 8A and Figure 8BIn this structure, one or more sacrificial gate structures 130 are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a first portion of the fin structure 112 and an insulating layer 117, while exposing an adjacent second portion.

[0098] like Figure 8A As shown, each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. In some embodiments, the mask layer 136 is a multilayer structure. For example, the mask layer 136 may include an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers to form the sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The first portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100.

[0099] like Figure 8B As shown, the sacrificial gate structure 130 extends longitudinally in the Y direction (perpendicular to the fin structure 112). For example, the first (e.g., left) and second (e.g., right) sacrificial gate structures 130 may span the transition portion TP of the fin structure 112 (e.g., individually disposed above the first portion FP and the second portion SP of the fin structure 112). In other words, the boundary of the transition portion TP of the fin structure 112 may be located in the space between the first and second sacrificial gate structures 130 without overlapping any portion of the sacrificial gate structure 130. In some embodiments, the fin structure is formed by the "jog first approach" as described above, and the length of the transition portion TP in the X direction is substantially longer than [missing information]. Figure 8B The length of the transition portion TP is shown. For example, the "protrusion-first method" can form a fin structure having a transition portion TP extending from one sacrificial gate structure 130 to an adjacent sacrificial gate structure 130. As a result, the dielectric spacer 144 formed ( Figure 13 The transition portion TP may be easily peeled off due to its sloping portion. Therefore, by using the "recessed method" described herein, the length of the transition portion TP in the X direction can be very small, for example, less than CPP, and the chance of the dielectric spacer 144 peeling off is greatly reduced.

[0100] Figure 9This is a schematic diagram of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 9 In this configuration, a spacer layer 138 is formed over (e.g., covering) the second portion of the sacrificial gate structure 130, the fin structure 112, and the second portion of the insulating layer 117. The spacer layer 138 may comprise one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. In some embodiments, the spacer layer 138 comprises two dielectric layers. In some embodiments, the spacer layer 138 is formed using a compliant process, such as atomic layer deposition (ALD). In some embodiments, the thickness of the spacer layer 138 ranges from about 2 nm to about 10 nm.

[0101] Figure 10 This is a schematic diagram of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 10 In this process, an anisotropic etching process is performed to remove the horizontal portion of the spacer layer 138. The anisotropic etching process can be a selective etching process that does not significantly affect the nitride layer 137, the first semiconductor layer 106, and the insulating layer 117. As a result, a second portion of the fin structure 112 is exposed, except for the area covered by the vertical portion of the spacer layer 138.

[0102] Figure 11 This is a schematic diagram of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 11 In this process, one or more etching processes are performed to recess the exposed second portion of the fin structure 112 not covered by the sacrificial gate structure 130 (and a plurality of portions of the spacer layer 138 formed on the sidewalls of the sacrificial gate structure 130), and to remove the plurality of portions of the spacer layer 138. In some embodiments, the portion of the spacer layer 138 formed on the sidewalls of the mask layer 136 may also be recessed. One or more etching processes may include dry etching, such as reactive ion etching, neutral beam etching (NBE), etc., and / or wet etching, such as using tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH). One or more etching processes form a spacer 140, which includes a first portion 140a formed on the sidewalls of the sacrificial gate electrode layer 134 and a second portion 140b formed on a second portion of the insulating layer 117. In some embodiments, one or more etching processes may also remove a plurality of portions of the second portion of the insulating layer 117, such as Figure 11As shown. As a result, after one or more etching processes, the top surface 117t of the second portion of the insulating layer 117 can be defined at a level generally lower than the top surface 116t1 of the well portion 116 outside the channel region (e.g., in the Z direction). In some embodiments, the top surface 116t1 can be defined at a level lower than the top surface 116t of the well portion 116 located below the sacrificial gate structure 130 (e.g., in the Z direction).

[0103] Figure 12 This is a schematic diagram of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 12 In this process, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 creates cavities between adjacent first semiconductor layers 106 above and below the second semiconductor layer 108. In some embodiments, multiple portions of the second semiconductor layer 108 are removed by a selective wet etching process. In embodiments where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as (but not limited to) ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0104] Figure 13 This is a schematic diagram of another site for manufacturing a semiconductor device structure 100 according to some embodiments. Figure 13 In the process of removing each second semiconductor layer 108 ( Figure 12 After the edge portion of the fin structure 112, a dielectric layer is deposited in the cavity to form dielectric spacers 144. Dielectric spacers 144 can be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. Dielectric spacers 144 can be formed by first forming a compliant dielectric layer using a compliant deposition process (e.g., ALD), followed by anisotropic etching to remove portions of the compliant dielectric layer other than the dielectric spacers 144. During the anisotropic etching process, a first semiconductor layer 106 protects the dielectric spacers 144 from etching. The remaining second semiconductor layer 108 capped between the dielectric spacers 144 along the X direction. The dielectric spacers 144 have a length along the Y direction and a width along the X direction. In some embodiments, the first portion FP of the fin structure 112... Figure 8B The length of the dielectric spacer 144 in the fin structure 112 is approximately smaller than that of the second part SP. Figure 8BThe length of the dielectric spacer 144 in the fin structure 112 is such that the width of the first portion FP of the fin structure 112 is approximately smaller than the width of the second portion SP of the fin structure 112. In some embodiments, by Figure 12 The process removes the same amount of edge portions from each of the second semiconductor layers 108, regardless of the location of the second semiconductor layer 108 (i.e., in the first portion FP or the second portion SP of the fin structure 112). As a result, the width of the dielectric spacer 144 located in the first portion FP of the fin structure 112 is approximately the same as the width of the dielectric spacer 144 located in the second portion SP of the fin structure 112. Therefore, in some embodiments, the dielectric spacer 144 has different aspect ratios depending on its location. The dielectric spacer 144 located in the first portion FP of the fin structure 112 has a first aspect ratio, and the dielectric spacer 144 located in the second portion SP of the fin structure 112 has a second aspect ratio that is approximately smaller than the first aspect ratio.

[0105] Figure 14A and Figure 14B Individually, these are schematic diagrams and top cross-sectional views of another site of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 14A and Figure 14B In this embodiment, the source / drain (S / D) region 146 is formed by the well portion 116 (e.g., formed on the corresponding top surface 116t1 of the well portion 116). The S / D region 146 can be grown vertically and horizontally to form facets that correspond to the crystal planes of the material of the well portion 116. In this invention, the source and drain regions are used interchangeably and their structures are substantially the same. Furthermore, depending on the context, the source / drain region can refer to the source or drain individually or collectively. The S / D region 146 can be made of one or more layers of Si, SiP, SiC, and SiCP for n-type FETs (NFETs) or Si, SiGe, and Ge for p-type FETs (PFETs). For PFETs, p-type dopants (e.g., boron (B)) can also be included in the S / D region 146. The S / D region 146 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0106] like Figure 14A and Figure 14BAs shown, a contact etch stop layer (CESL) 162 is compliantly formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of a first portion 140a of spacer 140 and is disposed on a second portion 140b of spacer 140 and the S / D region 146. CESL 162 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on CESL 162. The material of ILD layer 163 may comprise compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for ILD layer 163. ILD layer 163 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 163 is formed, the semiconductor device structure 100 may be subjected to heat treatment to anneal the ILD layer 163.

[0107] like Figure 14A As shown, a planarization process is performed to expose the sacrificial gate electrode layer 134. The planarization process can be any suitable process, such as a CMP process. The planarization process removes multiple portions of the ILD layer 163 and CESL 162 disposed on the sacrificial gate structure 130. The planarization process may also remove the mask layer 136.

[0108] like Figure 14B As shown, the S / D region 146 includes a shape corresponding to a corresponding well portion 116 of the fin structure 112 below the respective S / D region 146. For example, each of the S / D regions 146 located between the two sacrificial gate electrode layers 134 includes a first portion FP' having a third width w3 and a second portion SP' having a fourth width w4 greater than the third width w3, with a transition portion TP' between the first portion FP' and the second portion SP'. The transition portion TP' is configured to transition between the third width w3 and the fourth width w4. Due to the epitaxial growth pattern that is a feature of the S / D region 146, the transition portion TP' has a more gently sloping (e.g., approximately linear) taper or transition compared to the transition portion TP of the fin structure 112. For example, the transition portion TP' may intersect the first portion FP' at an angle a3 less than angle a1, and the transition portion TP' may intersect the second portion SP' at an angle a4 less than angle a2. In some embodiments, the ratio of a3 / a1 and the ratio of a4 / a2 may be in the range of about 0.5 to about 1, for example, about 0.7 to about 0.9.

[0109] like Figure 14B As shown, because the fin structure 112 has a varying width along the longitudinal direction (X direction), the S / D regions 146 have different shapes depending on their positions. For example, the S / D regions 146 formed in the region corresponding to the first portion FP of the fin structure 112 each have a constant third width w3 along the X direction, and the S / D regions 146 formed in the region corresponding to the second portion SP of the fin structure 112 each have a constant fourth width w4 along the X direction, and the constant fourth width w4 is generally larger than the constant third width w3. The S / D regions 146 formed in the region corresponding to the transition portion TP of the fin structure each have a varying width along the X direction, and the varying width includes widths w3, w4, and the width transitioning from width w3 to width w4.

[0110] In some embodiments, a plurality of first dielectric spacers 144 ( Figure 14B A plurality of first dielectric spacers 144 are located in a first portion FP of the fin structure 112, and a plurality of second dielectric spacers 144 are located in a second portion SP of the fin structure 112. Each of the plurality of first dielectric spacers 144 has a first aspect ratio, and each of the plurality of second dielectric spacers 144 has a second aspect ratio that is substantially smaller than the first aspect ratio. In some embodiments, an S / D region 146 between the sacrificial gate electrode layer 134 located above the first portion FP of the fin structure 112 and the sacrificial gate electrode layer 134 located above the second portion SP of the fin structure 112 is in contact with the first and second plurality of dielectric spacers 144.

[0111] Figure 15 This is a perspective view of another site of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 15 In this process, the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 are removed, exposing a portion of the top surface of the topmost first semiconductor layer 106. A first portion of the insulating layer 117 is also exposed. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can be performed by any suitable process, such as, for example, dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant (e.g., tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134, but without removing the spacer 140, the insulating layer 117, the ILD layer 163, and the CESL 162.

[0112] After removing the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132, a selective wet etching process can be used to remove the second semiconductor layer 108. In embodiments where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove SiGe without significantly affecting Si, the dielectric material of spacer 140, the insulating layer 117, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant, such as (but not limited to) hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant such as a fluorine-based (e.g., F2) or chlorine-based (e.g., Cl2) gas, or any suitable isotropic etchant.

[0113] like Figure 16A and Figure 16BAs shown, after removing the second semiconductor layer 108 to form a nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, the transition portion TP does not overlap with any portion of the gate structure 174. In some embodiments, an interfacial layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. The IL 168 may include an oxide, such as silicon oxide, and may be formed by a cleaning process. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 can include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate dielectric layer 170 and the gate electrode layer 172 can also be deposited over the ILD layer 163. The gate dielectric layer 170 and gate electrode layer 172 formed above the ILD layer 163 are then removed by means of, for example, CMP, until the top surface of the ILD layer 163 is exposed.

[0114] Figures 17A to 17E This is a top view of various types of protrusion geometries according to some embodiments. Semiconductor device structures 200, 210, 220, 230, 240 are similar to semiconductor device structure 100 (e.g., in...). Figures 5A to 5C or alternative Figures 6A to 6C (The manufacturing site shown). Figure 17A In the modified hard mask fin structure 202, there are symmetric jogs 206 (e.g., similar to...). Figures 5A to 5C The modified hard mask fin structure 115'. As indicated by the opposing arrows oriented in the same direction along the X-axis, the symmetrical protrusion 206 includes the width of the hard mask fin structure that narrows from both sides (e.g., one or more overlapping points in the X direction). Figure 17AAn exemplary photoresist 204, which can be used to form the modified hard mask fin structure 202, is schematically shown to illustrate the alignment between the modified hard mask fin structure 202 and the photoresist 204. For example, the photoresist 204 can protect etch-free portions of the hard mask fin structure (e.g., similar to...). Figure 4A and Figure 4B The second photoresist layer 123). Similar to photoresist 204, Figures 17B to 17E Other exemplary photoresists are shown below, as described in more detail.

[0115] exist Figure 17B In the modified hard mask fin structure 212, an inner jog 216 is included. As indicated by a single arrow oriented from the inside out, the inner jog 216 includes the width of the hard mask fin structure that narrows only from the inside. An exemplary photoresist 214 is used to form the modified hard mask fin structure 212. For example, the photoresist 214 can protect etched portions of the hard mask fin structure.

[0116] exist Figure 17C In the modified hard mask fin structure 222, an outer jog 226 is included. As indicated by a single arrow oriented from the outside in, the outer jog 226 includes the width of the hard mask fin structure that narrows only from the outside. An exemplary photoresist 224 is used to form the modified hard mask fin structure 222. For example, the photoresist 224 can protect etchable portions of the hard mask fin structure.

[0117] exist Figure 17D In the modified hard mask fin structure 232, an asymmetric protrusion 236 is included. As indicated by opposing arrows oriented in different directions along the X-axis, the asymmetric protrusion 236 includes the width of the hard mask fin structure that narrows from both sides (e.g., non-overlapping points in the X-direction). Figure 17D In this process, the asymmetrical protrusions 236 spanning adjacent hard mask fin structures are aligned in the Y direction, such that the resulting combined pattern is symmetrical relative to the X-axis. An exemplary photoresist 234 is used to form the modified hard mask fin structure 232. For example, the photoresist 234 can protect un-etched portions of the hard mask fin structure.

[0118] exist Figure 17E In the modified hard mask fin structure 242, staggered jogs 246 are included. The staggered jogs 246 include asymmetrical jogs combined with inner jogs, the inner recesses extending only in the middle portion of the hard mask fin structure in the X direction. Figure 17E In this case, the asymmetrical protrusions spanning adjacent hard mask fin structures are not aligned in the Y direction, causing the resulting patterns to intersect in the X direction. Figure 17EIn this process, the internal protrusions spanning adjacent hard mask fin structures are aligned in the Y direction, such that the resulting pattern defines square trenches between adjacent hard mask fin structures. An exemplary photoresist 244 is used to form the modified hard mask fin structure 242. For example, the photoresist 244 can protect un-etched portions of the hard mask fin.

[0119] Although the protrusion geometry was described above with reference to the corresponding modified hard mask fin structure, the same protrusion geometry also applies to the corresponding fin structure produced by etching the semiconductor layer stack 104 according to the pattern of the modified hard mask fin structure (e.g., similar to...). Figures 6A to 6C fin structure 112).

[0120] This utility model provides a semiconductor device structure and a method for forming the same. In some embodiments, the method for forming the semiconductor device structure includes forming a semiconductor layer stack on a substrate, depositing a hard mask on the semiconductor layer stack, forming a first photoresist layer over the hard mask, the first photoresist layer defining a first opening that exposes a plurality of portions of the hard mask to be etched, etching portions of the hard mask to form a hard mask fin structure, forming a second photoresist layer over a first portion of the hard mask fin structure, the second photoresist layer defining a second opening that exposes a second portion of the hard mask fin structure to be etched, etching the second portion of the hard mask fin structure to form a modified hard mask fin structure, and etching a plurality of portions of the semiconductor layer stack to form a fin structure.

[0121] In some embodiments, the fin structure extends longitudinally in a first direction and has a varying width in a second direction that is substantially perpendicular to the first direction.

[0122] In some embodiments, during the etching of the second portion of the hard mask fin structure, the first portion of the hard mask fin structure is protected by a second photoresist layer.

[0123] In some embodiments, the method of forming a semiconductor device structure further includes forming a first sacrificial gate structure and a second sacrificial gate structure over a fin structure.

[0124] In some embodiments, the fin structure includes a first portion having a first width, a second portion having a second width, and a transition portion between the first portion and the second portion, wherein the transition portion is located between the first sacrificial gate structure and the second sacrificial gate structure.

[0125] In some embodiments, the method of forming a semiconductor device structure further includes forming a first source / drain region between the first sacrificial gate structure and the second sacrificial gate structure.

[0126] In some embodiments, in a top view, the first source / drain region includes different complex widths.

[0127] In some embodiments, the method of forming a semiconductor device structure further includes forming a second source / drain region and a third source / drain region, wherein a first sacrificial gate structure is located between the first source / drain region and the second source / drain region, and a second sacrificial gate structure is located between the first source / drain region and the third source / drain region.

[0128] In some embodiments, in a top view, the width of the third source / drain region is greater than the width of the second source / drain region.

[0129] Another embodiment is a method of forming a semiconductor device structure. The method includes forming a hard mask fin structure over one or more semiconductor layers, the hard mask fin structure having a varying width along a first direction. The method further includes removing a plurality of portions of one or more semiconductor layers to form the fin structure, the fin structure having a varying width along the first direction. The method further includes depositing an insulating layer adjacent to the fin structure, forming a first sacrificial gate structure over a portion of the fin structure, the first sacrificial gate structure extending in a second direction substantially perpendicular to the first direction. The method further includes recessing a plurality of exposed portions of the fin structure to expose portions of a substrate, and forming a first source / drain region on the exposed portions of the substrate. The first source / drain region has a varying width along the first direction.

[0130] In some embodiments, the method of forming a semiconductor device structure further includes forming a second source / drain region, wherein the first source / drain region is formed on one side of the first sacrificial gate structure, and the second source / drain region is formed on the opposite side of the first sacrificial gate structure.

[0131] In some embodiments, the second source / drain region has a first constant width along a first direction.

[0132] In some embodiments, the method of forming a semiconductor device structure further includes forming a second sacrificial gate structure and forming a third source / drain region. A first source / drain region is formed on one side of the second sacrificial gate structure, and a third source / drain region is formed on the opposite side of the second sacrificial gate structure.

[0133] In some embodiments, the third source / drain region has a second constant width along a first direction, wherein the second constant width is substantially greater than the first constant width.

[0134] In some embodiments, the fin structure includes a first portion having a first width, a second portion having a second width substantially greater than the first width, and a transition portion between the first portion and the second portion.

[0135] In some embodiments, the transition portion is located between the first sacrificial gate structure and the second sacrificial gate structure.

[0136] Another embodiment is a semiconductor device structure. The structure includes a first gate electrode layer disposed above a substrate and extending in a first direction. The structure also includes a second gate electrode layer disposed above the substrate and extending in the first direction. The structure further includes a first source / drain region disposed on a first side of the first gate electrode layer, and the first source / drain region has a first constant width along a second direction substantially perpendicular to the first direction. The structure also includes a second source / drain region disposed on a second side of the first gate electrode layer opposite to the first side, and the second source / drain region has a varying width along the second direction.

[0137] In some embodiments, the second source / drain region is disposed on the first side of the second gate electrode layer.

[0138] In some embodiments, the semiconductor device structure further includes a third source / drain region disposed on a second side of the second gate electrode layer opposite to the first side, wherein the third source / drain region has a second constant width along a second direction.

[0139] In some embodiments, the second constant width is substantially greater than the first constant width.

[0140] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the present invention from various aspects. Those skilled in the art will understand and readily realize that other processes and structures can be designed or modified based on the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of the present invention. Various changes, substitutions, or modifications can be made to the present invention without departing from its inventive spirit and scope.

Claims

1. A semiconductor device structure, characterized by, Comprising: a first gate electrode layer disposed over a substrate, wherein the first gate electrode layer extends in a first direction; a second gate electrode layer disposed over the substrate, wherein the second gate electrode layer extends in the first direction; a first source / drain region disposed on a first side of the first gate electrode layer, wherein the first source / drain region has a first constant width along a second direction substantially perpendicular to the first direction; and a second source / drain region disposed on a second side of the first gate electrode layer opposite the first side, wherein the second source / drain region has a varying width along the second direction.

2. The semiconductor device structure of claim 1, wherein, The second source / drain region is disposed on a first side of the second gate electrode layer.

3. The semiconductor device structure of claim 2, wherein, Further comprising a third source / drain region disposed on a second side of the second gate electrode layer opposite the first side.

4. The semiconductor device structure of claim 3, wherein, The third source / drain region has a second constant width along the second direction.

5. The semiconductor device structure of claim 4, wherein, The second constant width is substantially greater than the first constant width.

6. The semiconductor device structure of claim 5, wherein, The second source / drain region includes a first portion on the second side of the first gate electrode layer, a second portion on the first side of the second gate electrode layer, and a transition portion between the first and second portions.

7. The semiconductor device structure of claim 6, wherein, The transition portion of the second source / drain region has a linearly sloped taper.

8. The semiconductor device structure of claim 6, wherein, The first portion of the second source / drain region has the first constant width, and the second portion of the second source / drain region has the second constant width.

9. The semiconductor device structure of claim 6, wherein, The transition portion of the second source / drain region intersects the first portion of the second source / drain region at an obtuse angle.

10. The semiconductor device structure of claim 6, wherein, The transition portion of the second source / drain region intersects the second portion of the second source / drain region at an acute angle.

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