Divider based on subtractor group, chip and wearable device

Abstract

The utility model relates to a divider based on a subtractor group, a chip and wearable equipment. The divider comprises an input module and the subtractor group, the input module inputs the divisor and the dividend into the subtractor group; the subtractor group comprises multiple stages of subtraction modules which are sequentially connected in series; two operation elements of the subtraction module come from the subtraction module at the upper level; after the two operation elements are subjected to shift subtraction in the subtraction module, two new operation elements are generated and are input into the subtraction module of the next level; each level of subtraction module outputs a comparison result of the level according to comparison between two operation elements; and the last-stage subtraction module is also connected with the first-stage subtraction module through the input module to form a loop structure so as to sequentially output comparison results generated by the subtractor group in previous cycles, so that the problem that the area overhead of the existing divider is relatively large is solved, the area overhead of the divider is reduced, the calculation complexity is simplified, and the calculation efficiency is improved. And the method is suitable for scenes with harsh device area requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital chip circuit design, in particular to a divider based on a subtractor group, a chip and a wearable device. BACKGROUND

[0002] The complexity of division operation is high, and the device used for division operation usually occupies a large area. Especially in devices with volume requirements, such as wearable devices, the limitation of hardware overhead of the divider structure is also more stringent.

[0003] The current principle design of the divider capable of reducing the calculation complexity is to obtain the reciprocal of the divisor by using a lookup table, and then to design a multiplier to multiply the reciprocal of the divisor and the dividend to obtain the result. This way, the calculation speed is faster, but the hardware overhead of the lookup table and the multiplier is still too large. In addition, there is also a way of obtaining the corresponding remainder lookup table and quotient lookup table by presetting the divisor to obtain the final result by step-by-step lookup. This way reduces the calculation unit, but increases the number of lookup tables, and the area overhead is also large.

[0004] At present, there is no effective solution to the problem of large area overhead of the divider in the related art. CONTENT OF THE INVENTION

[0005] In the present embodiment, a divider based on a subtractor group, a chip and a wearable device are provided to solve the problem of large area overhead of the divider in the related art.

[0006] In a first aspect, a divider based on a subtractor group is provided in the present embodiment, and the divider comprises an input module and a subtractor group.

[0007] The input module is connected with the subtractor group, and is configured to input a divisor and a dividend into the subtractor group.

[0008] The subtractor group comprises a plurality of stages of subtraction modules, the input end of the subtraction module of the first stage is connected with the output end of the input module, and the output end of each stage of the subtraction module is connected with the input end of the subtraction module of the next stage.

[0009] The output end of the subtraction module of the last stage is further connected with the input end of the subtraction module of the first stage through the input module.

[0010] In some embodiments, each stage of the subtraction module comprises a shift unit and a subtraction unit.

[0011] The output end of the shift unit is connected with the first input end of the subtraction unit; the second input end of the first stage of the subtraction unit is connected with the output end of the input module; the second input end of the rest stages of the subtraction unit is connected with the first output end of the subtraction unit of the previous stage;

[0012] The input end of the first stage of the shift unit is connected with the output end of the input module; the input end of the rest stages of the shift unit is connected with the output end of the shift unit of the previous stage.

[0013] In some embodiments, the subtraction unit is a 16-bit subtractor.

[0014] In some embodiments, four stages of the subtraction module are arranged in the subtractor group.

[0015] In some embodiments, the divider further comprises a storage module; the input end of the storage module is connected with the output end of each stage of the subtraction module in the subtractor group.

[0016] In some embodiments, the storage module comprises a shift register group, and the shift register group comprises a shift register unit; the second output end of each stage of the subtraction module is connected with the corresponding shift register unit of the stage.

[0017] In some embodiments, the divider further comprises a counter; the counter is connected with the control end of the input module, and is used for controlling the cycle number of the subtractor group.

[0018] In some embodiments, the input module comprises a first input unit and a second input unit; the first input unit and the second input unit are respectively connected with the counter;

[0019] The output end of the first input unit is connected with the input end of the first stage of the shift unit, and the output end of the second input unit is connected with the input end of the first stage of the subtraction unit.

[0020] The input end of the first input unit is feedback connected with the output end of the last stage of the shift unit, and the input end of the second input unit is feedback connected with the output end of the first stage of the subtraction unit.

[0021] The counter is used for recording the cycle number of the subtractor group, and simultaneously controls the opening and closing of the first input unit and the second input unit according to the cycle number.

[0022] In a second aspect, the present application provides a chip, which comprises the divider in any one of the first aspect.

[0023] In a third aspect, the application provides a wearable device, wherein a master chip of the wearable device is provided with the divider according to any one of the first aspect.

[0024] Compared with the related art, the divider based on the subtractor group, the chip and the wearable device provided in the embodiment, the divider comprises an input module and a subtractor group; the input module is connected with the subtractor group, and is used to input a divisor and a dividend into the subtractor group; the subtractor group comprises multiple-stage subtractor modules connected in series; two operation elements of the subtractor module at a first stage come from the input module, and two operation elements of the subtractor module at each of the remaining stages come from the subtractor module at a previous stage; after the two operation elements are subtracted after being shifted in the subtractor module, two new operation elements are generated to be input into the subtractor module at a next stage; according to a comparison between the two operation elements, the subtractor module at each stage outputs a comparison result at the stage; the subtractor module at a last stage is further connected with the subtractor module at the first stage through the input module to form a loop structure, so as to sequentially output the comparison results generated by the subtractor group in the previous loops, solve the problem of large area overhead of the existing divider, and provide the subtractor group based on the serial loop subtraction, which simplifies the calculation complexity and reduces the area overhead, and is suitable for a scene with strict requirements on device area.

[0025] Details of one or more embodiments of the application are set forth in the accompanying drawings and description below to make other features, objects, and advantages of the application more clear. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are included to provide a further understanding of the application, illustrate embodiments of the application and together with the description serve to explain the application. The accompanying drawings are included as part of this specification and illustrate embodiments of the application and, together with the description, serve to explain the application. In the drawings:

[0027] Figure 1 FIG. 1 is a structural schematic diagram of a divider based on a subtractor group in an embodiment of the application;

[0028] Figure 2 FIG. 2 is a structural schematic diagram of a divider based on a subtractor group in another embodiment of the application;

[0029] Figure 3 FIG. 3 is a structural schematic diagram of a storage module in an embodiment of the application;

[0030] Figure 4 FIG. 4 is a structural schematic diagram of a divider based on a subtractor group in a preferred embodiment of the application;

[0031] Figure 5 FIG. 5 is a structural schematic diagram of a divider based on a subtractor group in another preferred embodiment of the application.

[0032] Reference signs: 100, input module; 200, subtracter group; 210, shift unit; 220, subtraction unit; 300, storage module; 310, shift register unit; 400, counter. DETAILED DESCRIPTION

[0033] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and explained below in conjunction with the accompanying drawings and embodiments.

[0034] Unless otherwise defined, technical terms or scientific terms used in the present application shall have the general meaning understood by a person with ordinary skill in the art to which the present application belongs. In the present application, "one", "a", "an", "the", "these" and similar words do not represent a quantitative limitation, and they can be singular or plural. In the present application, the terms "include", "contain", "have" and any variants thereof have the purpose of covering non-exclusive inclusion; for example, a process, method and system, product or device containing a series of steps or modules (units) are not limited to the listed steps or modules (units), but can include steps or modules (units) not listed, or can include other steps or modules (units) inherent to the process, method, product or device. In the present application, the terms "connected", "connected", "coupled" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. In the present application, "multiple" means two or more. The association between the associated objects is described by the term "and / or", which means that there can be three relationships, for example, "A and / or B" can mean that A exists alone, A and B exist together, and B exists alone. In general, the character " / " represents an "or" relationship between the objects before and after it. In the present application, the terms "first", "second", "third" and the like are only used to distinguish similar objects, and do not represent a specific order for the objects.

[0035] In the present embodiment, a divider based on the subtracter group 200 is provided, as shown in Figure 1 The divider includes an input module 100 and a subtracter group 200.

[0036] The input module 100 is connected to the subtracter group 200, and is configured to input the divisor and the dividend to the subtracter group 200.

[0037] The subtracter group 200 includes a plurality of subtraction modules connected in series, and the input end of the first subtraction module is connected to the output end of the input module 100. The output end of each subtraction module is connected to the input end of the next subtraction module.

[0038] The two operation elements of the subtraction module of the first stage come from the input module 100, and the two operation elements of the subtraction module of each of the remaining stages come from the subtraction module of the previous stage; the two operation elements are subtracted after being shifted in the subtraction module to generate two new operation elements, which are input to the subtraction module of the next stage; each subtraction module outputs the comparison result of the current stage according to the comparison between the two operation elements.

[0039] The output end of the subtraction module of the last stage is also connected with the input end of the subtraction module of the first stage through the input module 100 to form a loop structure to sequentially output the comparison results generated in the previous loops by the subtraction module 200.

[0040] Specifically, the input module 100 inputs the received divisor as one of the operation elements to the subtraction module and inputs the received dividend as the other operation element to the subtraction module; in the loop calculation, the two new operation elements output by the subtraction module of the last stage are input to the subtraction module of the first stage through the input module 100 to perform a new round of calculation; the subtraction module of the multiple stages is simplified to simplify the division operation, and the target precision of the division result is obtained through multiple loops.

[0041] The division result is obtained based on the comparison results generated in the previous loops, and the multiple comparison results of the multiple subtraction modules in one loop form a group, and multiple groups of multiple comparison results are obtained through multiple loops; the multiple comparison results sequentially generated in the previous loops are received and saved to obtain the division result, i.e., the quotient of the divisor and the dividend.

[0042] In the embodiment, the input module 100 is connected with the subtraction module 200 to input the divisor and the dividend to the subtraction module 200; the subtraction module 200 includes multiple subtraction modules connected in sequence, the two operation elements of the subtraction module of the first stage come from the input module 100, and the two operation elements of the subtraction module of each of the remaining stages come from the subtraction module of the previous stage; the two operation elements are subtracted after being shifted in the subtraction module to generate two new operation elements, which are input to the subtraction module of the next stage; each subtraction module outputs the comparison result of the current stage according to the comparison between the two operation elements; the subtraction module of the last stage is also connected with the subtraction module of the first stage through the input module 100 to form a loop structure to sequentially output the comparison results generated in the previous loops by the subtraction module 200, which solves the problem of large area overhead of the existing division module, provides an operation module based on the subtraction in series loop, i.e., the subtraction module 200, reduces the area overhead, simplifies the calculation complexity, and is suitable for scenes with high requirements on device area.

[0043] In some embodiments, each subtraction module includes a shift unit 210 and a subtraction unit 220.

[0044] The output of shift unit 210 is connected to the first input of subtraction unit 220.

[0045] The second input terminal of the first-level subtraction unit 220 is connected to the output terminal of the input module 100; the second input terminal of each of the other subtraction units 220 is connected to the first output terminal of the previous-level subtraction unit 220; the second output terminal of the current-level subtraction unit 220 is used to output the comparison result of the current level.

[0046] The input terminal of the first-stage shift unit 210 is connected to the output terminal of the input module 100; the input terminals of the remaining shift units 210 are connected to the output terminals of the previous-stage shift unit 210, and the shift unit 210 is used to shift the input and then output it.

[0047] The minuend of the first-level subtraction unit 220 comes from the input module 100, while the minuends of the remaining subtraction units 220 come from the previous-level subtraction unit 220; the subtrahend of the current-level subtraction unit 220 comes from the current-level shift unit 210. The current-level subtraction unit 220 outputs the comparison result and the difference result based on the relationship between the minuend and the subtrahend; the comparison result is used to combine the results into a quotient, and the difference result is used as the minuend of the next-level subtraction unit 220.

[0048] Specifically, the input module 100 inputs the received dividend as the minuend into the first-level subtraction unit 220; and when the first-level subtraction unit 220 is reused, the difference result output by the last-level subtraction unit 220 in the previous loop is input as the minuend into the first-level subtraction unit 220. Additionally, the input module 100 inputs the received divisor as the subtrahend into the first-level shift unit 210; and when the first-level shift unit 210 is reused, the shift result output by the last-level shift unit 210 in the previous loop is input as the subtrahend into the first-level shift unit 210.

[0049] For details, see Figure 2 The output of shift unit 210 is equal to the input shifted right by 1 bit. Subtraction unit 220 includes two input terminals A and B, and two output terminals C and D. The first input terminal A is connected to the previous subtraction unit 220 to receive the difference result output by the previous subtraction unit 220, and uses the difference result as the minuend; the second input terminal is connected to the shift unit 210 of this stage to receive the subtrahend; the subtraction unit 220 is used to implement the following logic: compare the minuend at A and the subtrahend at B. If the minuend at A is greater than or equal to the subtrahend at B, then 1 is output at D, which is the comparison result, and the difference between the minuend at A and the subtrahend at B is output at C, which is the difference result; if the minuend at A is less than the subtrahend at B, then 0 is output at D, which is the comparison result, and the minuend at A is output at C, which is the difference result.

[0050] In some embodiments, the subtraction unit 220 is a 16-bit subtractor for processing 16-bit dividend and divisor.

[0051] In other embodiments, the subtraction unit 220 includes but is not limited to a 32-bit subtractor or a 64-bit subtractor.

[0052] In some embodiments, a 4-stage subtraction module is arranged in the subtractor group 200. In this case, the comparison result of the 4-stage subtraction module is output within one clock cycle. If four cycles are passed, a 16-bit division result can be output; if eight cycles are passed, a 32-bit division result can be output. Through the design of the number of series and the overall number of cycles in the subtractor group 200, the hardware area overhead and the calculation time of the device can be balanced.

[0053] In some embodiments, referring to Figure 2 , the divider further includes a storage module 300; the input end of the storage module 300 is connected with the output end of each stage of the subtraction module in the subtractor group 200, for receiving and storing the comparison result.

[0054] In some embodiments, the storage module 300 includes a shift register group, and the shift register group includes a shift register unit 310; the second output end of each subtraction module is connected with the corresponding shift register unit 310 of the stage.

[0055] Specifically, as shown in Figure 3 , each group of shift register units 310 includes a plurality of registers in series, and the more the number of registers, the more the number of bits of the division result that can be stored. The subtractor group 200 stores one bit (1 bit) of data in each group of shift register units 310 for each cycle, and the shift register units 310 are updated after the next cycle. The data in each group of shift register units 310 is simultaneously shifted in the same direction until the shift register units 310 are full, the cycle is stopped, or until the counter 400 reaches the target count value, the cycle is stopped. The more the number of cycles, the higher the accuracy of the division result, and the larger the required storage space.

[0056] In some embodiments, referring to Figure 4 , the divider further includes a counter 400; the counter 400 is connected with the input module 100, for controlling the number of cycles of the subtractor group 200.

[0057] Specifically, the counter 400 starts from 0, when the counter 400 equals 0, the input module 100 inputs the divisor and the dividend into the subtracter group 200. After the subtracter group 200 finishes the calculation, the counter 400 adds 1, the input module 100 feeds back the output of the last subtracter group 200 to the subtracter group 200, and the cycle calculation is repeated. The counter 400 is set with a stop number, when the counter value reaches the count number, the division calculation is completed, the cycle is stopped, and the quotient can be obtained from the storage module 300.

[0058] In some embodiments, the input module 100 comprises a first input unit and a second input unit; the first input unit and the second input unit are connected with the counter 400 respectively.

[0059] The output end of the first input unit is connected with the input end of the shift unit 210 of the first stage, and the output end of the second input unit is connected with the output end of the subtraction unit 220 of the first stage; the input end of the first input unit is feedback connected with the output end of the shift unit 210 of the last stage, and the input end of the second input unit is also feedback connected with the output end of the subtraction unit 220 of the last stage.

[0060] The counter 400 is used for recording the cycle number of the subtracter group 200, and simultaneously controls the opening and closing of the first input unit and the second input unit according to the cycle number.

[0061] In some embodiments, the first input unit comprises a first selector and a subtractor register, and the second input unit comprises a second selector and a minuend register.

[0062] The output of the shift unit 210 of the last stage in the subtracter group 200 is connected with the first selector, and the difference result of the subtraction unit 220 of the last stage in the subtracter group 200 is connected with the second selector.

[0063] The first selector is connected with the shift unit 210 of the first stage in the subtracter group 200 through the subtractor register, and the second selector is connected with the subtraction unit 220 of the first stage in the subtracter group 200 through the minuend register.

[0064] The first selector and the second selector are also connected with the counter 400 respectively.

[0065] The counter 400 starts from 0, when the counter 400 equals 0, the divisor and the dividend are stored in the subtractor register and the minuend register from the first selector and the second selector respectively. After the counter 400 adds 1, the subtractor register and the minuend register are updated as the output of the last subtracter.

[0066] The preferred embodiments are described and explained below. Figure 4Fig. 2 is a schematic diagram of a divider structure based on subtractor group 200 in a preferred embodiment.

[0067] As shown in Fig. 1, the divider comprises input module 100, subtractor group 200, counter 400 and storage module 300. Figure 4

[0068] Input module 100 is connected with subtractor group 200, for inputting the divisor and the dividend into subtractor group 200.

[0069] Subtractor group 200 comprises 4-stage subtractor modules connected in series. The two operation elements of the first-stage subtractor module come from input module 100, and the two operation elements of each of the remaining subtractor modules come from the subtractor module of the previous stage. After the two operation elements are subtracted in the subtractor module, two new operation elements are generated and input into the subtractor module of the next stage. Each subtractor module outputs the comparison result of the two operation elements according to the comparison between the two operation elements.

[0070] The last-stage subtractor module is also connected with the first-stage subtractor module through input module 100, forming a loop structure, for sequentially outputting the comparison results generated by subtractor group 200 in each loop.

[0071] Each subtractor module comprises shift unit 210 and subtractor unit 220. Subtractor unit 220 is a 16-bit subtractor.

[0072] Shift unit 210 and subtractor unit 220 are connected. The input of the current shift unit 210 comes from the shift unit 210 of the previous stage, and the shift unit 210 outputs the shifted input. The minuend of the current subtractor unit 220 comes from the subtractor unit 220 of the previous stage, and the subtrahend comes from the shift unit 210 of the current stage. The subtractor unit 220 outputs the comparison result and the difference result of the current stage according to the size relationship between the minuend and the subtrahend. The comparison result is used to combine the quotient, and the difference result is used as the minuend of the subtractor unit 220 of the next stage.

[0073] The divider further comprises storage module 300. Storage module 300 is connected with subtractor group 200, for receiving and storing the comparison results. Storage module 300 comprises a shift register group, which comprises shift register units 310. Each subtractor module is connected with a group of shift register units 310.

[0074] The divider further comprises counter 400. Counter 400 is connected with input module 100, for controlling the number of loops of subtractor group 200.

[0075] ​In the preferred embodiment, the output of the subtractor group 200 is connected back to the input for multiple loop iterations. The minuend of each subtractor in the subtractor group 200 comes from the result of the previous stage, the subtrahend comes from the shift unit 210, and the comparison result of the minuend and the subtrahend goes to the shift register. The counter 400 counts from 0 to 4, representing the start to the end of the division. During the counting, the difference of the serial subtractors is connected back to the minuend of the serial subtractors, and the subtrahend is divided by 16 and then connected back to the subtrahend of the serial subtractors, completing 4 iterations. When the counter 400 counts to 4, the result of the shift register group is the final result of the division.

[0076] In the preferred embodiment, the output of the subtractor group 200 is connected back to the input for multiple loop iterations. The minuend of each subtractor in the subtractor group 200 comes from the result of the previous stage, the subtrahend comes from the shift unit 210, and the comparison result of the minuend and the subtrahend goes to the shift register. The counter 400 counts from 0 to 4, representing the start to the end of the division. During the counting, the difference of the serial subtractors is connected back to the minuend of the serial subtractors, and the subtrahend is divided by 16 and then connected back to the subtrahend of the serial subtractors, completing 4 iterations. When the counter 400 counts to 4, the result of the shift register group is the final result of the division.

[0077] In the preferred embodiment, the output of the subtractor group 200 is connected back to the input for multiple loop iterations. The minuend of each subtractor in the subtractor group 200 comes from the result of the previous stage, the subtrahend comes from the shift unit 210, and the comparison result of the minuend and the subtrahend goes to the shift register. The counter 400 counts from 0 to 4, representing the start to the end of the division. During the counting, the difference of the serial subtractors is connected back to the minuend of the serial subtractors, and the subtrahend is divided by 16 and then connected back to the subtrahend of the serial subtractors, completing 4 iterations. When the counter 400 counts to 4, the result of the shift register group is the final result of the division.

[0078] R

[15] = Q0, R

[11] = Q1, R[7] = Q2, R[3] = Q3;

[0079] R

[14] = Q4, R

[10] = Q5, R[6] = Q6, R[2] = Q7;

[0080] R

[13] = Q8, R[9] = Q9, R[5] = Q10, R[1] = Q11;

[0081] R

[12] = Q12, R[8] = Q13, R[4] = Q14, R[0] = Q15.

[0082] In the preferred embodiment, a cyclic subtractor divider circuit structure is proposed, which has small hardware overhead and is suitable for wearable chips with high area requirements.

[0083] In another preferred embodiment, referring to Figure 5 The counting period of the counter 400 can be extended, and the number of serial registers in the shift register group can be increased, for example, the counting period is extended to 8, and the number of registers in the shift register group is modified to 4x8, so that a 32-bit divider can be obtained.

[0084] In the present application, a chip is also provided, which includes the divider in any of the above embodiments.

[0085] In the present embodiment, the problem of large area overhead of existing dividers is solved, and a subtractor group 200 based on serial cyclic subtraction is provided, which reduces the area overhead and simplifies the calculation complexity, and is suitable for scenes with high requirements on device area.

[0086] A wearable device is also provided in the present application, and a division device as in any of the above embodiments is arranged on a master control chip of the wearable device.

[0087] In the present embodiment, the problem of large area overhead of the existing division device is solved, which helps to reduce the volume of the wearable device.

[0088] It should be understood that the specific embodiments described herein are merely exemplary and not intended to limit the application. Any other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present application without creative labor are within the scope of the present application.

[0089] Obviously, the drawings are only some examples or embodiments of the present application, and those of ordinary skill in the art can also apply the present application to other similar situations without creative labor. In addition, it can be understood that although the work done in the development process may be complex and long, some design, manufacture or production changes made by those of ordinary skill in the art according to the technical content disclosed in the present application are only routine technical means and should not be regarded as insufficient disclosure of the present application.

[0090] The term "embodiment" in the present application means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the present application. The presence of this phrase in various places in the specification does not necessarily mean the same embodiment, nor does it mean independence or alternative to other embodiments. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0091] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of patent protection. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A subtractor bank based divider, characterized by, The divider comprises an input module (100) and a subtracter group (200); The input module (100) is connected with the subtracter group (200) and used for inputting a divisor and a dividend into the subtracter group (200); The subtracter group (200) comprises a plurality of subtracter modules, the input end of the first subtracter module is connected with the output end of the input module (100), the output end of each subtracter module is connected with the input end of the next subtracter module; The output end of the last subtracter module is further connected with the input end of the first subtracter module through the input module (100).

2. The subtractor bank based divider of claim 1, wherein, Each subtracter module comprises a shift unit (210) and a subtracter unit (220); The output end of the shift unit (210) is connected with the first input end of the subtracter unit (220); The second input end of the first subtracter unit (220) is connected with the output end of the input module (100); The second input end of each remaining subtracter unit (220) is connected with the first output end of the subtracter unit (220) of the previous stage; The input end of the first shift unit (210) is connected with the output end of the input module (100), and the input end of each remaining shift unit (210) is connected with the output end of the shift unit (210) of the previous stage.

3. The subtractor bank based divider of claim 2, wherein, The subtracter unit (220) is a 16-bit subtracter.

4. The subtracter bank based divider of claim 1, wherein, There are four stages of subtracter modules in the subtracter group (200).

5. The subtractor bank based divider of claim 1, wherein, The divider further comprises a storage module (300), and the input end of the storage module (300) is connected with the output end of each subtracter module in the subtracter group (200).

6. The subtractor bank based divider of claim 5, wherein, The storage module (300) comprises a shift register group, and the shift register group comprises a shift register unit (310), and the second output end of each subtracter module is connected with the corresponding shift register unit (310).

7. The subtractor bank based divider of claim 2, wherein, The divider further comprises a counter (400), and the counter (400) is connected with the control end of the input module (100) and used for controlling the cycle number of the subtracter group (200).

8. The subtractor bank based divider of claim 7, wherein, The input module (100) comprises a first input unit and a second input unit, and the first input unit and the second input unit are connected with the counter (400); The output end of the first input unit is connected with the input end of the first shift unit (210), and the output end of the second input unit is connected with the input end of the first subtracter unit (220); The input end of the first input unit is feedback connected with the output end of the last shift unit (210), and the input end of the second input unit is further feedback connected with the output end of the first subtracter unit (220); The counter (400) is used for recording the cycle number of the subtracter group (200) and simultaneously controlling the opening and closing of the first input unit and the second input unit according to the cycle number.

9. A chip, characterized by The chip comprises the divider in any one of claims 1 to 8.

10. A wearable device, comprising: The main control chip of the wearable device is provided with the divider as claimed in any one of claims 1 to 8. The main control chip of the wearable device is provided with the divider as claimed in any one of claims 1 to 8.

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