Multiplexer, driving chip and display device

Abstract

The utility model provides a multiplexer, a driving chip and a display device, the multiplexer comprises a plurality of selection paths located between an input end and a plurality of output ends, each selection path comprises a first switch tube, the first end and the second end of the first switch tube are respectively connected with the input end and the output end, the control end receives a selection control signal, and the first switch tube is connected with the input end and the output end of the first switch tube; the switch-on and switch-off of the selection path are controlled; the energy storage unit is connected to the control end of the first switching tube, collects and stores charges before the control end is converted from the high level to the low level, and releases the charges to the control end before the control end is converted from the low level to the high level; and the switch unit controls transfer of charges between the energy storage unit and the control end through on and off of the switch unit. According to the multiplexer and the application thereof, through the arrangement of the switch unit and the energy storage unit, charges at the control end of the first switch tube are stored and reused, the turn-on and turn-off speed of the first switch tube is increased, and the effect of saving electricity is achieved while the response speed is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular to a multiplexer, a driving chip and a display device. BACKGROUND

[0002] A display device usually comprises a display panel, a gate driver and a source driver, the display panel comprises a pixel array, each unit in the pixel array comprises a sub-pixel unit. The gate driver is connected to the sub-pixel units of corresponding rows via a plurality of scanning lines, for providing driving voltages in a scanning manner, so that the sub-pixel units of different rows are selected in one image frame period. The source driver is connected to the sub-pixel units of corresponding columns via a plurality of data lines, for providing pixel data to the sub-pixel units of each column when a plurality of thin film transistors of each row are selected. In the selected state, the source driver applies gray scale voltages on the sub-pixel units via the data lines, to realize the control of the display picture. The above-mentioned manner can be used to control the OLED type display device or the LED type display device.

[0003] In order to save the number of output buffers of the output end of the source driver, a plurality of MUXs (multiplexers or selectors) are arranged between the output buffers and the data lines, and the data reception of the plurality of data lines can be controlled by one output buffer through the MUX. The conduction and the turn-off of the transistor in the MUX circuit need to be controlled by the selection signal, so as to realize the conduction and the turn-off of the selection path, which increases the power consumption and reduces the charging speed due to the large conduction impedance. CONTENT

[0004] In order to solve the above technical problems, the present application provides a multiplexer, a driving chip and a display device.

[0005] According to an aspect of the present application, a multiplexer is provided, comprising one input end and a plurality of output ends, each output end and the input end are connected by one selection path, each selection path comprises: a first switch tube, the first end and the second end of the first switch tube are connected to the input end and the output end respectively, the control end of the first switch tube receives a selection control signal, and the conduction state of the selection path is controlled according to the selection control signal; an energy storage unit connected to the control end of the first switch tube, which collects and stores the charge of the control end when the control end is disconnected from the selection control signal and is in a high level state, and releases the charge to the control end of the first switch tube when the control end is disconnected from the selection control signal and is in a low level state; and a switch unit connected to the control end of the first switch tube, which controls the transfer of the charge between the energy storage unit and the control end by its conduction and turn-off.

[0006] Optionally, the first switch tube comprises a PMOS tube or an NMOS tube, and the first switch tube is switched between the on state and the off state according to the control of the selection control signal.

[0007] Optionally, the switch unit comprises a first switch connected between the control end of the first switch tube and the energy storage unit to control the transfer of the electric charge, and a second switch connected between the control end of the first switch tube and the providing end of the selection control signal to control the connection path between the selection control signal and the control end to control the on and off of the first switch tube, wherein the switching state of the first switch and the switching state of the second switch are opposite.

[0008] Optionally, when the first switch is on and the selection control signal is changed from invalid to valid, the electric charge at the control end of the first switch tube is collected and stored; when the first switch is on and the selection control signal is changed from valid to invalid, the stored electric charge is released to the control end of the first switch tube; and during the off of the first switch, the selection control signal is transmitted to the control end of the first switch tube through the second switch to control the on and off of the first switch tube, the first switch tube is off when the selection control signal is invalid, and the first switch tube is on when the selection control signal is valid.

[0009] Optionally, the first switch tube is a PMOS tube, the PMOS tube is off when the control end of the PMOS tube is at a high level, the first switch is controlled to be on and the second switch is controlled to be off before the high level of the control end of the PMOS tube is changed to a low level, and part of the electric charge at the control end of the PMOS tube is transferred to the energy storage unit; the PMOS tube is on when the control end of the first switch tube is at a low level, the first switch is controlled to be on and the second switch is controlled to be off before the low level of the control end of the PMOS tube is changed to a high level, and the electric charge on the energy storage unit is transferred to the control end of the PMOS tube.

[0010] Optionally, the first switch tube is an NMOS tube, the NMOS tube is on when the control end of the first switch tube is at a high level, the first switch is controlled to be on and the second switch is controlled to be off before the high level of the control end of the NMOS tube is changed to a low level, and part of the electric charge at the control end of the NMOS tube is transferred to the energy storage unit; the NMOS tube is off when the control end of the first switch tube is at a low level, the first switch is controlled to be on and the second switch is controlled to be off before the low level of the control end of the NMOS tube is changed to a high level, and the electric charge on the energy storage unit is transferred to the control end of the NMOS tube.

[0011] Optionally, the energy storage unit comprises a capacitor, and the capacitor is connected between the first switch and a ground terminal.

[0012] Optionally, each of the selection paths further comprises a second switch tube, a first end and a second end of the second switch tube are connected to the input terminal and the output terminal respectively, a control end of the second switch tube is connected to a control end of the first switch tube through the first switch, and the energy storage unit comprises the control end of the second switch tube.

[0013] Optionally, each of the selection paths further comprises a third switch, the control end of the second switch tube receives an inverted signal of the selection control signal through the third switch, and the second switch tube is synchronously turned on and turned off with the first switch tube.

[0014] Optionally, the first switch tube is one of a PMOS tube and an NMOS tube, and the second switch tube is the other of the PMOS tube and the NMOS tube.

[0015] According to another aspect of the present application, a driving chip is provided, comprising: a source driver configured to provide pixel data according to image data and configured to perform data transmission with data lines of a display area; and the multiplexer described above, wherein the source driver is connected to a plurality of the data lines through the multiplexer, and a pixel array of the display area is controlled through the plurality of the data lines.

[0016] Optionally, the driving chip comprises a display driving chip and a touch and display driving integrated chip.

[0017] According to another aspect of the present application, a display device is provided, comprising: a display panel, wherein the display panel comprises a pixel array and a plurality of data lines, the pixel array comprises a plurality of columns of sub-pixel units, and each data line is connected to a column of sub-pixel units; and the multiplexer described above, wherein an input terminal of the multiplexer is connected to a source driver, an output terminal of the multiplexer is connected to the plurality of the data lines, and the pixel array is controlled through the plurality of the data lines, and the source driver and the multiplexer are integrated in the same chip and located outside the display panel.

[0018] The present application has at least the following beneficial effects:

[0019] The embodiment of the present application provides a multiplexer, a driving chip and a display device, wherein the switch unit and the energy storage unit are arranged in each selection path of the multiplexer, the connection path between the energy storage unit and the first switch tube is controlled by the switch unit, the signal reception of the control end of the first switch tube is controlled, and the charge collection and reuse of the control end of the first switch tube are realized by the energy storage unit. The charge of the control end of the first switch tube is collected and stored before the control end changes from high level to low level by the work of the switch unit, and the charge is released to the control end of the first switch tube before the control end of the first switch tube changes from low level to high level, so that the electric energy required for driving the first switch tube is reduced. Therefore, the cyclic collection and utilization of the charge are realized, the energy recovery is realized, and the power saving effect is achieved.

[0020] Further, the first switch tube comprises a PMOS tube or an NMOS tube, and the energy storage unit can comprise a capacitor or the gate of a second switch tube connected in parallel with the first switch tube, so that different forms of multiplexers can be provided. When the capacitor is selected as the energy storage unit, the charge storage effect is good, and the performance is stable. When the gate of the second switch tube is selected as the energy storage unit, the circuit is simple, the occupied area is small, and the cost is low. Further, when the gate of the second switch tube is selected as the energy storage unit, the second switch tube is synchronously turned on with the first switch tube, that is, the second switch tube and the first switch tube jointly control the turn-on and turn-off of the selection path, so that the turn-on impedance can be reduced. The second switch tube has the function of storing charge while realizing the turn-on control, and the performance of the multiplexer is further optimized.

[0021] It should be noted that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The application of the multiplexer in the display device is shown;

[0023] Figure 2 The waveforms of the signals in the multiplexer of Figure 1 are shown;

[0024] Figure 3 The circuit schematic diagram of the multiplexer according to the first embodiment of the present application is shown;

[0025] Figure 4 The waveforms of the signals in the multiplexer of Figure 3 are shown;

[0026] Figure 5 The circuit schematic diagram of the multiplexer according to the second embodiment of the present application is shown;

[0027] Figure 6 The circuit schematic diagram of the multiplexer according to the second embodiment of the present application is shown;Figure 5 Waveform diagrams of signals in the multiplexer of

[0028] Figure 7 A schematic diagram of a driving chip and a display device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are given in the accompanying drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein.

[0030] In this specification, the phrase "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrases "in one embodiment" or "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, but can refer to one or more but not all embodiments unless otherwise indicated. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. "A plurality" means two or more.

[0031] In addition, the same reference numerals in the drawings denote the same or similar structures, and thus repeated descriptions thereof will be omitted, i.e., the description of each part is given in a combination of parallel and progressive manners, and each part focuses on the difference from other parts, and the same or similar parts between the parts can be understood by referring to each other.

[0032] Figure 1 A schematic diagram of the application of the multiplexer in a display device is shown, Figure 2 A schematic diagram of Figure 1 Waveform diagrams of signals in the multiplexer of

[0033] As Figure 1As shown, the display device includes a pixel array 10, a source driver 20 and a plurality of multiplexers 30, since the embodiment focuses on the function and use of the multiplexers, a series of devices such as the gate driver, the timing controller and the interface unit are omitted in the figure. In the embodiment, the pixel array 10 includes a plurality of sub-pixel units 11, each of which can display one of a plurality of primary colors, which can include at least one of red, green, blue and white. For example, a column of pixel units composed of red and blue pixels and a column of pixel units composed of green pixels are alternately distributed, and each column of pixel units is connected to the source driver 20 through a data line (S1-S6). The source driver 20 is configured to provide pixel data O1, O2, O3, …, to drive the corresponding column of pixel units via the data line. The output end of the source driver 20 is connected with an output buffer circuit 42, which includes a plurality of buffers to realize amplification and other processing of the pixel data. A plurality of multiplexers 30 are further provided between the output buffer circuit 42 and the data line, and the multiplexers are, for example, 1:2, that is, one input end and two output ends, so that the number of buffers can be half of the data lines, saving a large number of buffers.

[0034] Each multiplexer 30 includes two transistors, for example, a transistor P1 and a transistor P2, which are connected with the data lines S1 and S2 respectively as two selection paths. The multiplexer 30 receives selection signals MUX1 and MUX2 through an external output buffer circuit 41, and controls the conduction and non-conduction of the internal transistor P1 and transistor P2 through the selection signals MUX1 and MUX2, that is, controls the conduction and non-conduction of the two selection paths. The circuit structure and connection mode of the other multiplexers are similar, which will not be described one by one here.

[0035] Through Figure 2 It can be seen that the selection signals MUX1 and MUX2 are basically in opposite states, during the selection signal MUX1 is at a low level, the voltage Vgp at the control end of the transistor P1 is pulled to a low level, the selection path is turned on, while the selection signal MUX2 is at a high level, the path where the transistor P2 is located is turned off. When the selection signal MUX2 is at a high level, the voltage Vgp at the control end of the transistor P1 is pulled to a high level, the selection path is turned off, while the selection signal MUX1 is at a low level, the path where the transistor P2 is located is turned on. Thus, the pixel data O1 is provided to the data lines S1 and S2 in time to drive the corresponding column of pixel units. In Figure 2 Each time, the selection signal MUX1 needs to pull the voltage at the control end of the transistor high or low, which consumes a lot of electrical energy, and the electrical energy cannot be recycled, causing a lot of waste.

[0036] The multiplexer is improved in the utility model, and Figures 3-7The multiplexer, driver chip, and display device using it are described in detail below with reference to the accompanying drawings.

[0037] Figure 3 A circuit diagram of a multiplexer according to a first embodiment of the present invention is shown. Figure 4 It shows Figure 3 A schematic diagram of the waveforms of each signal in a multiplexer.

[0038] like Figure 3 As shown, the multiplexer 210 of this embodiment replaces... Figure 1 The multiplexer 30 in this embodiment is identical to the previous one and will not be described again here. The multiplexer 210 in this embodiment includes one input terminal and multiple output terminals, and two output terminals are taken as an example here. Each output terminal is connected to the input terminal as a selection path, so this embodiment includes two selection paths (selection path 220 and selection path 230). Each selection path includes a first switch, a switching unit 221 and an energy storage unit 222. Taking selection path 220 as an example, the first terminal and the second terminal of the first switch P1 are connected to the input terminal and the output terminal, respectively. The control terminal of the first switch P1 receives the selection control signal (MUX1) and controls the conduction and de-conduction of selection path 220 according to the selection control signal (MUX1). The energy storage unit 222 is connected to the control terminal of the first switch P1. Before the control terminal of the first switch P1 changes from high level to low level, it collects and stores the charge of the control terminal. Before the control terminal of the first switch P1 changes from low level to high level, it releases the charge to the control terminal of the first switch P1. Therefore, the charge of the first switch transistor is transferred away before the control terminal level needs to be pulled low, and the charge is replenished before the control terminal level needs to be pulled high, reducing the power required to drive the first switch transistor. Switching unit 221 is connected to the control terminal of the first switch transistor P1, and controls the transfer of charge between the energy storage unit 222 and the control terminal of the first switch transistor P1 through its own on / off switching. The first switch transistor includes a PMOS transistor or an NMOS transistor, which alternately turns on and off according to the selection control signal MUX1, transferring charge before turning off again after turning on, or before turning on again after turning off. When a PMOS transistor is used as the first switch transistor, its control terminal receives... Figure 2 MUX1 is used as the selection control signal, and when the NMOS transistor is used as the first switching transistor, its control terminal receives... Figure 2 The inverted signal of MUX1 is used as the selection control signal. In this embodiment... Figure 3 The example uses a PMOS transistor as the first switching transistor, but an NMOS transistor can also be used as the first switching transistor in practice.

[0039] Further, in the embodiment, the switch unit 221 includes a first switch K1 and a second switch K2. The first switch K1 is connected between the control terminal of the first switch tube P1 and the energy storage unit 222, and controls the transfer of the electric charge. The second switch K2 is connected between the control terminal of the first switch tube P1 and the providing terminal of the selection control signal MUX1, and controls the time when the selection control signal MUX1 is provided to the control terminal of the first switch tube P1, so as to control the conduction and the turn-off of the first switch tube P1. The switch state of the first switch K1 is opposite to the switch state of the second switch K2, that is, when the first switch K1 is turned on, the second switch K2 is turned off, and when the first switch K1 is turned off, the second switch K2 is turned on, which can be realized by the corresponding switch control signals of the two switches. When the first switch K1 is turned on and the selection control signal MUX1 is changed from invalid to valid, the electric charge collected at the control terminal of the first switch tube P1 is stored. When the first switch K1 is turned on and the selection control signal MUX1 is changed from valid to invalid, the stored electric charge is released to the control terminal of the first switch tube P1. When the selection control signal MUX1 is invalid, the first switch tube P1 is turned off, and when the selection control signal MUX1 is valid, the first switch tube P1 is turned on. During the period when the first switch K1 is turned off, the selection control signal MUX1 is transmitted to the control terminal of the first switch tube P1 through the second switch K2, and the conduction and the turn-off of the first switch tube P1 are controlled by the selection control signal MUX1.

[0040] Specifically, Figure 3In the embodiment, the first switch tube is a PMOS tube, and the first switch tube P1 is turned off when the control end is at high level. Before the high level of the control end of the PMOS tube is changed to low level after the first switch K1 is turned on and the second switch K2 is turned off by the switch control signals RE and REB, part of the charge on the control end of the PMOS tube is transferred to the energy storage unit 222. Then the first switch K1 is turned off and the second switch K2 is turned on, and the control end of the PMOS tube is pulled to low level by the selection control signal MUX1. Since part of the charge has been transferred to the energy storage unit 222, it is easy to pull the level of the control end of the first switch tube P1 to low level, and the power consumption is small. When the control end of the first switch tube P1 is at low level, the PMOS tube is turned on. Before the low level of the control end of the PMOS tube is changed to high level after the first switch K1 is turned on and the second switch K2 is turned off by the switch control signals RE and REB, the charge on the energy storage unit 222 is transferred to the control end of the PMOS tube. Thus, when the control end of the PMOS tube is pulled to high level by the selection control signal MUX1 after the first switch K1 is turned off and the second switch K2 is turned on, the PMOS tube can be quickly pulled to high level. Similarly, when the first switch tube is an NMOS tube, the NMOS tube is turned on when the control end is at high level. Before the high level of the control end of the NMOS tube is changed to low level, the control end of the NMOS tube is transferred to the energy storage unit 222 by turning on the first switch K1 and turning off the second switch K2. When the control end of the first switch tube is at low level, the NMOS tube is turned off. Before the low level of the control end of the NMOS tube is changed to high level, the charge on the energy storage unit 222 is transferred to the control end of the NMOS tube by turning on the first switch K1 and turning off the second switch K2. Thus, the collection and reuse of the charge can be realized, that is, the recycling of the charge is realized, and the effect of saving power is achieved.

[0041] Further, in the embodiment, the energy storage unit 222 includes a capacitor, which is connected between the first switch K1 and the ground. The type and number of the capacitor can be determined according to actual conditions. The use of the capacitor to realize the energy storage unit can make the charge be collected and released faster, and the performance is higher.

[0042] As Figure 4As shown, before time t1, the selection control signal MUX1 is high, the switch control signal RE is low, and the switch control signal REB is high. The first switch K1 is open, the second switch K2 is on, and the control terminal of the first switching transistor P1 is pulled high, putting the transistor in the off state. At time t1, the switch control signal RE is high, the switch control signal REB is low, the first switch K1 is on, the second switch K2 is open, and the charge at the control terminal of the first switching transistor P1 begins to partially transfer to the capacitor, where the voltage stabilizes at Vc. Between time t1 and time t2, the selection control signal MUX1 jumps to low. At time t2, the switch control signal RE is low, the switch control signal REB is high, the first switch K1 is open, the second switch K2 is on, and the control terminal of the first switching transistor P1 is pulled low, putting the transistor in the on state. At time t3, the switch control signal RE is high and the switch control signal REB is low. The first switch K1 is turned on, and the second switch K2 is turned off, causing the charge on the capacitor to begin transferring to the control terminal of the first switching transistor P1. Between time t3 and time t4, the selection control signal MUX1 jumps to a high level. At time t4, the switch control signal RE is low and the switch control signal REB is high. The first switch K1 is turned off, the second switch K2 is turned on, and the level at the control terminal of the first switching transistor P1 is pulled high, putting the transistor in the off state. This process is then repeated to achieve the repeated recycling of charge.

[0043] Figure 5 A circuit diagram of a multiplexer according to a second embodiment of the present invention is shown. Figure 6 It shows Figure 5 A schematic diagram of the waveforms of each signal in a multiplexer.

[0044] like Figure 5 As shown, the multiplexer in this embodiment also includes two or more selection paths, each selection path including a first switch, a switching unit, and an energy storage unit. Taking selection path 220 as an example, it includes a first switch P1, a switching unit 221, and an energy storage unit 222. The switching unit 221 includes a first switch K1 and a second switch K2, which are related to... Figure 3The same parts are not described again. The difference is that in this embodiment, the selection path 220 further comprises a second transistor N1, the first end and the second end of the second transistor N1 are connected to the input end and the output end respectively, the control end of the second transistor N1 is connected to the control end of the first transistor P1 through the first switch K1, and the control end of the second transistor N1 is used as the energy storage unit 222. The charge is transferred between the control end of the first transistor and the control end of the second transistor. In addition, the second transistor N1 can also control the conduction and turn-off of the selection path, that is, the second transistor N1 is synchronously turned on and turned off with the first transistor P1, which can reduce the conduction impedance. Further, the switch unit 221 further comprises a third switch K3, and the control end of the second transistor N1 receives the inverted signal of the selection control signal MUX1 through the third switch K3. For example, the selection control signal MUX1 is connected to the control end of the second transistor N1 through the third switch K3 after passing through the inverter. The third switch K3 receives the same switch control signal REB as the second switch K2 and is synchronously turned on and turned off.

[0045] In this embodiment, the types of the first transistor and the second transistor are opposite, that is, the first transistor is one of a PMOS transistor and an NMOS transistor, and the second transistor is the other one of the PMOS transistor and the NMOS transistor. Here, the first transistor P1 is taken as a PMOS transistor and the second transistor N1 is taken as an NMOS transistor as an example. Of course, the NMOS transistor can also be regarded as the first transistor N1, and the PMOS transistor can also be regarded as the second transistor P1. Then, the charge of the control end of the first transistor can be transferred to the control end of the second transistor, and the charge of the control end of the second transistor can also be transferred to the control end of the first transistor. That is, taking any one of the transistors as the first transistor, the control end of the other transistor can be regarded as the energy storage unit, and the charge is transferred between the control ends of the two transistors. The driving energy when the two transistors are turned on can be reduced. The following will be described in combination with the waveform diagram of FIG. 6. Figure 6

[0046] As shown in FIG. 6, the selection control signal MUX1 is a pulse signal, and the inverted signal of the selection control signal MUX1 is also a pulse signal. The selection control signal MUX1 is connected to the control end of the first transistor P1 through the first switch K1, and the inverted signal of the selection control signal MUX1 is connected to the control end of the second transistor N1 through the third switch K3. The switch control signal REB is connected to the control end of the first switch K1 and the control end of the third switch K3. The switch control signal REB is a pulse signal, and the inverted signal of the switch control signal REB is also a pulse signal. Figure 6 ​As shown, before the time t1, the selection control signal MUX1 is high, the switch control signal RE is low, the switch control signal REB is high, the first switch K1 is off, the second switch K2 and the third switch K3 are on, the control end of the first switch tube P1 is pulled high, and the control end of the second switch tube N1 is pulled low, and both the PMOS tube and the NMOS tube are in the off state. At the time t1, the switch control signal RE is high, the switch control signal REB is low, the first switch K1 is on, the second switch K2 and the third switch K3 are off, the charge at the control end of the first switch tube P1 starts to transfer to the control end of the second switch tube N1, and the potentials of the two control ends are the same. Before the time t2 after the time t1, the selection control signal MUX1 jumps to low. At the time t2, the switch control signal RE is low, the switch control signal REB is high, the first switch K1 is off, the second switch K2 and the third switch K3 are on, the control end of the first switch tube P1 is pulled low, and the control end of the second switch tube N1 is pulled high, and both the PMOS tube and the NMOS tube are in the on state, and the selection path 220 is on. In this process, due to the transfer of the charge, the potentials of the control ends of the two transistors are at the intermediate potential, so that the on of the transistors can be quickly realized, and the selection control signal MUX1 only needs to drive the potential of the control end from the intermediate potential to high or from the intermediate potential to low, thereby saving a large amount of electric energy and achieving the purpose of saving electricity. After that, at the time t3, the switch control signal RE is high, the switch control signal REB is low, the first switch K1 is on, the second switch K2 and the third switch K3 are off, the charge at the control end of the second switch tube N1 starts to transfer to the control end of the first switch tube P1, and the potentials of the two control ends reach the same time and stop, both of which are at the intermediate potential. Before the time t4 after the time t3, the selection control signal MUX1 jumps to high. At the time t4, the switch control signal RE is low, the switch control signal REB is high, the first switch K1 is off, the second switch K2 and the third switch K3 are on, the control end of the first switch tube P1 is pulled high from the intermediate potential, and the control end of the second switch tube N1 is pulled low from the intermediate potential, and both the PMOS tube and the NMOS tube are in the off state, and the selection path 220 is off. In this process, the potentials of the two control ends are at the intermediate potential, which can be quickly pulled high or low to realize fast response, and the selection control signal MUX1 only needs to drive the potential of the control end from the intermediate potential to high or from the intermediate potential to low, thereby saving a large amount of electric energy. Then the above process is repeated to realize the repeated utilization of the charge.

[0047] In the embodiment, the second switch tube can not only store charges as an energy storage unit, but also serve as a conduction control unit of a selection path, so that the conduction and turn-off of the two switch tubes are more easy, and the conduction impedance on the selection path can be reduced. Replacing the capacitor with the second switch tube can reduce the circuit area, reduce the cost, and reduce the conduction impedance, so that the conduction and turn-off of the selection path are more easy, and the response speed is improved.

[0048] Figure 7 A schematic diagram of a driving chip and a display device according to an embodiment of the present application is shown.

[0049] The multiplexer in the embodiment can also be integrated in a driving chip, as shown in Figure 7 The driving chip 200 includes a source driver 201, an output selection circuit 202, and a timing controller 203, and in some embodiments, a gate driver 204. The driving chip 200 is located outside the display panel 100, and the output selection circuit 202 includes Figures 3-6 Any multiplexer is shown. The source driver 201 provides pixel data Data according to image data, and performs data transmission with the data lines of the display area. The output end of the source driver 201 is connected to a plurality of data lines S1, S2, …, Sm via the output selection circuit 202, and the pixel array of the display area 100 is controlled by the plurality of data lines. The gate driver 204 is connected to the pixel array of the display area 100 through a plurality of scan lines G1, G2, …, Gn. The driving chip can be a display driving chip used in a display device, or the driving chip can be a touch and display driving integrated chip, i.e., a TDDI (Touch and Display Driver Integration) chip.

[0050] The embodiment also provides a display device, which includes a display panel and a driving chip 200, and the driving chip 200 is located outside the display panel. The display panel includes a display area 100 and a plurality of data lines, the display area 100 includes a pixel array, and the pixel array includes a plurality of columns of sub-pixel units, and each data line is connected to a column of sub-pixel units. One sub-pixel unit 101 is shown in the figure, and the actual sub-pixel unit 101 is arranged in an array.

[0051] The multiplexer, the driving chip using the multiplexer, and the display device of the embodiment of the present application, by the setting of the switch unit and the energy storage unit, the charges at the control end of the first switch tube are stored and reused, while improving the response speed, the effect of saving power is realized.

[0052] Finally, it should be noted that the above-mentioned embodiments are merely intended for the purpose of illustration, and are not intended to limit the embodiments. Based on the above descriptions, those skilled in the art can further make other variations and changes of different forms. Here, it is not necessary or possible to enumerate all the embodiments. The obvious variations and changes derived therefrom are still within the scope of the present application.

Claims

1. A multiplexer comprising an input and a plurality of outputs, each output having a select path between the input and the output, characterised in that, Each of the selection paths comprises: a first switch tube, first and second ends of the first switch tube being connected to the input end and the output end respectively, a control end of the first switch tube receiving a selection control signal, and the first switch tube being controlled according to the selection control signal to control a conduction state of the selection path; an energy storage unit connected to the control end of the first switch tube, the energy storage unit collecting and storing electric charges of the control end when the control end is disconnected from the selection control signal and in a high level state, and the energy storage unit releasing the electric charges to the control end of the first switch tube when the control end is disconnected from the selection control signal and in a low level state; and a switch unit connected to the control end of the first switch tube, the switch unit controlling a transfer of the electric charges between the energy storage unit and the control end of the first switch tube by switching on and off.

2. The multiplexer of claim 1, wherein, The first switch tube comprises a PMOS tube or an NMOS tube, and the first switch tube is switched between a conduction state and an off state according to the control of the selection control signal.

3. The multiplexer of claim 1, wherein, The switch unit comprises: a first switch connected between the control end of the first switch tube and the energy storage unit to control the transfer of the electric charges; and a second switch connected between the control end of the first switch tube and a supply end of the selection control signal to control a connection path between the selection control signal and the control end of the first switch tube, so as to control the conduction and the off of the first switch tube, wherein the switching state of the first switch and the switching state of the second switch are opposite.

4. The multiplexer of claim 3, wherein: when the first switch is switched on and the selection control signal is changed from invalid to valid, the electric charges of the control end of the first switch tube are collected and stored; when the first switch is switched on and the selection control signal is changed from valid to invalid, the stored electric charges are released to the control end of the first switch tube; and during the off of the first switch, the selection control signal is transmitted to the control end of the first switch tube through the second switch, and the conduction and the off of the first switch tube are controlled by the selection control signal, the first switch tube is off when the selection control signal is invalid, and the first switch tube is on when the selection control signal is valid.

5. The multiplexer of claim 3, wherein, when the control end of the first switch tube is in a high level, the PMOS tube is off, and before the high level of the control end of the PMOS tube is changed to a low level, the first switch is switched on and the second switch is switched off, and the electric charges of the control end of the PMOS tube are partially transferred to the energy storage unit; when the control end of the first switch tube is in a low level, the PMOS tube is on, and before the low level of the control end of the PMOS tube is changed to a high level, the first switch is switched on and the second switch is switched off, and the electric charges of the energy storage unit are transferred to the control end of the PMOS tube.

6. The multiplexer of claim 3, wherein, The first switch tube is an NMOS tube, the NMOS tube is turned on when the control end of the first switch tube is high, the first switch is turned on and the second switch is turned off before the high level of the control end of the NMOS tube is changed to low level, and part of the charge of the control end of the NMOS tube is transferred to the energy storage unit; The first switch tube is an NMOS tube, the NMOS tube is turned on when the control end of the first switch tube is high, the first switch is turned on and the second switch is turned off before the high level of the control end of the NMOS tube is changed to low level, and part of the charge of the control end of the NMOS tube is transferred to the energy storage unit; 7. The multiplexer according to any one of claims 3-6, wherein, The energy storage unit includes a capacitor connected between the first switch and the ground terminal.

8. The multiplexer of any of claims 3-6, wherein, Each of the selection paths further includes: A second switch tube, the first end and the second end of the second switch tube are connected to the input terminal and the output terminal respectively, the control end of the second switch tube is connected to the control end of the first switch tube through the first switch, and the energy storage unit includes the control end of the second switch tube.

9. The multiplexer of claim 8, wherein, Each of the selection paths further includes: A third switch, the control end of the second switch tube receives the inverted signal of the selection control signal through the third switch, and the second switch tube is turned on and turned off synchronously with the first switch tube.

10. The multiplexer of claim 9, wherein, The first switch tube is one of a PMOS tube and an NMOS tube, and the second switch tube is the other of the PMOS tube and the NMOS tube.

11. A driver chip, characterized by comprising: It includes: A source driver, which provides pixel data according to image data and performs data transmission with data lines of a display area; And The multiplexer according to any one of claims 1-10, the source driver is connected to a plurality of the data lines through the multiplexer, and a pixel array of a display area is controlled through a plurality of the data lines.

12. The driving chip according to claim 11, characterized in that, The driving chip includes a display driving chip and a touch and display driving integrated chip.

13. A display device comprising: It includes: A display panel, the display panel includes a pixel array and a plurality of data lines, the pixel array includes a plurality of columns of sub-pixel units, and each data line is connected to a column of sub-pixel units; And The multiplexer according to any one of claims 1-10, the input terminal of the multiplexer is connected to a source driver, the output terminal of the multiplexer is connected to a plurality of the data lines, and the pixel array is controlled through a plurality of the data lines, Wherein, the source driver and the multiplexer are integrated in the same chip and located outside the display panel.

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