Hardware delay detection circuit capable of collecting and displaying delay time

Abstract

The utility model provides a hardware delay detection circuit capable of collecting and displaying delay time, relates to the technical field of relay delay control, and solves the problem of limitation of existing delay sampling in the aspects of operation, efficiency, processing speed and precision. The circuit structure comprises a delay acquisition circuit, a timer circuit, a counter circuit, an encoder circuit, a decoder circuit and a display nixie tube which are connected in sequence. The delay acquisition circuit is also connected with the delay control board; the delay acquisition circuit is used for acquiring delay time and outputting the delay time to the timer circuit, the timer circuit is used for generating counting signals and outputting the counting signals to the counter circuit, and the counter circuit is used for counting counting characteristics and outputting the counting characteristics in a decimal signal form; the decimal signals are converted into seven-segment codes through the encoder circuit and the decoder circuit in sequence, and then the seven-segment codes are output to the display nixie tube, and the corresponding delay time is displayed. According to the utility model, acquisition and display of delay time are realized through a pure hardware circuit design mode.

Description

Technical Field

[0001] This utility model relates to the field of relay delay control technology and is applied in the process of delay time acquisition. Specifically, it relates to a hardware delay detection circuit that can acquire and display delay time. Background Technology

[0002] In modern industrial automation control systems, relays are widely used as key components in the safety control and signal transmission processes of various devices. Among these, the emergency stop function is crucial for ensuring safe equipment operation and protecting the lives of operators. To meet the needs of certain application scenarios, such as avoiding accidental triggering or achieving smooth shutdown, some system designs incorporate mechanisms for delaying emergency stop signals. This mechanism is typically implemented using specially designed delay boards, the core of which is precisely controlling the time interval between receiving the emergency stop signal and receiving a response.

[0003] However, in practical applications, detecting the operating status and performance of these delay boards has become a technical challenge. Traditionally, technicians rely on oscilloscopes for measurement. While this method provides relatively accurate results, it is complex and inefficient, especially when multiple samples need to be tested frequently, significantly limiting production efficiency. Furthermore, current mainstream delay sampling methods mostly employ microprocessor units (MCUs) in conjunction with software algorithms to read and process time data, then output the results to display devices such as digital tubes. This approach not only increases system complexity but also requires operators to possess certain programming knowledge and technical backgrounds, further increasing labor costs and training burdens.

[0004] More importantly, existing technical solutions have limitations in terms of data processing speed and accuracy. Because data conversion and calculation are involved at the software level, additional delays and errors are inevitably introduced. This can lead to discrepancies between the final delay measurement value and the actual value, affecting the accuracy of determining whether a delay board is qualified. At the same time, such a process is also difficult to meet the higher demands of the rapidly evolving market for product testing efficiency and quality.

[0005] Therefore, developing a more efficient, convenient, and accurate time delay measurement tool is particularly urgent. This tool should be able to directly test relay time delay boards, quickly obtaining reliable measurement results without complex operating procedures or extensive programming knowledge, thereby significantly improving the efficiency of production inspection and product quality control. Utility Model Content

[0006] The purpose of this invention is to solve the problems of complex operation and low efficiency of oscilloscopes in existing technologies, as well as the slow data processing speed and limited accuracy of MCU chips for delay sampling. Therefore, a hardware delay detection circuit capable of acquiring and displaying delay time is proposed. This invention, through a pure hardware circuit design, achieves delay time acquisition and display without relying on microcontroller units and software programming, thereby effectively improving the work efficiency and product quality control level of the production inspection process.

[0007] The present invention employs the following technical solution to achieve its objective:

[0008] A hardware delay detection circuit capable of acquiring and displaying delay time includes a delay acquisition circuit, a timer circuit, a counter circuit, an encoder circuit, a decoder circuit, and a digital display tube connected in sequence. The delay acquisition circuit is also connected to a delay control board to be tested. The delay acquisition circuit acquires the delay time of the delay control board and outputs it to the timer circuit. The timer circuit generates a counting signal and outputs it to the counter circuit. The counter circuit counts the counting features in the counting signal and outputs the counting result as a decimal signal. The decimal signal passes through the encoder circuit and the decoder circuit in sequence, is converted into a seven-segment code, and then output to the digital display tube to display the corresponding delay time.

[0009] Preferably, the input terminal of the delay acquisition circuit receives a high-level signal, and the delay acquisition circuit is used to transmit the high-level signal to the input terminal of the timer circuit; the duration of the high-level signal characterizes the delay time of the delay control board.

[0010] Optionally, the input terminal of the delay acquisition circuit is connected to the high-level signal output terminal of the relay delay control board; the high-level signal output terminal of the relay delay control board continuously outputs a high-level signal before the relay state switches.

[0011] Preferably, after receiving a high-level signal input, the timer circuit generates a square wave signal as the counting signal; the square wave signal has a preset signal period, and the duration of the square wave signal is the same as the duration of the high-level signal.

[0012] Specifically, the counting characteristic in the square wave signal is the rising edge of each square wave; the counter circuit counts the number of square waves within the duration of the square wave signal, and outputs the total number of square waves obtained after counting to the encoder circuit in the form of a decimal signal.

[0013] Specifically, the counter circuit has three counters connected in sequence. The input terminal of the first counter is connected to the output terminal of the timer circuit and receives the input of the counting signal. The output terminal of each counter is also connected to a second inverter. The output terminals of multiple second inverters serve as the output terminals of the counter circuit, outputting the decimal signal obtained after counting to the encoder circuit.

[0014] Specifically, the encoder circuit is used to convert decimal signals into BCD codes and output them to the decoder circuit, and the decoder circuit is used to convert BCD codes into seven-segment codes and output them to the display digital tube.

[0015] Preferably, the BCD code is an 8421 BCD code.

[0016] Specifically, the encoder circuit has three encoders and three first inverters connected in a one-to-one correspondence. The output of the encoder is connected to the input of the corresponding first inverter, and the output of the first inverter is connected to the decoder circuit. The three encoders are used to convert the hundreds, tens and units digits of the decimal signal, which represent the delay time in milliseconds, respectively.

[0017] Specifically, the decoder circuit has three decoders, each of which is connected to a single-digit display tube. The three decoders are connected to the three first inverters in the encoder circuit. The three decoders are used to convert the 8421 BCD code representing the hundreds, tens and units digits into seven-segment codes and output them to the corresponding connected display tubes, so that the display tubes can display the delay time including the hundreds, tens and units digits.

[0018] In summary, due to the adoption of this technical solution, the beneficial effects of this utility model are as follows:

[0019] This invention adopts a pure hardware circuit design, which does not rely on MCU or complex software programming, thus reducing circuit complexity and operation difficulty. This design not only reduces costs, but also enables non-professionals to easily operate and maintain the equipment, thereby improving the user experience.

[0020] To improve measurement accuracy, this invention employs the principle of level duration to acquire delay time and converts this information into a standard signal form that is easy to process at the circuit level. This method can, to some extent, avoid delays and errors in traditional data processing, ensuring the accuracy and reliability of the measurement results. Furthermore, by converting the delay time into a square wave signal of a specific frequency on the hardware circuit and directly reading the square wave count using a counter, the speed and accuracy of data acquisition are further improved.

[0021] To facilitate intuitive reading of the delay time by users, this invention employs a digital tube display. Through a series of encoding conversions, the raw measurement data is transformed into a format suitable for digital tube display, thereby achieving real-time visual display of the delay time. This feature significantly enhances user convenience, making the test results immediately clear without requiring additional data interpretation or calculation steps. Attached Figure Description

[0022] Figure 1 This is a schematic diagram showing the composition and signal transmission of the hardware delay detection circuit of this utility model;

[0023] Figure 2 This is a schematic diagram of the electrical connection structure of a simulated example of this utility model;

[0024] Figure 3 This is a simulation diagram of the delay detection effect of the hardware delay detection circuit of this utility model. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0027] Example 1

[0028] like Figure 1 As shown, a hardware delay detection circuit capable of acquiring and displaying delay time includes a delay acquisition circuit, a timer circuit, a counter circuit, an encoder circuit, a decoder circuit, and a digital display tube connected in sequence. The delay acquisition circuit is also connected to a delay control board to be tested. The delay acquisition circuit acquires the delay time of the delay control board and outputs it to the timer circuit. The timer circuit generates a counting signal and outputs it to the counter circuit. The counter circuit counts the counting features in the counting signal and outputs the counting result in decimal form. The decimal signal passes through the encoder circuit and the decoder circuit in sequence, is converted into a seven-segment code, and then output to the digital display tube to display the corresponding delay time.

[0029] In this embodiment, the input terminal of the delay acquisition circuit receives a high-level signal, and the delay acquisition circuit is used to transmit the high-level signal to the input terminal of the timer circuit; the duration of the high-level signal characterizes the delay time of the delay control board.

[0030] As an optional example of this embodiment, the hardware delay detection circuit can be used to monitor the relay delay control board, collect and display its delay time. For the relay delay control board, when it is triggered and performs a delay operation, it can generate and acquire a high-level signal until the delay is completed and the relay state switches; therefore, its high-level signal output terminal continuously outputs a high-level signal before the relay state switches, thereby characterizing the delay time. The input terminal of the delay acquisition circuit is also connected to the high-level signal output terminal of the relay delay control board.

[0031] The hardware delay detection circuit in this embodiment is described using a relay as the delay detection object. If it is necessary to measure the delay of other types of devices, it can be achieved simply by changing the corresponding connection structure of the delay acquisition circuit.

[0032] In a preferred embodiment, after receiving a high-level signal input, the timer circuit generates a square wave signal as the counting signal. The square wave signal has a preset signal period. In this embodiment, the signal period of the square wave signal is determined to be 1ms, and the duration of the square wave signal is the same as the duration of the high-level signal.

[0033] The counting characteristic of a square wave signal is the rising edge of each square wave; the counter circuit counts the number of square waves within the duration of the square wave signal, and outputs the total number of square waves obtained after counting to the encoder circuit in the form of a decimal signal.

[0034] As a specific structural reference, the counter circuit in this embodiment is described as follows: The counter circuit has three counters connected in sequence, wherein the input terminal of the first counter is connected to the output terminal of the timer circuit and receives the input of the counting signal; the output terminal of each counter is also connected to a second inverter, and the output terminals of multiple second inverters serve as the output terminals of the counter circuit, outputting the decimal signal obtained after counting to the encoder circuit.

[0035] In this embodiment, the encoder circuit converts the decimal signal into BCD code and outputs it to the decoder circuit. The decoder circuit converts the BCD code into a seven-segment code and outputs it to the display tube. As a specific example, the BCD code used is 8421 BCD code.

[0036] As a specific structural reference, the encoder circuit and decoder circuit of this embodiment are described as follows: The encoder circuit has three encoders and three first inverters connected in a one-to-one correspondence. The output terminal of the encoder is connected to the input terminal of the corresponding first inverter, and the output terminals of the first inverters are all connected to the decoder circuit; the three encoders are respectively used to convert the hundreds, tens and units digits of the 8421 BCD code in the decimal signal, which represent the delay time in milliseconds.

[0037] The decoder circuit has three decoders, each of which is connected to a single-digit display tube. The three decoders are connected to the three first inverters in the encoder circuit. The three decoders are used to convert the 8421 BCD code representing the hundreds, tens and units digits into seven-segment codes and output them to the corresponding connected display tubes, so that the display tubes can display the delay time including the hundreds, tens and units digits.

[0038] Example 2

[0039] Based on Example 1, this example provides a schematic diagram of the electrical connection structure, using the core circuit structure and specific structural references from Example 1. It also offers guidance on selecting relevant components. Detailed electrical connection relationships can be found in [reference needed]. Figure 2 The illustration.

[0040] like Figure 2 As shown, section A, which is marked, is used to simulate the emergency stop and recovery states of a relay. This corresponds to the delay acquisition circuit of the hardware delay detection circuit and its connected delay control board. In this embodiment, it is a relay delay control board. Section B is the timer circuit, section C is the counter circuit, section D is the encoder circuit, and section F is the decoder circuit and the connected digital display tube.

[0041] This embodiment uses a total of 3 single-digit display LEDs. Figure 2 The LEDs are labeled LED1, LED2, and LED3, and their model number is FJ5161AH. The three single-digit display LEDs are used to display the hundreds, tens, and units digits of the delay time, respectively. The delay time unit is milliseconds (ms). Therefore, the delay time acquisition and display range of this embodiment is 1-999ms.

[0042] In Part A, connectors CN1 and CN2 are connected to the corresponding terminals of the relay delay control board. Before switch SW2 is closed, transistors Q1, Q2, and Q3 are not conducting. At this time, pin 4 of timer U2 (model NE555) in Part B is at a low level. When switch SW2 is closed, the relay delay control board will be powered on and start the delay (pin 1 of connector CN1 is connected to an emergency stop signal; the closing and opening of switch SW2 can simulate the emergency stop and recovery of the relay). At the same time, NPN transistor Q2 in Part A is turned on, and the base of PNP transistor Q1 is turned on. When the base of transistor Q1 is pulled low, transistor Q1 also conducts. After transistor Q1 conducts, resistors R5 and R9 are connected in series to divide the voltage, so pin 4 of timer U2 is at a high level. However, transistor Q3 is not conducting because its base is also pulled low (this is because pin 3 of connector CN2 is connected to the normally closed contact of the relay, so the base of transistor Q3 is pulled low and cannot conduct). After a delay, the emergency stop signal controls the relay to switch, and the base level of transistor Q3 changes from low to high, transistor Q3 conducts, and pin 4 of timer U2 is pulled low. Therefore, the duration of the high level on pin 4 of timer U2 is the delay time.

[0043] Part B serves as a timer circuit. When part A sets pin 4 of timer U2 high, it outputs a square wave signal of a specific period, which is 1ms in this embodiment. When pin 4 of timer U2 returns to a low level, timer U2 stops outputting the square wave signal. The frequency and duty cycle of the output square wave are calculated as follows:

[0044] Frequency: f = 1 / T = 1.44 / (R11*C3 + 2R10*C3);

[0045] Duty cycle: D = tl / T = R10 / (R11 + 2R10).

[0046] Section C serves as a counter circuit, containing counters U4, U5, and U15, all of which are of the same model, CD4017BM / TR. Counter U4 counts at the rising edge of the square wave, and its maximum count is 9. When it reaches 10, pin 12 of counter U4 outputs a carry signal. Therefore, the same counters U5 and U15 are used sequentially to measure the tens and hundreds digits.

[0047] In this embodiment, as Figure 2 As shown, the output bit of counter U4 is high when decoding is present and low when decoding is absent. Since the input ports of the subsequent encoder circuit components are statically high, and low levels have higher priority than high levels, therefore... Figure 2 The inverters U6, U7, U8, and U16 (all model 74HC14D, 653; also corresponding to the second inverter described in Example 1) are used to change the state of the counter. The connection method can be found in [reference needed]. Figure 2 The illustration.

[0048] Part D serves as the encoder circuit, with encoders U9, U10, and U17 all being 8421 BCD encoders, model CD74HC147M. These three encoders convert decimal signals into 8421 BCD code. Since devices that directly convert decimal signals to seven-segment codes are rare and expensive, failing to meet the cost considerations of this embodiment, the encoder circuit performs a conversion here. The truth table for the converted 8421 BCD code is the opposite of that for the seven-segment code; therefore, inverters U11, U12, and U18 (all model 74HC14D, 653; also corresponding to the first inverter described in Embodiment 1) are used to correspond to the respective truth tables.

[0049] Section F serves as the decoder circuit. Decoders U13, U14, and U19 are seven-segment encoders, all model CD4511BDRG. These three decode the 8421 BCD code into the corresponding seven-segment code, which is then output to the corresponding display digital tube to show the delay time.

[0050] In summary, the working principle of the circuit structure scheme in this embodiment can be described as follows:

[0051] The hardware delay detection circuit determines the specific delay time by monitoring the duration of the high-level signal before the relay switches on the relay delay control board. The delay time is converted into a square wave signal with a period of 1ms by timer U2. Counters U4, U5, and U15 obtain a decimal signal by measuring the number of rising edges of the square wave. Inverters U6, U7, U8, and U16 invert the decimal signal to obtain the signal required by the 8421 BCD encoder. Encoders U9, U10, and U17 then convert the decimal number into a binary number. Since the truth tables of encoders U9, U10, and U17 are opposite to those of the seven-segment encoder (i.e., decoders U13, U14, and U19), inverters U11, U12, and U18 are used to match their truth tables. After decoders U13, U14, and U19 convert the binary code into the seven-segment code required by the display digital tube, the display digital tube can then display the corresponding delay time.

[0052] Figure 3 This is a schematic diagram of a simulation test effect of the circuit structure in this embodiment. Figure 3 As can be seen, when the simulation delay time is set to 34.769ms, the circuit structure simulation of this embodiment successfully acquired and displayed a 34ms delay on the tens and units digits of the display tube, which meets the application requirements of actual engineering testing.

Claims

1. A hardware delay detection circuit capable of acquiring and displaying delay time, characterized in that: The delay time acquisition circuit is connected with the delay time control board to be detected, and is used to acquire the delay time of the delay time control board and output to the timer circuit; the timer circuit is used to generate a counting signal and output to the counter circuit; the counter circuit is used to count the counting characteristics in the counting signal and output the counting result in the form of a decimal signal; the decimal signal is converted into a seven-segment code by the encoder circuit and the decoder circuit, and then output to the display nixie tube to display the corresponding delay time.

2. The hardware delay detection circuit of claim 1, wherein: The input end of the delay time acquisition circuit receives the input of a high-level signal, and the delay time acquisition circuit is used to transmit the high-level signal to the input end of the timer circuit; the duration of the high-level signal represents the delay time of the delay time control board.

3. The hardware delay detection circuit of claim 2, wherein: The input end of the delay time acquisition circuit is connected with the high-level signal output end of the relay delay time control board; the high-level signal output end of the relay delay time control board continuously outputs a high-level signal before the state of the relay is switched.

4. The hardware delay detection circuit of claim 2, wherein: After receiving the input of the high-level signal, the counting signal generated by the timer circuit is a square wave signal; the square wave signal has a preset signal period, and the duration of the square wave signal is the same as that of the high-level signal.

5. The hardware delay detection circuit of claim 4, wherein: The counting characteristics in the square wave signal are the rising edges of each square wave; the counter circuit counts the number of square waves in the duration of the square wave signal, and outputs the total number of square waves obtained after counting in the form of a decimal signal to the encoder circuit.

6. The hardware delay detection circuit of claim 1, wherein: The counter circuit has three counters connected in sequence, wherein the input end of the first counter is connected with the output end of the timer circuit and receives the input of the counting signal; the output end of each counter is also connected with a second inverter, and the outputs of the multiple second inverters are used as the output end of the counter circuit to output the decimal signal obtained after counting to the encoder circuit.

7. The hardware delay detection circuit of claim 1, wherein: The encoder circuit is used to convert the decimal signal into a BCD code and output to the decoder circuit, and the decoder circuit is used to convert the BCD code into a seven-segment code and output to the display nixie tube.

8. The hardware delay detection circuit of claim 6, wherein: The BCD code is an 8421 BCD code.

9. The hardware delay detection circuit of claim 7, wherein: The encoder circuit has three encoders and three first inverters connected one by one, the output end of the encoder is connected with the input end of the corresponding first inverter, and the output end of the first inverter is connected to the decoder circuit; the three encoders are respectively used to convert the 8421 BCD code of the hundredth, tenth and unit delay time represented in the decimal signal into the 8421 BCD code.

10. The hardware delay detection circuit of claim 8, wherein: The decoder circuit has three decoders, each of which is connected with a 1-digit display nixie tube; the three decoders are connected with the three first inverters in the encoder circuit, and the three decoders are respectively used to convert the 8421 BCD code representing the hundredth, tenth and unit into a seven-segment code and output to the corresponding display nixie tube, so that the display nixie tube displays the delay time including the hundredth, tenth and unit.

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