Novel high-voltage charge pump for display driving chip

Abstract

The utility model provides a novel high-voltage charge pump for a display driving chip, which provides three-rate charges and is characterized by comprising a first PMOS switch M1 (1), a third PMOS switch M3 (3), a fifth PMOS switch M5 (5), a seventh PMOS switch M7 (7), a second NMOS switch M2 (2), a fourth NMOS switch M4 (4), a sixth PMOS switch M6 (6), an eighth NMOS switch M8 (8) and a fly-line capacitor, the drain electrode of the first PMOS switch M1 (1) is connected with a power supply VSP, the source electrode of the first PMOS switch M1 (1) is connected with an upper polar plate C1 of the fly-line capacitor (9), and the drain electrode of the second PMOS switch M1 (1) is connected with a lower polar plate C1 of the fly-line capacitor (9). And the grid electrode is connected with a first time sequence signal CLK1. The three-rate charge supply circuit is simple in structure, provides three-rate charges with a small area, and can provide more-rate charges through cascade expansion according to specific needs.

Description

Technical Field

[0001] This utility model belongs to the field of chips, specifically to the field of display driver chips, and particularly to a novel charge pump for use inside a display driver chip. Background Technology

[0002] Display driver ICs often use charge pumps for voltage boosting. A traditional three-rate charge pump structure is as follows: Figure 1 As shown.

[0003] like Figure 1 As shown, a conventional triple-rate charge pump contains seven MOS switches, M1 to M7, controlled by clock signals CLK1, CLK2, CLK1B, and CLK2B; Cfly1 and Cfly2 are flying lead capacitors, Cout is the load capacitor; VSP is the power supply voltage; GND is the reference ground with a voltage of 0.

[0004] The timing sequence of clock signals CLK1, CLK2, CLK1B, and CLK2B during charge pump operation is as follows: Figure 2 As shown, CLK1 and CLK1B, and CLK2 and CLK2B are two sets of inverted clocks. CLK1 and CLK2 are two-phase non-overlapping clocks. The non-overlapping clock ΔT is used to ensure that the two sets of switches M2 and M4, and M5 and M7 connected to the power supply will not be turned on at the same time.

[0005] Assuming the initial voltage across each capacitor is 0, the working principle of a traditional three-rate charge pump is as follows:

[0006] like Figure 2 As shown, the charge pump operates in two phases, A and B, within one clock cycle. Phase A is the charging phase: during phase A, M1, M2, M6, and M7 are turned on, while M3, M4, and M5 are turned off. Power supplies VSP and GND charge the flying lead capacitor Cfly1, while flying lead capacitor Cfly2 and load capacitor Cout share the charge. Ignoring the on-resistance of the switching transistors, the voltage VA at point A and the voltage VB at point B are charged to VSP and GND, respectively. At the end of phase A, the voltage difference between the upper and lower plates of flying lead capacitor Cfly1 is ΔV = VA - VB = VSP, while the voltage difference between the upper and lower plates of flying lead capacitor Cfly2 and load capacitor Cout remains 0.

[0007] Phase B is the discharge phase: During phase B, M1, M2, M6, and M7 are off, while M3, M4, and M5 are on. Due to the conservation of charge in the flying lead capacitor Cfly1, the voltage difference ΔV between the upper and lower plates of Cfly1 remains constant at VSP, i.e., ΔV = VA - VB = VSP. VB changes from 0 to VSP, thus VA is boosted to 2 × VSP. At this time, switch M3 is on, and flying lead capacitors Cfly1 and Cfly2 share charge. After several cycles, the voltage VC at point C will be charged to 2 × VSP. In the next phase B, M7 is closed. Due to the conservation of charge in flying lead capacitor Cfly2, VC is boosted to 3 × VSP, VC = VOUT = 3 × VSP, achieving a 3x voltage boost function.

[0008] The above analysis shows that a single-stage flying wire in a traditional charge pump structure can only generate a one-time voltage boost. However, in real-world applications, display driver ICs often require several times the voltage boost. For example, an eight-times voltage boost would require an eight-stage charge pump, which includes eight flying wire capacitors. This would increase the chip area and introduce parasitic effects that would affect circuit performance.

[0009] Currently, there is a need in existing technologies for providing sufficient charge with fewer flying wire capacitors and a smaller chip area, for example, for... Figure 1 The triple-rate charge pump requires an improved technical solution. Utility Model Content

[0010] To address the technical deficiencies of existing technologies, the purpose of this utility model is to provide a novel high-voltage charge pump for a display driver chip, which provides a three-fold power boost. Its features include a first PMOS switch M1, a third PMOS switch M3, a fifth PMOS switch M5, a seventh PMOS switch M7, a second NMOS switch M2, a fourth NMOS switch M4, a sixth PMOS switch M6, an eighth NMOS switch M8, and a flying lead capacitor. Specifically, the drain of the first PMOS switch M1 is connected to the power supply VSP, its source is connected to the upper plate C1 of the flying lead capacitor, and its gate is connected to the first timing signal CLK1. The source of the second NMOS switch M2 is connected to the power supply VSN, and its gate is connected to the second timing signal CLK2. The drain of the third PMOS switch M3 is connected to the power supply ground, and its gate is connected to the third timing signal CLK3. The drain of the fourth NMOS switch M4 is connected to the power supply ground. The lower electrode C2 of the flying lead capacitor is connected to the gate of the fourth timing signal CLK4; the drain of the second NMOS switch M2, the source of the third PMOS switch M3, and the source of the fourth NMOS switch M4 are connected at the first connection point X; the drain of the fifth PMOS switch M5 is connected to C1, the source is connected to the output terminal VOUT of the charge pump, and the gate is connected to the fifth timing signal CLK5; the drain of the sixth PMOS switch M6 is connected to C2, and the gate is connected to the sixth timing signal CLK6; the source of the seventh PMOS switch M7 is connected to the power supply VSP, and the gate is connected to the seventh timing signal CLK7; the drain of the eighth NMOS switch M8 is connected to the power supply ground, and the gate is connected to the eighth timing signal CLK8; the source of the sixth PMOS switch M6, the drain of the seventh PMOS switch M7, and the source of the eighth NMOS switch M8 are connected at the second connection point Y.

[0011] Preferably, the fourth timing signal CLK4 and the sixth timing signal CLK6 are normally low signals, and the second NMOS switch M2 and the third PMOS switch M3, the seventh PMOS switch M7 and the eighth NMOS switch M8 will not be turned on simultaneously.

[0012] Preferably, the first PMOS switch M1 and the fifth PMOS switch M5, the third PMOS switch M3 and the seventh PMOS switch M7 are not turned on simultaneously. The fourth NMOS switch M4 and the sixth PMOS switch M6 are normally turned on to short-circuit the first connection point X and the second connection point Y. The second timing signal CLK2 and the eighth timing signal CLK8 are normally low to normally turn off the second NMOS switch M2 and the eighth NMOS switch M8 and to shield the power supply VSN, thereby providing a double-rate power boost.

[0013] This novel charge pump improves the output voltage by increasing the voltage difference between the upper and lower plates of the flying lead capacitor during the charging phase, thus refining the boost mode and achieving a three-fold boost from a single capacitor stage. This reduces the number of required flying lead capacitors and charge pump stages, saving circuit area. By adding breakdown-resistant MOSFET switches (the fourth NMOS switch M4 and the sixth PMOS switch M6) to the circuit, the voltage withstand capability issues of the second NMOS switch M2 and the seventh PMOS switch M7 in the novel charge pump structure are resolved. The breakdown-resistant MOSFET switches, namely the fourth NMOS switch M4 and the sixth PMOS switch M6, use an adaptive clock for switching on and off, further reducing circuit area and power consumption. This patent is compatible with both three-rate and two-rate outputs, allowing selection based on specific application scenarios and broadening its applicability.

[0014] The present invention has a simple implementation method, high cost performance, and can effectively solve the above-mentioned technical problems, and has extremely high commercial value. Attached Figure Description

[0015] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0016] Figure 1 A schematic diagram of the circuit structure of a conventional three-rate charge pump in the prior art is shown;

[0017] Figure 2 A signal timing diagram of a conventional three-rate charge pump in the prior art is presented;

[0018] Figure 3 A schematic diagram of the unit circuit structure of the novel charge pump according to the first embodiment of the present invention is shown;

[0019] Figure 4 A signal timing diagram of the novel charge pump provided according to the first embodiment of the present invention in triple-rate mode is shown;

[0020] Figure 5 A signal timing diagram of the novel charge pump according to a second embodiment of the present invention in double-rate mode is shown; and

[0021] Figure 6 A schematic diagram of the unit circuit structure of the novel charge pump in double-rate mode according to the second embodiment of the present invention is shown. Detailed Implementation

[0022] To better illustrate the technical solution of this utility model, the following description, in conjunction with the accompanying drawings, will further explain this utility model.

[0023] The novel charge pump unit designed in this utility model is as follows: Figure 3 As shown, it includes eight MOS switches M1 to M8, among which the fourth PMOS switch M4 and the sixth PMOS switch M6 are adaptive isolation switches used to solve the voltage withstand problem of the new structure; M1 to M8 are controlled by timing signals CLK1 to CLK8 respectively; VSP is the positive power supply voltage, VSN is the negative power supply voltage, VSN = -VSP; Cfly is a flying lead capacitor.

[0024] The drain of the first PMOS switch M1 is connected to the power supply VSP, the source is connected to the upper plate of the flying lead capacitor C1, and the gate is connected to the first timing signal CLK1; the source of the second NMOS switch M2 is connected to the power supply VSN, and the gate is connected to the second timing signal CLK2; the drain of the third PMOS switch M3 is connected to the power supply ground, and the gate is connected to the third timing signal CLK3; the drain of the fourth NMOS switch M4 is connected to the lower plate of the flying lead capacitor C2, and the gate is connected to the fourth timing signal CLK4; wherein the drain of the second NMOS switch M2, the source of the third PMOS switch M3, and the source of the fourth NMOS switch M4 are connected to the first time-series signal CLK1. Point X is connected; the drain of the fifth PMOS switch M5 is connected to C1, the source is connected to the output terminal VOUT of the charge pump, and the gate is connected to the fifth timing signal CLK5; the drain of the sixth PMOS switch M6 is connected to C2, and the gate is connected to the sixth timing signal CLK6; the source of the seventh PMOS switch M7 is connected to the power supply VSP, and the gate is connected to the seventh timing signal CLK7; the drain of the eighth NMOS switch M8 is connected to the power supply ground, and the gate is connected to the eighth timing signal CLK8; the source of the sixth PMOS switch M6, the drain of the seventh PMOS switch M7, and the source of the eighth NMOS switch M8 are connected at the second connection point Y.

[0025] refer to Figure 4 , Figure 5 This utility model has two working modes: a 3x working mode and a 2x working mode.

[0026] refer to Figure 3 , Figure 4 In the triple-rate operating mode, the novel charge pump provided by this invention provides triple-rate charge. Correspondingly, when the charge pump is in the triple-rate operating mode, the timing signals CLK1 to CLK8 are as follows: Figure 4 As shown, the fourth timing signal CLK4 and the sixth timing signal CLK6 are normally low signals; the non-overlapping times ΔT1 and ΔT2 are used to ensure that the two sets of switches connected to the power supply, the second NMOS switch M2 and the third PMOS switch M3, the seventh PMOS switch M7 and the eighth NMOS switch M8, will not be turned on at the same time.

[0027] Furthermore, such as Figure 4As shown, the charge pump operates in two phases within one clock cycle: Phase A and Phase B. Phase A is the charging phase. In Phase A, the first PMOS switch M1 and the second NMOS switch M2 are turned on, while the third PMOS switch M3 is turned off. At this time, the voltage at the first connection point X is VX = VSN. The gate-source voltage V of the fourth NMOS switch M4 is... GS4 =0 -VSN = VSP, which is greater than the NMOS turn-on voltage. The fourth NMOS switch M4 adaptively turns on, and the power supply VSP and VSN charge the flying lead capacitor Cfly. The voltage difference between the upper and lower plates ΔV = V C1 -V C2 =VSP-VSN=2×VSP; The fifth PMOS switch M5 and the seventh PMOS switch M7 are turned off, and the eighth NMOS switch M8 is turned on, pulling the voltage VY at point Y down to ground, VY=0, to avoid the HIGH-Z state at point Y; At this time, the gate-source voltage VGS6 of M6 = 0-VSN=VSP, which is a positive value. The sixth PMOS switch M6 is adaptively turned off, isolating point Y from point C2, to avoid the drain-source voltage V of the seventh PMOS switch M7 during the charging of the flying capacitor Cfly. DS7 In the case where VSP - VSN = 2 × VSP, the voltage withstand problem of the switching transistor is solved;

[0028] Phase B is the discharge phase. The first PMOS switch M1 and the second NMOS switch M2 are turned off, stopping the power supply from charging Cfly. The third PMOS switch M3 is turned on, pulling point X down to ground, VX = 0, preventing point X from entering a HIGH-Z state. At this time, the gate-source voltage VGS4 of the fourth NMOS switch M4 is 0, less than the NMOS turn-on voltage. The fourth NMOS switch M4 adaptively turns off, isolating point X from point C2, preventing the voltage difference VDS2 = VSP - VSN = 2 × VSP across the source and drain of the second NMOS switch M2 during the discharge of the flying lead capacitor Cfly, thus solving the voltage withstand problem of the switch. The fifth PMOS switch M5 and the seventh PMOS switch M7 are turned on, and the eighth NMOS switch M8 is turned off, raising VY to VSP. At this time, the gate-source voltage VGS6 of the sixth PMOS switch M6 is -VSP, greater than the PMOS turn-on voltage. The sixth PMOS switch M6 adaptively turns on, V... C2 =VY=VSP; Due to the conservation of charge in Cfly, the pressure difference between the upper and lower plates of Cfly, ΔV=V C1 -V C2 =2×VSP remains unchanged, VC2=VSP, therefore V OUT =V C1 =3×VSP, achieving a three-fold voltage boost for a single-stage capacitor.

[0029] refer to Figure 5 , Figure 6In the second embodiment, when the novel charge pump provided by this invention is in double-rate operating mode, the timing signals CLK1 to CLK8 are as follows: Figure 5 As shown, the non-overlapping clock ΔT is used to ensure that the two sets of switches, namely the first PMOS switch M1 and the fifth PMOS switch M5, and the third PMOS switch M3 and the seventh PMOS switch M7, will not be turned on simultaneously; the second timing signal CLK2 and the eighth timing signal CLK8 are normally low, the second NMOS switch M2 and the eighth NMOS switch M8 are normally off, and the power supply VSN is shielded; the fourth timing signal CLK4 is normally high, the sixth timing signal CLK6 is normally low, the fourth NMOS switch M4 and the sixth PMOS switch M6 are normally on, and C2 is shorted to X and Y. The equivalent circuit diagram is shown below. Figure 6 As shown.

[0030] The charge pump operates in two phases within one clock cycle: Phase A and Phase B. Phase A is the charging phase: During Phase A, the first PMOS switch M1 and the third PMOS switch M3 are turned on, while the fifth PMOS switch M5 and the seventh PMOS switch M7 are turned off. Power supplies VSP and GND charge the flying lead capacitor Cfly, and the voltage at point C1 is V. C1 and the voltage V at point C2 C2 They are charged to VSP and GND respectively. At the end of stage A, the voltage difference between the upper and lower plates of the flying capacitor Cfly is ΔV = V. C1 -V C2 =VSP.

[0031] Phase B is the discharge phase: During phase B, M1 and M3 are off, and the fifth PMOS switch M5 and the seventh PMOS switch M7 are on. Due to the conservation of charge in the flying lead capacitor Cfly, the voltage difference between the upper and lower plates of the flying lead capacitor Cfly remains constant at VSP, i.e., ΔV = V. C1 -V C2 =VSP, VC2 changes from 0 to VSP, therefore VC1 is raised to 2×VSP. V C1 =V OUT =2×VSP, to achieve the function of doubling the voltage.

[0032] The specific embodiments of this utility model have been described above. It should be understood that this utility model is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the substantive content of this utility model.

Claims

1. A novel high-voltage charge pump for display driver ICs providing a tripler power boost, characterized in that, comprise a first PMOS switch M1(1), a third PMOS switch M3(3), a fifth PMOS switch M5(5), a seventh PMOS switch M7(7), a second NMOS switch M2(2), a fourth NMOS switch M4(4), a sixth PMOS switch M6(6), an eighth NMOS switch M8(8), and a flying capacitor, wherein the first PMOS switch M1(1) is connected to a power supply VSP at the drain, to the upper plate C1 of the flying capacitor (9) at the source, and to a first timing signal CLK1 at the gate; the second NMOS switch M2(2) is connected to a power supply VSN at the source, and to a second timing signal CLK2 at the gate; the third PMOS switch M3(3) is connected to a power supply ground at the drain, and to a third timing signal CLK3 at the gate; the fourth NMOS switch M4(4) is connected to the lower plate C2 of the flying capacitor (9) at the drain, and to a fourth timing signal CLK4 at the gate; the drain of the second NMOS switch M2(2), the source of the third PMOS switch M3(3), and the source of the fourth NMOS switch M4(4) are connected at a first connection point X; the fifth PMOS switch M5(5) is connected to C1 at the drain, to the output VOUT of the charge pump at the source, and to a fifth timing signal CLK5 at the gate; the sixth PMOS switch M6(6) is connected to C2 at the drain, and to a sixth timing signal CLK6 at the gate; the seventh PMOS switch M7(7) is connected to the power supply VSP at the source, and to a seventh timing signal CLK7 at the gate; the eighth NMOS switch M8(8) is connected to the power supply ground at the drain, and to an eighth timing signal CLK8 at the gate; the source of the sixth PMOS switch M6(6), the drain of the seventh PMOS switch M7(7), and the source of the eighth NMOS switch M8(8) are connected at a second connection point Y.

2. The novel high-voltage charge pump according to claim 1, characterized in that, The fourth timing signal CLK4 and the sixth timing signal CLK6 are always low signals, and the second NMOS switch M2(2) and the third PMOS switch M3(3), the seventh PMOS switch M7(7) and the eighth NMOS switch M8(8) are not turned on at the same time.

3. A novel high-voltage charge pump according to claim 1 or 2, characterized in that, The first PMOS switch M1(1) and the fifth PMOS switch M5(5), the third PMOS switch M3(3) and the seventh PMOS switch M7(7) are not turned on at the same time, the fourth NMOS switch M4(4) and the sixth PMOS switch M6(6) are always on to short connect the first connection point X and the second connection point Y, the second timing signal CLK2 and the eighth timing signal CLK8 are always low signals to always turn off the second NMOS switch M2(2) and the eighth NMOS switch M8(8), and to shield the power supply VSN, thereby providing a two-fold power supply boost.

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