Semiconductor device

Abstract

Various embodiments of the utility model relate to a semiconductor device. The semiconductor device comprises a first active region layer extending along a first direction; a first over-diffusion metal layer extending in a second direction different from the first direction, the first over-diffusion metal layer being over the first active region layer; a first polysilicon gate contact extending in a second direction over the first active region layer; a first polysilicon end of the first polysilicon gate contact adjoining the first dielectric region; and a first low-k dielectric material in the first dielectric region.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] Generally, devices such as transistors are arranged adjacent to each other in a plane (e.g., the xy plane) of a semiconductor device. In some devices, complementary transistors are arranged adjacent to each other, such that one transistor is a p-type transistor and the adjacent transistor is an n-type transistor. A complementary transistor includes an active region (also referred to herein as an oxide diffusion (OD) layer) separated in the x or y direction and a gate region connected through a gate contact.

[0003] A stacked complementary field-effect transistor (CFET) comprises another transistor type (e.g., a p-type transistor) stacked on top of one transistor type (e.g., an n-type transistor). Stacked CFETs increase the cell area by 50%, where the active regions of the transistors are separated in the z-direction, and the gate regions are connected via gate contacts. Furthermore, the interconnects of the stacked CFETs are located in the z-direction. Typically, stacked CFET devices are used in semiconductor devices that include back-side wiring or power rails. Utility Model Content

[0004] One embodiment of this invention provides a semiconductor device. The semiconductor device includes a first active region layer extending along a first direction. The semiconductor device also includes a first diffusion-over-metal layer extending along a second direction different from the first direction, the first diffusion-over-metal layer being located above the first active region layer. The semiconductor device further includes a first polysilicon gate contact extending along the second direction above the first active region layer. The semiconductor device also includes a first polysilicon end of the first polysilicon gate contact adjacent to a first dielectric region. The semiconductor device also includes a first low-k dielectric material located within the first dielectric region.

[0005] Another aspect of this utility model provides a semiconductor device. The semiconductor device includes a first cell and a second cell. The first cell includes: a first active region layer extending along a first direction; a first diffusion-over-metal layer extending along a second direction perpendicular to the first direction, the first diffusion-over-metal layer being located above the first active region layer; a first polysilicon gate contact extending along the second direction above the first active region layer; and a first polysilicon end of the first polysilicon gate contact adjacent to a first dielectric region. The second cell includes: a second active region layer extending along the first direction; a second diffusion-over-metal layer extending along the second direction above the second active region layer; a second polysilicon gate contact extending along the second direction above the second active region layer; a second polysilicon end of the second polysilicon gate contact adjacent to a second dielectric region; and a third polysilicon end of the second polysilicon gate contact in the second cell adjacent to the first dielectric region.

[0006] Another aspect of this invention provides a method for manufacturing a semiconductor device. The method includes forming an active region layer extending along a first direction. The method further includes forming a polysilicon gate contact including a polysilicon end and extending over the active region in a second direction different from the first direction. The method also includes forming a dielectric region adjacent to the polysilicon end, wherein forming the dielectric region includes: a first portion of the dielectric region having a high-k dielectric material; and a second portion of the dielectric region having a low-k dielectric material.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating a semiconductor device including a 2D CMG region according to some embodiments, wherein the 2D CMG region cuts the polysilicon gate contact to provide a shortened polysilicon end.

[0009] Figure 2 This is a schematic diagram illustrating the dimensions of a semiconductor device according to some embodiments.

[0010] Figure 3 This is a schematic diagram illustrating a semiconductor device including a first semiconductor device and a second semiconductor device according to some embodiments.

[0011] Figure 4 This is an illustrative representation according to some embodiments. Figure 3 A cross-sectional view of the semiconductor device taken along line AA.

[0012] Figure 5This is a schematic diagram illustrating a semiconductor device according to some embodiments, including a 2D CMG region at least partially located in each of a first semiconductor device and a second semiconductor device.

[0013] Figure 6 This is an illustrative representation according to some embodiments. Figure 5 A cross-sectional view of the semiconductor device taken along line BB.

[0014] Figure 7 This is a schematic diagram illustrating a semiconductor device including a 2D CMG region according to some embodiments.

[0015] Figure 8 This is an illustrative representation according to some embodiments. Figure 7 A cross-sectional view of a semiconductor device taken along line CC.

[0016] Figure 9 This is a schematic diagram illustrating a semiconductor device including a 2D CMG region according to some embodiments, the 2D CMG region including a low-k dielectric and a high-k dielectric.

[0017] Figure 10 This is an illustrative representation according to some embodiments. Figure 9 A cross-sectional view of a semiconductor device taken along line DD.

[0018] Figure 11 This is a schematic diagram illustrating a semiconductor device including a 2D CMG region according to some embodiments, the 2D CMG region including a low-k dielectric and a high-k dielectric.

[0019] Figure 12 This is an illustrative representation according to some embodiments. Figure 11 A table of geometric dimensions of semiconductor devices.

[0020] Figure 13 This is a schematic diagram illustrating a semiconductor device having a CMG region pattern etched into the semiconductor device according to some embodiments.

[0021] Figure 14 This is a schematic diagram illustrating a pattern of CMG regions filled with a high-k dielectric according to some embodiments.

[0022] Figure 15 This is a schematic diagram illustrating the filling of space with a low-k dielectric according to some embodiments.

[0023] Figure 16 This is a schematic diagram illustrating an n-type transistor on the front side of a semiconductor device according to some embodiments.

[0024] Figure 17 This is a schematic diagram illustrating a p-type transistor on the back side of a semiconductor device according to some embodiments.

[0025] Figure 18 This is a schematic diagram showing the n-type transistors on the front of a semiconductor device connected as a 2-input NAND gate according to some embodiments.

[0026] Figure 19 This is a schematic diagram showing the p-type transistors on the back of a semiconductor device connected as a 2-input NAND gate according to some embodiments.

[0027] Figure 20 This is an illustrative representation of a semiconductor manufacturing apparatus according to some embodiments (e.g. Figures 13 to 15 A diagram of a method for using a semiconductor device.

[0028] Figure 21 This is a block diagram schematically illustrating an example of a computer system configured to provide the semiconductor apparatus and methods disclosed herein according to some embodiments.

[0029] Figure 22 This is a block diagram of a semiconductor device manufacturing system and a related semiconductor device manufacturing process according to some embodiments. Detailed Implementation

[0030] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the utility model description. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. Such repetition is for the purpose of brevity and clarity, and not to indicate any relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another. In addition to the orientations depicted in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0032] Each transistor in a CFET structure includes an active region that forms the source, drain, and channel. The channel is located below the gate, which has gate contacts. The active region is also called the OD layer. The active region layer of a complementary transistor can be separated in the x, y, or z directions.

[0033] Some CFET structures include active region merging cells, which include active region layers with expanded active region layer widths. This increases the effective device current capability of the active region merging cell. The active region layer of the active region merging cell has a larger width than the active region layer of a single-height cell. Furthermore, the active region merging cell has a larger cell height, such as 1.5 times the cell height or double the cell height. However, in the active region merging cell, there is a maximum width limitation on the active region layer, which results in a longer polysilicon gate contact from the active region layer to the first cut metal gate (CMG) region, where the CMG region is also referred to herein as the dielectric region. This results in a larger polysilicon end capacitance from the polysilicon gate contact to the metal over diffusion (MD) layer. A second CMG region may be located near the active region layer to provide a minimum length of polysilicon end from the active region layer to the second CMG region. However, as the cell height of the active region merged cells increases, the minimum spacing requirement between the first and second CMG regions cannot be maintained. Instead, the second CMG region is removed, resulting in a longer polysilicon end from the active region layer to the first CMG region, and a larger polysilicon end capacitor in the enlarged cell.

[0034] The disclosed embodiments provide a semiconductor device that minimizes the length of the polysilicon end extending from the active region layer of a cell to the CMG region, also referred to herein as the dielectric region of the cell. This reduces the polysilicon end capacitance, such as the polysilicon end capacitance from the polysilicon gate contact to the MD layer. In some embodiments, the polysilicon end capacitance is from the polysilicon gate contact in one cell to the MD layer in an adjacent cell. In some embodiments, the polysilicon end capacitance is from the polysilicon gate contact in one cell to the MD layer in another cell. In some embodiments, the polysilicon end capacitance is from the polysilicon gate contact in one cell to the active region layer in another cell.

[0035] The disclosed embodiments also provide a semiconductor device including a polysilicon gate contact and a CMG region (also referred to as a dielectric region), the CMG region abutting and cleaving the polysilicon gate contact to provide a shortened polysilicon end. The CMG region includes a first portion having a first width and a second portion having a second width greater than the first width, wherein the second portion abuts and cleaves the polysilicon gate contact at the shortened polysilicon end. A low-k dielectric material is located in the second portion of the CMG region, also referred to as the dielectric region. In some embodiments, the shortened polysilicon end is a minimum length polysilicon end. Furthermore, throughout this specification, the CMG region is also referred to as the dielectric region.

[0036] Figure 1 This is a schematic diagram illustrating a semiconductor device 20 including a 2D CMG region 22 (also referred to as dielectric region 22) according to some embodiments, the 2D CMG region 22 abutting and cleaving polysilicon gate contacts 24 and 26 to provide shortened polysilicon ends 28 and 30, respectively. In some embodiments, throughout the specification, the polysilicon gate contacts (e.g., polysilicon gate contacts 24 and 26) comprise a metal gate material. In some embodiments, each of the shortened polysilicon ends 28 and 30 has a minimum polysilicon end length L.

[0037] Semiconductor device 20 includes a 2D CMG region 22, polysilicon gate contacts 24 and 26, an active region layer 32, and an MD layer 34. The active region layer 32 extends in the x-direction, and the MD layer 34 extends in the y-direction perpendicular to the x-direction. The MD layer 34 is located above the active region layer 32. In other embodiments, the active region layer 32 extends in a first direction and the MD layer 34 extends in a second direction different from the first direction.

[0038] Polysilicon gate contacts 24 and 26 extend in the y-direction above the active region layer 32. A 2D CMG region 22 cuts the polysilicon gate contacts 24 and 26 to provide shortened polysilicon ends 28 and 30. This results in a smaller MD layer to the polysilicon end capacitances 36 and 38. The 2D CMG region 22 includes a low-dielectric-constant dielectric material (low-k dielectric material) 40.

[0039] The 2D CMG region 22 includes a first portion 42 having a first width W1 and a second portion 44 having a second width W2 greater than the first width W1. The second portion 44 cuts polysilicon gate contacts 24 and 26 to provide shortened polysilicon ends 28 and 30. A low-k dielectric material 40 is located in the second portion 44 of the 2D CMG region 22.

[0040] The 2D CMG region 22 includes a low-k dielectric material 40 within a high-k dielectric material 46. In some embodiments, the low-k dielectric is a dielectric material with a lower dielectric constant or k value than silicon dioxide (SiO2), where k < 3.9. In some embodiments, the high-k dielectric is a dielectric material with a higher dielectric constant or k value than SiO2, where k > 3.9.

[0041] Figure 2 This is a schematic diagram illustrating the dimensions of a semiconductor device 20 according to some embodiments. The height H of the semiconductor device 20 includes the CMG width (W1) A, two polysilicon end caps (PO end caps) C, the maximum active region width (Max active region width) D, and the CMG protrusion (W2-W1) E. The height H of the semiconductor device 20 having a 2D CMG region 22 is A + (C*2) + D + E.

[0042] Figure 3 This is a schematic diagram illustrating a semiconductor device 50 including a first semiconductor device 52 and a second semiconductor device 54 according to some embodiments. The first semiconductor device 52 is a CFET including one type of active region layer / transistor located above one type of active region layer / transistor in the z-direction, and the second semiconductor device 54 is a CFET including one type of active region layer / transistor located above one type of active region layer / transistor in the z-direction. The first semiconductor device 52 is separated from the second semiconductor device 54 in the y-direction. In some embodiments, each transistor in the first semiconductor device 52 and each transistor in the second semiconductor device 54 are similar to... Figure 1 Semiconductor device 20.

[0043] The top transistor in the first semiconductor device 52 and the top transistor in the second semiconductor device 54 each include a 2D CMG region 22, polysilicon gate contacts 24 and 26, an active region layer 32, and an MD layer 34. The active region layer 32 of the second semiconductor device 54 is separated from the active region layer 32 of the first semiconductor device 52 in the y-direction. The active region layer 32 extends in the x-direction, and the MD layer 34 extends in the y-direction perpendicular to the x-direction. Moreover, the MD layer 34 is located above the active region layer 32, and the polysilicon gate contacts 24 and 26 extend along the y-direction above the active region layer 32. The 2D CMG region 22 extends in the z-direction and cuts the polysilicon gate contacts 24 and 26 to provide shortened polysilicon ends 28 and 30, respectively. This results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor within each of the semiconductor devices 52 or 54 and between the semiconductor devices 52 and 54 and the other.

[0044] The 2D CMG region 22 includes a low-k dielectric material 40 and a high-k dielectric material 46. The 2D CMG region 22 includes a first portion 42 having a first width W1 and a second portion 44 having a second width W2 greater than the first width W1. The second portion 44 cuts through polysilicon gate contacts 24 and 26 to provide shortened polysilicon ends 28 and 30. The low-k dielectric material 40 is located within the second portion 44 of the 2D CMG region 22 and inside the high-k dielectric material 46.

[0045] Figure 4 This is an illustrative representation based on some embodiments. Figure 3 The diagram shows a cross-section 60 taken along line AA of the semiconductor device 50. Cross-section 60 includes a first semiconductor device 52 and a second semiconductor device 54.

[0046] The first semiconductor device 52 includes an MD layer 34 located on an active region layer 32, which is located on an insulating layer 62. The insulating layer 62 is located below the active region layer 32 and above a second active region layer 32'. The first semiconductor device 52 includes a bottom MD layer 34' below the second active region layer 32'. A CMG region 22 extends in the z-direction and includes a high-k dielectric 46 and a low-k dielectric 40. The CMG region 22 cleaves polysilicon gate contacts 24 and 26. In some embodiments, the polysilicon gate contacts 24 and 26 extend above the active region layer 32 and the second active region layer 32', and the CMG region 22 cleaves the polysilicon gate contacts 24 and 26 extending above the active region layer 32 and the second active region layer 32'. In some embodiments, the active region layer 32 is an n-type active region layer and the active region layer 32' is a p-type active region layer. In some embodiments, the active region layer 32 is a p-type active region layer and the active region layer 32' is an n-type active region layer.

[0047] The second semiconductor device 54 includes an MD layer 34 located on an active region layer 32, which is located on an insulating layer 64. The insulating layer 64 is located below the active region layer 32 and above the second active region layer 32'. The second semiconductor device 54 includes a bottom MD layer 34' below the second active region layer 32'. A CMG region 22 extends in the z-direction and includes a high-k dielectric 46 and a low-k dielectric 40. The CMG region 22 cleaves polysilicon gate contacts 24 and 26. In some embodiments, the polysilicon gate contacts 24 and 26 extend above the active region layer 32 and the second active region layer 32', and the CMG region 22 cleaves the polysilicon gate contacts 24 and 26 extending above the active region layer 32 and the second active region layer 32'. In some embodiments, the active region layer 32 is an n-type active region layer and the active region layer 32' is a p-type active region layer. In some embodiments, the active region layer 32 is a p-type active region layer and the active region layer 32' is an n-type active region layer.

[0048] Figure 5This is a schematic diagram illustrating a semiconductor device 70 including a 2D CMG region 72 at least partially located in each of a first semiconductor device 74 and a second semiconductor device 76, according to some embodiments. The first semiconductor device 74 is a CFET including a CFET of one type of active region layer / transistor located above one type of active region layer / transistor in the z-direction, and the second semiconductor device 76 is a CFET including a CFET of one type of active region layer / transistor located above one type of active region layer / transistor in the z-direction. The first semiconductor device 74 is separated from the second semiconductor device 76 in the y-direction. In some embodiments, each transistor in the first semiconductor device 74 and each transistor in the second semiconductor device 76 are similar to... Figure 1 Semiconductor device 20.

[0049] The top transistor in the first semiconductor device 74 and the top transistor in the second semiconductor device 76 each include polysilicon gate contacts 78 and 80, an active region layer 82, an MD layer 84, and at least a portion of a 2D CMG region 72. Furthermore, the top transistor in the second semiconductor device 76 includes a CMG region 86. The active region layer 82 of the second semiconductor device 76 is separated from the active region layer 82 of the first semiconductor device 74 in the y-direction. The active region layer 82 extends in the x-direction, and the MD layer 84 extends in the y-direction perpendicular to the x-direction. Moreover, the MD layer 84 is located above the active region layer 82, and the polysilicon gate contacts 78 and 80 extend in the y-direction above the active region layer 82. The 2D CMG region 72 extends in the z-direction and cuts through the polysilicon gate contacts 78 and 80 in each of the first semiconductor device 74 and the second semiconductor device 76 to provide shortened polysilicon ends 88 and 90. Furthermore, the CMG region 86 extends in the z-direction and cuts through the polysilicon gate contacts 78 and 80 in the second semiconductor device 76 to provide shortened polysilicon ends 92 and 94, respectively. This results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor within each of the semiconductor devices 74 and 76 and between the two semiconductor devices 74 and 76.

[0050] The 2D CMG region 72 includes a low-k dielectric material 96 and a high-k dielectric material 98. The 2D CMG region 72 includes a first portion 100 having a first width W1 and a second portion 102 having a second width W2 greater than the first width W1. The second portion 102 cuts polysilicon gate contacts 78 and 80 in each of the first semiconductor device 74 and the second semiconductor device 76 to provide shortened polysilicon ends 88 and 90. The low-k dielectric material 96 is located in the second portion 102 of the 2D CMG region 72 and is internal to the high-k dielectric material 98. Furthermore, the CMG region 86 has a third width W3 and includes the high-k dielectric material 98. In some embodiments, the first width W1 and the third width W3 are the same.

[0051] Figure 6 This is an illustrative representation according to some embodiments. Figure 5 The diagram shows a cross-section 110 taken along line BB of the semiconductor device 70. Cross-section 110 includes a first semiconductor device 74 and a second semiconductor device 76.

[0052] The first semiconductor device 74 includes an MD layer 84 located on an active region layer 82, which is located on an insulating layer 112. The insulating layer 112 is located below the active region layer 82 and above a second active region layer 82'. The first semiconductor device 74 includes a bottom MD layer 84' below the second active region layer 82'. A CMG region 72 extends in the z-direction and includes a high-k dielectric 98 and a low-k dielectric 96. The CMG region 72 cleaves polysilicon gate contacts 78 and 80. In some embodiments, the polysilicon gate contacts 78 and 80 extend above the active region layer 82 and the second active region layer 82', and the CMG region 72 cleaves the polysilicon gate contacts 78 and 80 extending above the active region layer 82 and the second active region layer 82'. In some embodiments, the active region layer 82 is an n-type active region layer and the active region layer 82' is a p-type active region layer. In some embodiments, active region layer 82 is a p-type active region layer and active region layer 82' is an n-type active region layer.

[0053] The second semiconductor device 76 includes an MD layer 84 located on an active region layer 82, which is located on an insulating layer 114. The insulating layer 114 is located below the active region layer 82 and above the second active region layer 82'. The second semiconductor device 76 includes a bottom MD layer 84' below the second active region layer 82'. A CMG region 72 extends in the z-direction and includes a high-k dielectric 98 and a low-k dielectric 96. The CMG region 72 cleaves polysilicon gate contacts 78 and 80. In some embodiments, the polysilicon gate contacts 78 and 80 extend above the active region layer 82 and the second active region layer 82', and the CMG region 72 cleaves the polysilicon gate contacts 78 and 80 extending above the active region layer 82 and the second active region layer 82'.

[0054] Furthermore, the second semiconductor device 76 includes a CMG region 86 extending in the z-direction and cleaving polysilicon gate contacts 78 and 80 in the second semiconductor device 76 to provide shortened polysilicon ends 92 and 94, respectively. In some embodiments, the polysilicon gate contacts 78 and 80 extend over the active region layer 82 and the second active region layer 82', and the CMG region 86 cleaves the polysilicon gate contacts 78 and 80 extending over the active region layer 82 and the second active region layer 82'. In some embodiments, the active region layer 82 is an n-type active region layer and the active region layer 82' is a p-type active region layer. In some embodiments, the active region layer 82 is a p-type active region layer and the active region layer 82' is an n-type active region layer.

[0055] Figure 7 This is a schematic diagram illustrating a semiconductor device 120 including a 2D CMG region 122 according to some embodiments. The semiconductor device 120 is a CFET comprising two active region layers, one type of active region layer / transistor positioned above the other type of active region layer / transistor in the z-direction. In some embodiments, each transistor in the semiconductor device 120 is similar to... Figure 1 Semiconductor device 20.

[0056] Semiconductor device 120 includes a 2D CMG region 122, polysilicon gate contacts 124 and 126, and an active region layer 128. Furthermore, semiconductor device 120 may include one or more MD layers (not shown). Active region layer 128 extends in the x-direction, and polysilicon gate contacts 124 and 126 extend in the y-direction perpendicular to the x-direction. Polysilicon gate contacts 124 and 126 extend over and surround the two active region layers in CFET semiconductor device 120, including active region layer 128.

[0057] The 2D CMG region 122 extends in the z direction and cuts the polysilicon gate contacts 124 and 126 to provide shortened polysilicon ends 128 and 130, respectively. This results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor within the semiconductor device 120 and between one semiconductor device (e.g., semiconductor device 120) and another.

[0058] The 2D CMG region 122 includes a high-k dielectric material 132. The 2D CMG region 122 includes a first portion 134 having a first width W1 and a second portion 136 having a second width W2 greater than the first width W1. The second portion 136 cuts the polysilicon gate contacts 124 and 126 to provide shortened polysilicon ends 128 and 130, respectively.

[0059] Figure 8 This is an illustrative representation according to some embodiments. Figure 7 The image shows a cross-section 140 taken along line CC of the semiconductor device 120. Cross-section 140 includes a portion of the semiconductor device 120 and the second device 142.

[0060] Semiconductor device 120 includes a polysilicon gate contact 126 surrounding an active region layer 128 and a second active region layer 128'. The polysilicon gate contact 126 is located on an insulating layer 144, which is located below the active region layer 128 and above the second active region layer 128'. A CMG region 122 extends in the z-direction and includes a high-k dielectric 132. The CMG region 122 cuts across the polysilicon gate contact 126 extending above the active region layer 128 and the second active region layer 128'. In some embodiments, the high-k dielectric 132 is silicon nitride (SiN) with a k-value of 6. In some embodiments, the active region layer 128 is an n-type active region layer and the active region layer 128' is a p-type active region layer. In some embodiments, the active region layer 128 is a p-type active region layer and the active region layer 128' is an n-type active region layer.

[0061] Figure 9 This is a schematic diagram illustrating a semiconductor device 150 including a 2D CMG region 152 according to some embodiments, the 2D CMG region 152 including a low-k dielectric 154 and a high-k dielectric 156. The semiconductor device 150 is a CFET comprising two active region layers, one type of active region layer / transistor located above the other type of active region layer / transistor in the z-direction. In some embodiments, each transistor in the semiconductor device 150 is similar to... Figure 1 Semiconductor device 20.

[0062] Semiconductor device 150 includes a 2D CMG region 152, polysilicon gate contacts 158 and 160, and an active region layer 162. Furthermore, semiconductor device 150 may include one or more MD layers (not shown). Active region layer 162 extends in the x-direction, and polysilicon gate contacts 158 and 160 extend in the y-direction perpendicular to the x-direction. Polysilicon gate contacts 158 and 160 extend over and around the two active region layers in CFET semiconductor device 150, including active region layer 162.

[0063] The 2D CMG region 152 extends in the z direction and cuts the polysilicon gate contacts 158 and 160 to provide shortened polysilicon ends 164 and 166, respectively. This results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor within the semiconductor device 150 and between one semiconductor device (e.g., semiconductor device 150) and between another semiconductor device.

[0064] The 2D CMG region 152 includes a low-k dielectric 154 and a high-k dielectric 156 surrounding the low-k dielectric 154 at least in the x and y directions. The 2D CMG region 152 includes a first portion 168 having a first width W1 and a second portion 170 having a second width W2 greater than the first width W1. The second portion 170 cuts through polysilicon gate contacts 158 and 160 to provide shortened polysilicon ends 164 and 166, respectively. The low-k dielectric 154 reduces capacitance across the 2D CMG region 152, such as capacitance from one of the polysilicon gate contacts 158 and 160 to an MD layer or active region layer in another device.

[0065] Figure 10 This is an illustrative representation according to some embodiments. Figure 9 A view of a cross-section 180 taken along line DD of the semiconductor device 150. Cross-section 180 includes a portion of the semiconductor device 150 and the second device 182.

[0066] Semiconductor device 150 includes a polysilicon gate contact 160 surrounding an active region layer 162 and a second active region layer 162'. The polysilicon gate contact 160 is located on an insulating layer 184, which is located below the active region layer 162 and above the second active region layer 162'. A CMG region 152 extends in the z-direction and includes a low-k dielectric 154 and a high-k dielectric 156 surrounding the low-k dielectric 154 at least in the x and y directions. The CMG region 152 cuts across the polysilicon gate contact 160 extending over the active region layer 162 and the second active region layer 162'. In some embodiments, the k-value of the high-k dielectric 156 is 6. In some embodiments, the low-k dielectric 154 has a k-value from 0 to 3.9. In some embodiments, the active region layer 162 is an n-type active region layer and the active region layer 162' is a p-type active region layer. In some embodiments, active region layer 162 is a p-type active region layer and active region layer 162' is an n-type active region layer.

[0067] Figure 11 and Figure 12 This is a schematic diagram illustrating the semiconductor device 200 and its geometry according to some embodiments. In some embodiments, a second semiconductor device is located above the semiconductor device 200 in the y-direction. In some embodiments, a second semiconductor device is located below the semiconductor device 200 in the y-direction.

[0068] Figure 11This is a schematic diagram illustrating a semiconductor device 200 including a 2D CMG region 202 according to some embodiments, the 2D CMG region 202 including a low-k dielectric 204 and a high-k dielectric 206. In some embodiments, the semiconductor device 200 is a CFET including two active regions, one type of active region layer / transistor being located above the other type of active region layer / transistor in the z-direction. In some embodiments, the semiconductor device 200 is similar to Figure 1 The semiconductor device 200. In some embodiments, the semiconductor device 200 is similar to... Figure 9 Semiconductor device 150.

[0069] Semiconductor device 200 includes a 2D CMG region 202, polysilicon gate contacts 208 and 210, and an active region layer 212. Furthermore, semiconductor device 200 may include one or more MD layers (not shown). The active region layer 212 extends in the x-direction, and the polysilicon gate contacts 208 and 210 extend in the y-direction perpendicular to the x-direction.

[0070] The 2D CMG region 202 extends in the z direction and cuts the polysilicon gate contacts 208 and 210 to provide shortened polysilicon ends 214 and 216, respectively. This results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor within the semiconductor device 200 and between one semiconductor device (e.g., semiconductor device 200) and between another semiconductor device.

[0071] The 2D CMG region 202 includes a low-k dielectric 204 and a high-k dielectric 206 surrounding the low-k dielectric 204 at least in the x and y directions. The low-k dielectric 204 reduces capacitance across the 2D CMG region 202, such as capacitance from one of the polysilicon gate contacts 208 and 210 to the MD layer or active region layer in the other device. The 2D CMG region 202 includes a first portion 218 having a first width W1 and a second portion 220 having a second width W2 greater than the first width W1. The second portion 220 cuts the polysilicon gate contacts 208 and 210 to provide shortened polysilicon ends 214 and 216, respectively.

[0072] Figure 12 This is an illustrative representation based on some embodiments. Figure 11 The geometric dimensions of the semiconductor device 200 are shown in Table 230.

[0073] Column A, 232 of Table 230 represents the CMG width W1 of the first portion 218, which in some embodiments ranges from 15 to 20 nanometers (nm). Column B, 234 of Table 230 represents the CMG protrusion with width W2 minus width W1, which in some embodiments ranges from 15 to 30 nm. Column C, 236 of Table 230 represents the spacing between the CMG region and the active region layer, which in some embodiments ranges from 10 to 15 nm. Column D, 238 of Table 230 represents the width of the low-k dielectric 204, which in some embodiments ranges from 15 to 30 nm. Furthermore, in some embodiments, the values ​​in column B, 234 are the same as those in column D, 238.

[0074] Column E 240 of Table 230 represents the distance from the edge of the CMG region 202 to the edge of the low-k dielectric 204, which in some embodiments ranges from 7.5 to 10 nm. Column F 242 of Table 230 represents the maximum width of the active region layer 212, which in some embodiments ranges from 50 to 70 nm. In some embodiments, the values ​​in column E 240 are the same as the values ​​in column A 232 divided by 2.

[0075] Figures 13 to 15 This is a schematic diagram illustrating a semiconductor device 250 according to some embodiments and a process for fabricating a 2D CMG region 252 comprising a high-k dielectric 254 and a low-k dielectric 256 in the semiconductor device 250. In some embodiments, the semiconductor device 250 is a CFET comprising two active regions, wherein one type of active region layer / transistor is located above another type of active region layer / transistor in the z-direction. In some embodiments, the semiconductor device 250 is similar to Figure 1 The semiconductor device 20. In some embodiments, the semiconductor device 250 is similar to... Figure 3 The semiconductor device 50. In some embodiments, the semiconductor device 250 is similar to... Figure 5 The semiconductor device 70. In some embodiments, the semiconductor device 250 is similar to... Figure 9 The semiconductor device 150. In some embodiments, the semiconductor device 250 is similar to... Figure 11 Semiconductor device 200.

[0076] Figure 13This diagram schematically illustrates a semiconductor device 250 having a CMG region pattern 258 etched into the semiconductor device 250 according to some embodiments. The semiconductor device 250 includes polysilicon gate contacts 260 and 262, an active region layer 264, and one or more MD layers (not shown). The active region layer 264 extends in the x-direction, and the polysilicon gate contacts 260 and 262 extend in the y-direction perpendicular to the x-direction. The polysilicon gate contacts 260 and 262 include metal gate material removed by etching the CMG region pattern 258 into the semiconductor device 250; that is, at least some metal gate material is removed by etching the CMG region pattern 258 into the semiconductor device 250.

[0077] CMG region pattern 258 includes a first portion 266 having a first width W1 and a second portion 268 having a second width W2 greater than the first width W1. The first portion 266 of CMG region pattern 258 extends in the z-direction and cuts through the polysilicon gate contact 260. The second portion 268 of CMG region pattern 258 extends in the z-direction and cuts through the polysilicon gate contact 262 to provide a shortened polysilicon end 270, which results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor within the semiconductor device 250 and between one semiconductor device (e.g., semiconductor device 250) and between another semiconductor device.

[0078] Figure 14 This is a schematic diagram illustrating the filling of the CMG region pattern 258 with a high-k dielectric 254 according to some embodiments. The CMG region pattern 258 is partially filled with the high-k dielectric 254, leaving a space 272, as indicated by the arrow, for the low-k dielectric 256.

[0079] Figure 15 This is a schematic diagram illustrating the filling of space 272 with low-k dielectric 256 according to some embodiments. The 2D CMG region 252 includes low-k dielectric 256 and high-k dielectric 254 surrounding the low-k dielectric 256 at least in the x and y directions. A second portion 268 of the CMG region pattern 258 includes low-k dielectric 256 and cuts the polysilicon gate contact 262 to provide a shortened polysilicon end 270. The low-k dielectric 256 reduces the capacitance across the 2D CMG region 252, such as the capacitance from one of the polysilicon gate contacts 262 to the MD layer or active region layer in another device.

[0080] Figure 16 and Figure 17This is a schematic diagram illustrating a semiconductor device 300 including a 2D CMG region 302 according to some embodiments. The 2D CMG region 302 includes a low-k dielectric 304 and a high-k dielectric 306. The semiconductor device 300 includes an n-type transistor located above a p-type transistor in the z-direction. The semiconductor device 300 is configured as a CFET inverter with a drive strength of 2. In some embodiments, the semiconductor device 300 is similar to Figure 1 The semiconductor device 20. In some embodiments, the semiconductor device 300 is similar to... Figure 3 The semiconductor device 50. In some embodiments, the semiconductor device 300 is similar to... Figure 5 The semiconductor device 70. In some embodiments, the semiconductor device 300 is similar to... Figure 9 The semiconductor device 150. In some embodiments, the semiconductor device 300 is similar to... Figure 11 Semiconductor device 200.

[0081] Figure 16 This is a schematic diagram illustrating an n-type transistor on the front side of a semiconductor device 300 according to some embodiments. The semiconductor device 300 includes a 2D CMG region 302, polysilicon gate contacts 308 and 310, an n-type active region layer 312, and an MD layer 314. The n-type active region layer 312 extends in the x-direction, and the polysilicon gate contacts 308 and 310 and the MD layer 314 extend in the y-direction perpendicular to the x-direction.

[0082] The 2D CMG region 302 extends in the z direction and cuts the polysilicon gate contacts 308 and 310 to provide shortened polysilicon ends 316 and 318, respectively, which results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor.

[0083] The 2D CMG region 302 includes a low-k dielectric 304 and a high-k dielectric 306 surrounding the low-k dielectric 304 at least in the x and y directions. The low-k dielectric 304 reduces capacitance across the 2D CMG region 302, such as capacitance from one of the polysilicon gate contacts 308 and 310 to the MD layer or active region layer in the other device. The 2D CMG region 302 includes a first portion 320 having a first width W1 and a second portion 322 having a second width W2 greater than the first width W1. The second portion 322 cuts the polysilicon gate contacts 308 and 310 to provide shortened polysilicon ends 316 and 318, respectively.

[0084] Semiconductor device 300 is configured as a CFET inverter with a drive strength of 2. Polysilicon gate contacts 308 and 310 are connected to input 324 via vias 326 and 328, respectively. A reference voltage VSS is connected to the MD layer 314 on one side of each of the polysilicon gate contacts 308 and 310 above the n-type active region layer 312. The other side of each polysilicon gate contact 308 and 310 is connected to output OUT via a contact 330 and a via 332. In some embodiments, a high-k dielectric 306 is connected to the reference voltage VSS.

[0085] Figure 17 This is a schematic diagram illustrating a p-type transistor on the back side of a semiconductor device 300 according to some embodiments. The semiconductor device 300 includes a 2D CMG region 302, polysilicon gate contacts 308 and 310, a p-type active region layer 312', and an MD layer 334. The p-type active region layer 312' extends in the x-direction, and the polysilicon gate contacts 308 and 310 and the MD layer 334 extend in the y-direction perpendicular to the x-direction.

[0086] The 2D CMG region 302 extends in the z-direction and cuts the polysilicon gate contacts 308 and 310 to provide shortened polysilicon ends 316 and 318, respectively. Furthermore, the 2D CMG region 302 includes a low-k dielectric 304 and a high-k dielectric 306 surrounding the low-k dielectric 304, and includes a first portion 320 having a first width W1 and a second portion 322 having a second width W2 greater than the first width W1, wherein the second portion 322 cuts the polysilicon gate contacts 308 and 310 to provide shortened polysilicon ends 316 and 318, respectively.

[0087] Semiconductor device 300 is configured as a CFET inverter with a drive strength of 2. A power supply voltage VDD is connected to the MD layer 334 on one side of each of the polysilicon gate contacts 308 and 310, above the p-type active region layer 312'. The other side of each polysilicon gate contact 308 and 310 is connected to the output OUT via a contact 330. In some embodiments, a high-k dielectric 306 is connected to the power supply voltage VDD.

[0088] Figure 18 and Figure 19This diagram schematically illustrates a semiconductor device 340 according to some embodiments, which is a 2-input NAND gate including a 2D CMG region 342. The 2D CMG region 342 includes a low-k dielectric 344 and a high-k dielectric 346. The semiconductor device 340 includes an n-type transistor located above a p-type transistor in the z-direction. The semiconductor device 340 is configured as a 2-input NAND gate with a drive strength of 2. In some embodiments, the semiconductor device 340 is configured as a 2-input NAND gate with a drive strength of 4. In some embodiments, the semiconductor device 340 is similar to... Figure 1 The semiconductor device 20. In some embodiments, the semiconductor device 340 is similar to... Figure 3 The semiconductor device 50. In some embodiments, the semiconductor device 340 is similar to... Figure 5 The semiconductor device 70. In some embodiments, the semiconductor device 340 is similar to... Figure 9 The semiconductor device 150. In some embodiments, the semiconductor device 340 is similar to... Figure 11 Semiconductor device 200.

[0089] Figure 18 This is a schematic diagram illustrating the n-type transistors on the front side of a semiconductor device 340 connected as a 2-input NAND gate according to some embodiments. The semiconductor device 340 includes a 2D CMG region 342, polysilicon gate contacts 348, 350, 352, and 354, an n-type active region layer 356, and MD layers 358, 360, 362, 364, and 366. The n-type active region layer 356 extends in the x-direction, and the polysilicon gate contacts 348, 350, 352, and 354, as well as the MD layers 358, 360, 362, 364, and 366, extend in the y-direction perpendicular to the x-direction.

[0090] The 2D CMG region 342 extends in the z direction and cuts polysilicon gate contacts 348, 350, 352 and 354 to provide shortened polysilicon ends 368, 370, 372 and 374 respectively, which results in a smaller MD layer to the polysilicon end capacitor and a smaller active region layer to the polysilicon end capacitor.

[0091] The 2D CMG region 342 includes a low-k dielectric 344 and a high-k dielectric 346 surrounding the low-k dielectric 344 at least in the x and y directions. The low-k dielectric 344 reduces capacitance across the 2D CMG region 342, such as capacitance from one of the polysilicon gate contacts 348, 350, 352, and 354 to an MD layer or active region layer in another device. The 2D CMG region 342 includes a first portion 376 having a first width W1 and a second portion 378 having a second width W2 greater than the first width W1. The second portion 378 cuts the polysilicon gate contacts 348, 350, 352, and 354 to provide shortened polysilicon ends 368, 370, 372, and 374, respectively.

[0092] Semiconductor device 340 is connected as a 2-input NAND gate with a drive strength of 2. Polysilicon gate contacts 350 and 352 are connected to input A1 380 via vias 382 and 384, respectively. Polysilicon gate contacts 348 and 354 are connected to input A2 386 via vias 388 and 390, respectively. A reference voltage VSS is connected to MD layers 358 and 366 above an n-type active region layer 356 on one side of each of the polysilicon gate contacts 348 and 354. The other side of each polysilicon gate contact 348 and 354 is connected to one side of polysilicon gate contacts 350 and 352, and the other side of polysilicon gate contacts 350 and 352 is connected to output OUT via a contact 392 and a via 394. In some embodiments, a high-k dielectric 346 is connected to the reference voltage VSS.

[0093] Figure 19 This is a schematic diagram illustrating the p-type transistors on the back side of a semiconductor device 340 connected as a 2-input NAND gate according to some embodiments. The semiconductor device 340 includes a 2D CMG region 342, polysilicon gate contacts 348, 350, 352, and 354, a p-type active region layer 356', and MD layers 396, 398, 400, 402, and 404. The p-type active region layer 356' extends in the x-direction, and the polysilicon gate contacts 348, 350, 352, and 354, as well as the MD layers 396, 398, 400, 402, and 404, extend in the y-direction perpendicular to the x-direction.

[0094] The 2D CMG region 342 extends in the z-direction and cuts polysilicon gate contacts 348, 350, 352, and 354 to provide shortened polysilicon ends 368, 370, 372, and 374, respectively. Furthermore, the 2D CMG region 342 includes a low-k dielectric 344 and a high-k dielectric 346 surrounding the low-k dielectric 344, and includes a first portion 376 having a first width W1 and a second portion 378 having a second width W2 greater than the first width W1. The second portion 378 cuts the polysilicon gate contacts 348, 350, 352, and 354 to provide shortened polysilicon ends 368, 370, 372, and 374, respectively.

[0095] Semiconductor device 340 is configured as a 2-input NAND gate with a drive strength of 2. A power supply voltage VDD is connected to MD layers 398 and 402 on one side above the p-type active region layer 356' and on each of the polysilicon gate contacts 348, 350, 352, and 354. The other side of each polysilicon gate contact 348, 350, 352, and 354 is connected to the output OUT via metal layer 406, vias 408, 410, and 412, and contact 392. In some embodiments, a high-k dielectric 346 is connected to the power supply voltage VDD.

[0096] Figure 20 This is an illustrative representation of a semiconductor manufacturing apparatus according to some embodiments (e.g. Figures 13 to 15 A diagram of a method for forming a semiconductor device 250. At 420, the method includes forming an active region layer (e.g., active region layer 264) extending in a first direction (e.g., the x-direction). At 422, the method includes forming a polysilicon gate contact, the polysilicon gate contact including a polysilicon end and extending over the active region in a second direction different from the first direction. At 424, the method includes forming a dielectric region adjacent to the polysilicon end, wherein forming the dielectric region includes: a first portion having a high-k dielectric material; and a second portion having a low-k dielectric material. In some embodiments, the second portion is located within the first portion of the dielectric region. In some embodiments, the method includes forming a polysilicon gate contact comprising a metal gate material, removing at least some of the metal gate material from at least one of the polysilicon gate contacts to form a CMG region (e.g., CMG region pattern 258), filling a first portion of the CMG region with a high-k dielectric material (e.g., high-k dielectric 254), and filling a second portion (e.g., space 272) of the CMG region with a low-k dielectric material (e.g., low-k dielectric 256). In some embodiments, the second portion is located inside the first portion of the CMG region.

[0097] In some embodiments, the method includes forming a magnetic material layer (MD layer) extending in a second direction (e.g., the y-direction). The MD layer is located above the active region layer. Furthermore, in some embodiments, the method includes a second direction (e.g., the y-direction) perpendicular to a first direction (e.g., the x-direction).

[0098] Figure 21 This is a block diagram schematically illustrating an example of a computer system 500 configured to provide the semiconductor devices and methods disclosed herein according to some embodiments. Part or all of the design, layout, and fabrication of the semiconductor device (also referred to as a semiconductor circuit) may be performed by or in conjunction with the computer system 500. In some embodiments, the computer system 500 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0099] In some embodiments, system 500 is a general-purpose computing device including processor 502 and non-transitory computer-readable storage medium 504. Computer-readable storage medium 504 may be encoded with (i.e., stored) computer program code, such as executable instructions 506. Execution of instructions 506 by processor 502 provides (at least partially) design tools for implementing some or all of the functions of system 500 (e.g., pre-placement simulation, post-placement simulation, routing, rerouting, and final placement for manufacturing). Additionally, manufacturing tools 508 are included to further place and physically implement the design and manufacture of the semiconductor device. In some embodiments, execution of instructions 506 by processor 502 provides (at least partially) design tools for implementing some or all of the functions of system 500. In some embodiments, system 500 includes a commercial router. In some embodiments, system 500 includes an automatic place and route (APR) system.

[0100] Processor 502 is electrically coupled to computer-readable storage medium 504 via bus 510, and is also electrically coupled to input / output (I / O) interface 512 via bus 510. Network interface 514 is connected to network 516 so that processor 502 and computer-readable storage medium 504 can connect to external components using network 516. Processor 502 is configured to execute computer program code or instructions 506 encoded in computer-readable storage medium 504 so that system 500 can be used to perform some or all of the functions of system 500, such as providing the semiconductor device and method of this disclosure and other functions of system 500. In some embodiments, processor 502 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0101] In some embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, device, or apparatus. For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 504 includes compact disk read-only memory (CD-ROM), compact disk read / write memory (CD-R / W), and / or digital video disc (DVD).

[0102] In some embodiments, computer-readable storage medium 504 stores computer program code or instructions 506 configured to cause system 500 to perform some or all of the functions of system 500. In some embodiments, computer-readable storage medium 504 also stores information that facilitates the performance of some or all of the functions of system 500. In some embodiments, computer-readable storage medium 504 stores a database 518 including one or more of a component library, a digital circuit cell library, and a database.

[0103] System 500 includes an I / O interface 512 coupled to external circuitry. In some embodiments, the I / O interface 512 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and instructions to processor 502.

[0104] Network interface 514 is coupled to processor 502 and allows system 500 to communicate with network 516, which is also connected to one or more other computer systems. Network interface 514 may include: a wireless network interface, such as Bluetooth, Wireless Fidelity (WIFI), Worldwide Interoperability of Microwave Access (WIMAX), General Packet Radio Service (GPRS), or Wideband Code Division Multiple Access (WCDMA); or a wired network interface, such as Ethernet, Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers (IEEE)-1364. In some embodiments, some or all of the functions of system 500 may be performed in two or more systems similar to system 500.

[0105] System 500 is configured to receive information via I / O interface 512. The information received via I / O interface 512 includes one or more of the following: instructions, data, design rules, components and cellular libraries, and / or other parameters for processing by processor 502. This information is transmitted to processor 502 via bus 510. Furthermore, system 500 is configured to receive information related to the user interface (UI) via I / O interface 512. This UI information can be stored as UI 520 in computer-readable media 504.

[0106] In some embodiments, some or all of the functions of system 500 are implemented via a standalone software application executed by a processor. In some embodiments, some or all of the functions of system 500 are implemented as a software application as part of an additional software application. In some embodiments, some or all of the functions of system 500 are implemented as a plug-in to a software application. In some embodiments, at least one of the functions of system 500 is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the functions of system 500 are implemented as a software application used by system 500. In some embodiments, layout diagrams are generated using tools such as VIRTUOSO, available from Cadence Design Systems, Inc., or another suitable layout generation tool.

[0107] In some embodiments, routing, layout, and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in memory or memory units, such as one or more optical discs (e.g., digital video discs (DVDs) or digital versatile discs (DVDs)), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM and RAM), and memory cards and similar media.

[0108] As described above, embodiments of system 500 include manufacturing tools 508 for implementing manufacturing processes of system 500. For example, based on the final layout, a photolithography mask can be generated, which is used to manufacture a semiconductor device using manufacturing tools 508.

[0109] Combination Figure 22 Other aspects of the device's manufacturing process were revealed. Figure 22This is a block diagram of a semiconductor device manufacturing system 522 and associated semiconductor device manufacturing processes according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 522 is used to manufacture one or more semiconductor masks and / or at least one component in a layer of a semiconductor device.

[0110] exist Figure 22 In this semiconductor device manufacturing system 522, entities such as a design house 524, a mask house 526, and a semiconductor device manufacturer / foundry (“Fab”) 528 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of semiconductor devices (such as those described herein). The entities in system 522 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 524, mask house 526, and semiconductor device foundry 528 are owned by a single, larger company. In some embodiments, two or more of the design house 524, mask house 526, and semiconductor device foundry 528 coexist in shared facilities and use shared resources.

[0111] Design agency (or design team) 524 generates a semiconductor device design layout 530. The semiconductor device design layout 530 includes various geometric patterns or semiconductor device layouts designed for the semiconductor device. The geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers constituting various components of the semiconductor structure to be manufactured. These layers are combined to form various semiconductor device features. For example, a portion of the semiconductor device design layout 530 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions, gate electrodes, source electrodes, drain electrodes, metal lines, partial vias, and openings for bond pads. Design agency 524 performs a design process to generate the semiconductor device design layout 530. The semiconductor device design layout 530 exists in one or more data files containing information about the geometric patterns. For example, the semiconductor device design layout 530 may be expressed in GDSII file format or DesignFramework II (DFII) file format. In some embodiments, the design process includes one or more of the following: simulation circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design including power via design, power supply voltage rail design, reference voltage rail design, placement and routing routines, and physical placement design.

[0112] Mask assembly 526 includes data preparation 532 and mask fabrication 534. Mask assembly 526 uses a semiconductor device design layout 530 to fabricate one or more masks 536 for the various layers to be used in the fabrication of a semiconductor device or semiconductor structure. Mask assembly 526 performs mask data preparation 532, in which the semiconductor device design layout 530 is translated into a representative data file (RDF). Mask data preparation 532 provides the RDF to mask fabrication 534. Mask fabrication 534 includes a mask writer that converts the RDF into an image on a substrate (e.g., a mask 536 or a semiconductor wafer 538). The design layout 530 is processed by mask data preparation 532 to comply with the characteristics of the mask writer and / or the requirements of the semiconductor device foundry 528. Figure 22 In this embodiment, mask data preparation 532 and mask manufacturing 534 are shown as separate components. In some embodiments, mask data preparation 532 and mask manufacturing 534 may be collectively referred to as mask data preparation.

[0113] In some embodiments, mask data preparation 532 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, and similar factors. OPC adjusts the semiconductor device design layout 530. In some embodiments, mask data preparation 532 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and similar techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT), which treats OPC as a reverse imaging problem, is also used.

[0114] In some embodiments, mask data preparation 532 includes a mask rule checker (MRC) that uses a set of mask creation rules, containing certain geometric and / or connectivity constraints, to check the semiconductor device design layout 530 that has undergone various processes in the OPC to ensure that there is sufficient margin to account for the variability in the semiconductor manufacturing process and achieve similar effects. In some embodiments, the MRC modifies the semiconductor device design layout 530 to compensate for constraints during mask fabrication 534, which can undo some modifications implemented by the OPC to satisfy the mask creation rules.

[0115] In some embodiments, mask data preparation 532 includes lithography process checking (LPC), which simulates the processing to be performed by a semiconductor device foundry 528. LPC simulates this processing based on a semiconductor device design layout 530 to create a simulated fabricated device. Processing parameters in the LPC simulation may include parameters associated with various processes in the semiconductor device manufacturing cycle, parameters associated with the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors, or combinations thereof. In some embodiments, after a simulated fabricated device has been created using LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the semiconductor device design layout 530.

[0116] For clarity, the above description of mask data preparation 532 has been simplified. In some embodiments, data preparation 532 includes additional features such as logic operations (LOPs) to modify the semiconductor device design layout 530 according to manufacturing rules. Furthermore, the processes applied to the semiconductor device design layout 530 during data preparation 532 can be performed in various different sequences.

[0117] After mask data preparation 532 and during mask manufacturing 534, a mask 536 or a set of masks 536 is manufactured based on a modified semiconductor device design layout 530. In some embodiments, mask manufacturing 534 includes performing one or more lithographic exposures based on the semiconductor device design layout 530. In some embodiments, a pattern is formed on the mask (photomask or stencil) 536 using an electron beam (e-beam) or multiple electron beam mechanism based on the modified semiconductor device design layout 530. The mask 536 can be formed using various techniques. In some embodiments, the mask 536 is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 536 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in opaque areas of the binary mask. In another example, mask 536 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of mask 536, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask may be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 534 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 538, in etching processes to form various etched regions in semiconductor wafer 538, and / or other suitable processes.

[0118] Semiconductor device foundry 528 includes wafer fabrication 540. Semiconductor device foundry 528 is a semiconductor device manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various semiconductor device products. In some embodiments, semiconductor device foundry 528 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple semiconductor device products, a second manufacturing facility for back-end-of-line (BEOL) manufacturing of interconnects and packages for semiconductor device products, and a third manufacturing facility for providing other services to the foundry enterprise.

[0119] Semiconductor device foundry 528 uses mask 536, fabricated by mask assembly 526, to manufacture the semiconductor structure or semiconductor device 542 of this disclosure. Therefore, semiconductor device foundry 528 uses semiconductor device design layout 530 at least indirectly to manufacture the semiconductor structure or semiconductor device 542 of this disclosure. Furthermore, semiconductor wafer 538 includes a silicon substrate or other suitable substrate on which material layers are formed, and semiconductor wafer 538 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent manufacturing steps). In some embodiments, semiconductor wafer 538 is fabricated by semiconductor device foundry 528 using mask 536 to form the semiconductor structure or semiconductor device 542 of this disclosure. In some embodiments, semiconductor device fabrication includes performing one or more photolithographic exposures based at least indirectly on semiconductor device design layout 530.

[0120] The disclosed embodiments provide a semiconductor device with shortened and / or minimally long polysilicon gate contact ends extending from the edge of the active region layer of the semiconductor device to the edge of the CMG region. The shorter polysilicon gate contact ends reduce polysilicon gate contact capacitance, such as capacitance from the polysilicon gate contact to the MD layer or from the polysilicon gate contact to the active region layer. In some embodiments, the capacitance extends from the polysilicon gate contact in one cell to the MD layer in the same cell. In some embodiments, the capacitance extends from the polysilicon gate contact in one cell to the MD layer in another cell. In some embodiments, the capacitance extends from the polysilicon gate contact in one cell to the active region layer in another cell.

[0121] Furthermore, the disclosed embodiments provide a semiconductor device including a polysilicon gate contact and a CMG region, wherein the CMG region cleaves the polysilicon gate contact to provide a shortened polysilicon gate contact end, i.e., a shortened polysilicon end. The CMG region includes a first portion having a first width and a second portion having a second width greater than the first width. The second portion cleaves the polysilicon gate contact to provide the shortened polysilicon end. The second portion includes a high-k dielectric material located around a low-k dielectric at least in the x and y directions. In some embodiments, the shortened polysilicon end is a minimum-length polysilicon end.

[0122] According to some embodiments, a semiconductor device includes: a first active region layer extending along a first direction; a first diffusion-over-metal layer extending along a second direction different from the first direction, the first diffusion-over-metal layer being located above the first active region layer; a first polysilicon gate contact extending along the second direction above the first active region layer; a first polysilicon end of the first polysilicon gate contact adjacent to a first dielectric region; and a first low-k dielectric material located in the first dielectric region.

[0123] In some embodiments, the first dielectric region does not include a first polysilicon gate contact. In some embodiments, the first direction is perpendicular to the second direction. In some embodiments, the first dielectric region includes a first portion having a first width and a second portion having a second width greater than the first width. In some embodiments, the second portion abuts the first polysilicon gate contact at a first polysilicon end. In some embodiments, a first low-dielectric-constant dielectric material is located in the second portion of the first dielectric region. In some embodiments, the semiconductor device further includes an insulating layer extending along the first direction below the first active region layer and above the second active region layer. In some embodiments, the semiconductor device further includes a second diffusion-over-metal layer extending along the second direction and below the second active region layer. In some embodiments, the first polysilicon gate contact extends above the second active region layer and abuts the first dielectric region. In some embodiments, the semiconductor device includes: a second active region layer extending in a first direction, the second active region layer being separated from the first active region layer in a second direction; a second diffusion over metal layer extending in a second direction above the second active region layer; a second polysilicon gate contact extending in a second direction above the second active region layer; a second polysilicon end of the second polysilicon gate contact adjacent to a second dielectric region; and a second low dielectric constant dielectric material located in the second dielectric region.

[0124] According to another embodiment, a semiconductor device includes a first cell and a second cell. The first cell includes: a first active region layer extending along a first direction; a first diffusion-over-metal layer extending along a second direction perpendicular to the first direction, the first diffusion-over-metal layer being located above the first active region layer; a first polysilicon gate contact extending along the second direction above the first active region layer; and a first polysilicon end of the first polysilicon gate contact adjacent to a first dielectric region. The second cell includes: a second active region layer extending along the first direction; a second diffusion-over-metal layer extending along the second direction above the second active region layer; a second polysilicon gate contact extending along the second direction above the second active region layer; a second polysilicon end of the second polysilicon gate contact adjacent to a second dielectric region; and a third polysilicon end of the second polysilicon gate contact in the second cell adjacent to the first dielectric region.

[0125] In some embodiments, the first dielectric region includes a first portion having a first width and a second portion having a second width greater than the first width and extending into the first cell and the second cell. In some embodiments, the second portion abuts a first polysilicon gate contact in the first cell at a first polysilicon end and a second polysilicon gate contact in the second cell at a third polysilicon end. In some embodiments, a low-dielectric-constant dielectric is located in the second portion. In some embodiments, the semiconductor device includes an insulating layer extending in a first direction below a first active region layer and above a third active region layer. In some embodiments, the semiconductor device includes a third diffusion-over-metal layer extending in a second direction below the third active region layer, wherein the first polysilicon gate contact extends above the third active region layer and the first dielectric region abuts the first polysilicon gate contact.

[0126] According to a further disclosed aspect, a method of manufacturing a semiconductor device includes: forming an active region layer extending along a first direction; forming a polysilicon gate contact including a polysilicon end and extending over the active region in a second direction different from the first direction; and forming a dielectric region adjacent to the polysilicon end, wherein forming the dielectric region includes: a first portion of forming the dielectric region having a high-k dielectric material; and a second portion of forming the dielectric region having a low-k dielectric material.

[0127] In some embodiments, the second portion is located within the first portion of the dielectric region. In some embodiments, the method includes forming a diffusion-over-metal layer extending along a second direction, the diffusion-over-metal layer being located above the active region layer. In some embodiments, the second direction is perpendicular to the first direction.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: The first active region extends along the first direction; The first diffusion upper metal layer extends along a second direction different from the first direction, and the first diffusion upper metal layer is located above the first active region layer; A first polysilicon gate contact extends along the second direction above the first active region layer; The first polysilicon end of the first polysilicon gate contact is adjacent to the first dielectric region; as well as The first low dielectric constant dielectric material is located in the first dielectric region.

2. The semiconductor device according to claim 1, characterized in that, The first dielectric region does not include the first polysilicon gate contact.

3. The semiconductor device according to claim 1, characterized in that, The first dielectric region includes a first portion having a first width and a second portion having a second width greater than the first width.

4. The semiconductor device according to claim 3, characterized in that, The first low dielectric constant dielectric material is located in the second part of the first dielectric region.

5. A semiconductor device, characterized in that, include: The first cell unit includes: The first active region extends along the first direction; The first diffusion-above metal layer extends along a second direction perpendicular to the first direction, and the first diffusion-above metal layer is located above the first active region layer; A first polysilicon gate contact extends along the second direction above the first active region layer; and The first polysilicon end of the first polysilicon gate contact is adjacent to the first dielectric region; and The second cell unit includes: The second active region extends along the first direction; The second diffusion layer extends along the second direction above the second active region layer; A second polysilicon gate contact extends over the second active region layer along the second direction; The second polysilicon end of the second polysilicon gate contact is adjacent to the second dielectric region; and The third polysilicon end of the second polysilicon gate contact in the second cell is adjacent to the first dielectric region.

6. The semiconductor device according to claim 5, characterized in that, The first dielectric region includes a first portion having a first width and a second portion having a second width greater than the first width and extending into the first cell and the second cell.

7. The semiconductor device according to claim 6, characterized in that, The second portion is adjacent to the first polysilicon gate contact in the first cell at the first polysilicon end and to the second polysilicon gate contact in the second cell at the third polysilicon end.

8. The semiconductor device according to claim 6, characterized in that, The low dielectric constant dielectric is located in the second part.

9. The semiconductor device according to claim 5, characterized in that, It includes an insulating layer located below the first active region layer and above the third active region layer, extending along the first direction.

10. The semiconductor device according to claim 9, characterized in that, Includes a third diffusion over metal layer extending in the second direction below the third active region layer, wherein the first polysilicon gate contact extends above the third active region layer and the first dielectric region is adjacent to the first polysilicon gate contact.

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