SSD test board supporting low power consumption
By integrating the motherboard communication interface and optimizing the signal transmission path on the SSD test board, the signal attenuation problem caused by multiple PCIe signal transfers is solved, achieving low-power, high-efficiency SSD testing capabilities and meeting the needs of large-scale testing.
Patent Information
- Application Number
- CN202520250437.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2035-02-17
AI Technical Summary
The PCIe signal of the existing SSD test board suffers severe attenuation during multiple switching processes, resulting in excessive signal loss and failing to meet the requirements of efficient testing.
Design a low-power SSD test board that integrates the first communication interface directly on the motherboard and connects it directly to the SSD via the backplane, reducing the number of PCIe signal transfers. Use the MCIO interface to fix the high-speed line, optimize the signal transmission path, and maximize the splitting of the CPU's PCIe signals through a customized BIOS to independently control multiple SSD slots.
It effectively reduces signal loss, improves PCIe signal quality, supports simultaneous testing of multiple PCIe 5.0 SSDs, reduces unit port cost, improves testing efficiency, and has low-power testing capabilities to meet the needs of large-volume SSD testing.
Smart Images
Figure CN223796587U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of SSD testing technology, and in particular to an SSD testing board that supports low power consumption. Background Technology
[0002] The SSD test board is a device mainly used for testing SSDs. The current solution is to use an expansion board inserted into the motherboard's PCIe interface. The CPU splits multiple 4X PCIe signals through multiple AIC interfaces on the expansion board and sends them to the backplane, where they are connected to the SSDs plugged in.
[0003] However, PCIe signals are high-speed signals, and too many transfers will lead to excessive signal attenuation. In the current solution, after PCIe is transferred through the expansion board, it still needs to be transferred to the backplane, and finally transferred to the SSD through the backplane. The whole process involves three transfers, which aggravates the attenuation. Utility Model Content
[0004] To address the shortcomings of existing technologies, this invention provides a low-power SSD test board that effectively reduces signal loss caused by adapters.
[0005] This utility model is achieved through the following technical solution:
[0006] A low-power SSD test board includes:
[0007] A motherboard, wherein a CPU and multiple first communication interfaces connected to the CPU are integrated on the motherboard;
[0008] The backplane integrates multiple second communication interfaces and multiple SSD slots, with each of the multiple second communication interfaces connected to one of the multiple SSD slots, and each of the multiple first communication interfaces connected to one of the multiple second communication interfaces.
[0009] Both the first communication interface and the second communication interface support at least the PCIe protocol.
[0010] Furthermore, multiple first communication interfaces are arranged sequentially along the same edge of the motherboard.
[0011] Furthermore, the CPU is positioned close to the first communication interface.
[0012] Furthermore, multiple second communication interfaces are arranged sequentially along the same edge of the backplate.
[0013] Furthermore, both the first communication interface and the second communication interface adopt the MCIO interface.
[0014] Furthermore, the MCIO interface has a latch for securing the high-speed line from which the PCIe signal is led out.
[0015] Furthermore, the CPU is connected to multiple independent PCIe 4X signal lines, and each of the multiple PCIe 4X signal lines is connected to one of the multiple first communication interfaces.
[0016] Furthermore, the PCIe 4X signal lines are provided in four groups, and each of the four groups of PCIe 4X signal lines is independent and independently controls multiple SSD slots.
[0017] Furthermore, the motherboard also integrates a bridge chip connected to the CPU and a clock management chip connected to the bridge chip, and the clock management chip is simultaneously connected to multiple of the first communication interfaces.
[0018] Furthermore, the CPU contains a main control chip, which is connected to a power module.
[0019] Compared with existing technologies, the advantages of this utility model are:
[0020] 1. By integrating multiple primary communication interfaces directly onto the motherboard, the PCIe on the CPU is transferred to the backplane, and then transferred to the SSD through the backplane. The PCIe signal transfer only occurs twice, effectively reducing signal loss caused by the transfer. The PCIe signal quality is effectively improved, which is far superior to Intel's design standard, laying a solid foundation for the company's test platform.
[0021] 2. This application utilizes a custom-developed BIOS to maximize the splitting of PCIe signals in the CPU. One CPU can output multiple sets of PCIe signal lines, and each set of PCIe 4X signal lines is independent and controls multiple SSD slots independently. This allows for simultaneous testing of multiple PCIe 5.0 SSDs, maximizing the use of PCIe signals in the CPU. More SSDs can be connected during testing, reducing the cost per port and greatly improving testing efficiency, thus meeting customers' needs for large-volume SSD testing.
[0022] 3. By adopting MCIO interfaces for both the first and second communication interfaces, the MCIO interface can transmit high-speed signals. It is not only compatible with PCIe signals, but also has a latch to fix the high-speed line leading out the PCIe signal, preventing the high-speed line from becoming loose and ensuring stable signal transmission.
[0023] 4. By placing the first communication interface on the edge of the motherboard and placing multiple second communication interfaces on the same edge of the backplane, the high-speed cable connecting the first and second communication interfaces can be shortened to the maximum extent, effectively reducing signal attenuation and enhancing signal quality.
[0024] 5. By placing the CPU close to the first communication interface, the PCIe signal trace from the CPU to the MCIO interface is minimized and optimized, thus reducing trace length to the greatest extent, effectively reducing signal attenuation, and enhancing signal quality.
[0025] 6. By introducing a clkreq# signal to each MCIO interface, clkreq# goes high when low power is required, allowing independent low-power testing for each SSD under test. Motherboards designed with this solution can perform low-power testing on every consumer-grade SSD, a feature not found in conventional motherboards, thus meeting customer testing needs. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the SSD test board.
[0027] Figure 2 This is a schematic diagram of the MCIO interface distribution on the SSD test board;
[0028] Figure 3 A schematic diagram of the CPU splitting PCIe architecture;
[0029] Figure 4 This is a schematic diagram of the MCIO interface.
[0030] 1. Motherboard; 2. CPU; 3. First communication interface; 4. Backplate; 5. Second communication interface; 6. SSD slot; 7. Bridge chip; 8. Clock management chip; 9. Clip. Detailed Implementation
[0031] The following detailed, non-limiting description of the utility model's technical solution, in conjunction with preferred embodiments and accompanying drawings, is provided. In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.
[0032] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0033] like Figure 1 As shown, an embodiment of this utility model provides a low-power SSD test board, including a motherboard 1 and a backplate 4. The motherboard 1 integrates a CPU 2 and multiple first communication interfaces 3 connected to the CPU 2. The backplate 4 integrates multiple second communication interfaces 5 and multiple SSD slots 6, wherein each of the multiple second communication interfaces 5 is connected to a corresponding SSD slot 6, and each of the multiple first communication interfaces 3 is connected to a corresponding second communication interface 5. Both the first communication interfaces 3 and the second communication interfaces 5 support at least the PCIe protocol. (Reference) Figure 1 In this application, multiple first communication interfaces 3 are directly integrated on the motherboard 1. The PCIe on the CPU is transferred to the backplane 4, and then transferred to the SSD through the backplane 4. The number of PCIe signal transfers is only two, which effectively reduces the signal loss caused by the transfer and effectively improves the PCIe signal quality, which is far superior to the Intel design standard, laying a solid foundation for the company's test platform.
[0034] like Figure 3As shown, this application utilizes a custom-developed BIOS to maximize the splitting of PCIe signals within the CPU. A single CPU can output multiple sets of PCIe signal lines. In this embodiment, CPU 2 is connected to multiple independent sets of PCIe 4X signal lines, and these multiple sets of PCIe 4X signal lines are connected one-to-one with multiple first communication interfaces 3. Further reference... Figure 3 There are four sets of PCIe 4X signal lines, each of which is independent and controls multiple SSD slots. This allows for simultaneous testing of four PCIe 5.0 SSDs, maximizing the use of the PCIe signals in the CPU. More SSDs can be connected during testing, reducing the cost per port and greatly improving testing efficiency, thus meeting customers' needs for large-volume SSD testing.
[0035] like Figure 4 As shown, in this embodiment, both the first communication interface 3 and the second communication interface 5 adopt the MCIO interface. Specifically, multiple PCIe signals in the CPU 2 are pulled to the MCIO interface. The MCIO interface can transmit high-speed signals and is compatible with PCIe signals. In addition, the MCIO interface has a latch 9, which is used to fix the high-speed line leading out the PCIe signal to avoid the high-speed line from becoming loose and to ensure stable signal transmission.
[0036] like Figure 2 As shown, multiple first communication interfaces 3 are arranged sequentially along the same edge of the motherboard 1, while multiple second communication interfaces 5 are arranged sequentially along the same edge of the backplate 4. The first communication interfaces 3 in this application can be flexibly adjusted in position and are not limited by the position of the PCIe interface on the motherboard 1. By arranging the first communication interfaces 3 on the edge of the motherboard 1 and arranging multiple second communication interfaces 5 on the same edge of the backplate 4, the high-speed lines connecting the first communication interfaces 3 and the second communication interfaces 5 can be shortened to the maximum extent, effectively reducing signal attenuation and enhancing signal quality.
[0037] In addition, the CPU 2 is positioned close to the first communication interface 3. By adjusting the position of the CPU 2 within the motherboard 1, the PCIe signal trace from the CPU to the MCIO interface is made the shortest and most optimal. This minimizes the trace length, effectively reduces signal attenuation, and enhances signal quality.
[0038] like Figure 1As shown, the motherboard 1 also integrates a bridge chip 7 connected to the CPU 2 and a clock management chip 8 connected to the bridge chip 7. The clock management chip 8 is simultaneously connected to multiple first communication interfaces 3. By introducing a clkreq# signal to each MCIO interface, clkreq# becomes high when low power is required, allowing independent low-power testing for each SSD under test. The motherboard designed with this solution can perform low-power testing on every consumer-grade SSD, a feature not found in conventional motherboards, thus meeting customer testing needs.
[0039] CPU2 contains a main control chip, which is connected to a power module.
[0040] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.
Claims
1. A test board supporting low-power SSDs, characterized in that, include: A motherboard (1) is provided, on which a CPU (2) and a plurality of first communication interfaces (3) connected to the CPU (2) are integrated; Backplate (4), on which multiple second communication interfaces (5) and multiple SSD slots (6) are integrated, the multiple second communication interfaces (5) are connected to the multiple SSD slots (6) one by one, and the multiple first communication interfaces (3) are connected to the multiple second communication interfaces (5) one by one; Both the first communication interface (3) and the second communication interface (5) support at least the PCIe protocol.
2. The SSD test board supporting low power consumption according to claim 1, characterized in that, Multiple first communication interfaces (3) are arranged sequentially along the same edge of the motherboard (1).
3. The SSD test board supporting low power consumption according to claim 2, characterized in that, The CPU (2) is positioned close to the first communication interface (3).
4. The SSD test board supporting low power consumption according to claim 1, characterized in that, Multiple second communication interfaces (5) are arranged sequentially along the same edge of the backplate (4).
5. The SSD test board supporting low power consumption according to claim 1, characterized in that, Both the first communication interface (3) and the second communication interface (5) adopt the MCIO interface.
6. A low-power SSD test board according to claim 5, characterized in that, The MCIO interface has a latch (9) for securing the high-speed line from which the PCIe signal is led out.
7. The SSD test board supporting low power consumption according to claim 1, characterized in that, The CPU (2) is connected to multiple independent PCIe 4X signal lines, and the multiple PCIe 4X signal lines are connected one-to-one with multiple first communication interfaces (3).
8. A low-power SSD test board according to claim 7, characterized in that, The PCIe 4X signal lines are provided in four groups, and each of the four groups of PCIe 4X signal lines is independent and controls multiple SSD slots (6) independently.
9. A low-power SSD test board according to claim 1, characterized in that, The motherboard (1) also integrates a bridge chip (7) connected to the CPU (2) and a clock management chip (8) connected to the bridge chip (7). The clock management chip (8) is simultaneously connected to multiple first communication interfaces (3).
10. A low-power SSD test board according to claim 1, characterized in that, The CPU (2) has a main control chip inside, and the main control chip is connected to a power module.