Multi-slave SPI communication connection circuit

Abstract

The utility model belongs to the technical field of communication, and particularly discloses a multi-slave SPI (Serial Peripheral Interface) communication connection circuit which comprises a host, slaves and an AND gate core, an SPI communication chip selection signal interface CS of the host is connected with an SPI communication chip selection signal interface CS of each slave, a communication clock signal interface SCK of the host is connected with a communication clock signal interface SCK of each slave, and the AND gate core is connected with the host. And a data output pin MOSI of the host is connected with a data input pin MOSI of the slave. Through a standardized communication interface and flexible protocol configuration, the method can easily adapt to various SPI slaves, the development cost and the debugging time caused by the equipment compatibility problem are reduced, and the universality and the applicability of the system are improved. Meanwhile, the simplified hardware circuit is also beneficial to improving the reliability and maintainability of the system. And the interference resistance of the communication system is improved through an innovative hardware connection design and a signal processing algorithm.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, specifically to a multi-slave SPI communication connection circuit. Background Technology

[0002] In traditional SPI communication, all data inputs of multiple slave devices are shorted on the same bus, making them susceptible to interference and resulting in weak anti-interference capabilities.

[0003] To achieve multi-slave SPI communication, additional hardware circuitry is required, such as multiplexers and drivers. This additional hardware increases the cost and complexity of the system.

[0004] Traditional SPI communication uses multiple slave devices, resulting in low compatibility. SPI devices from different manufacturers may differ in electrical characteristics and communication protocol details. In multi-slave systems, compatibility issues may arise when using devices from different manufacturers, leading to communication failures or instability. Utility Model Content

[0005] The purpose of this invention is to provide a multi-slave SPI communication connection circuit to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a multi-slave SPI communication connection circuit, comprising:

[0007] Master, slave, AND gate chip;

[0008] Wherein, the master's SPI communication chip select signal interface CS is connected to the slave's SPI communication chip select signal interface CS, the master's communication clock signal interface SCK is connected to the slave's communication clock signal interface SCK, and the master's data output pin MOSI is connected to the slave's data input pin MOSI.

[0009] The slave device's _SPI communication data output pin MISO is connected to an AND gate chip, and the AND gate chip is connected to the master device's _SPI communication data output pin MISO.

[0010] Preferably, there are three slave devices, and the number of SPI communication chip select signal interfaces (CS) of the master device is the same as the number of slave devices.

[0011] Preferably, the slave device includes an RTC module, a pressure sensor module, and a storage chip module.

[0012] Preferably, the AND gate chip is a three-channel AND gate chip, and the input values ​​of the three slave devices are selectively output to one I / O port of the AND gate chip.

[0013] Compared with the prior art, the beneficial effects of this utility model are:

[0014] Compatible with multiple device types: This multi-slave SPI communication connection method boasts broad compatibility, adapting to SPI devices from different manufacturers and models. Through standardized communication interfaces and flexible protocol configurations, this method easily adapts to various SPI slaves, reducing development costs and debugging time caused by device compatibility issues, and improving the system's versatility and applicability.

[0015] Simplifying hardware circuit design: By optimizing communication connections and reducing unnecessary hardware circuitry, such as using multiplexers to simplify the chip select signal control circuitry, hardware costs and complexity are reduced. Furthermore, the simplified hardware circuitry also improves system reliability and maintainability.

[0016] Reduce signal interference: Improve the anti-interference capability of communication systems through innovative hardware connection design and signal processing algorithms. Attached Figure Description

[0017] Figure 1 This is a system logic block diagram of the present invention;

[0018] Figure 2 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0020] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0021] Example 1, please refer to Figure 1 This utility model provides a technical solution: a multi-slave SPI communication connection circuit, including: a master, a slave, and an AND gate chip;

[0022] Specifically, the master's SPI chip select interface CS is connected to the slave's SPI chip select interface CS; the master's communication clock interface SCK is connected to the slave's communication clock interface SCK; and the master's data output pin MOSI is connected to the slave's data input pin MOSI. The slave's SPI data output pin MISO is connected to an AND gate chip, and the AND gate chip is connected to the master's SPI data output pin MISO. The AND gate chip is a three-channel AND gate chip, and the input values ​​from the three slave devices are selectively output to one I / O port of the AND gate chip.

[0023] Analysis of the above content: such as Figure 1 As shown, where:

[0024] CS3: Slave 3 _SPI communication chip select signal, transmitted from the master to the _SPI communication chip select signal interface CS of slave 3;

[0025] CS2: Slave 2 SPI communication chip select signal, transmitted from the master to the SPI communication chip select signal interface CS of slave 2;

[0026] CS1: Slave 1 SPI communication chip select signal, transmitted from the master to the SPI communication chip select signal interface CS of slave 1;

[0027] MISO3: Slave 3_SPI communication data output pin, master SPI receive;

[0028] MISO2: Slave 2 SPI communication data output pin, master SPI receive;

[0029] MISO1: Slave 2 SPI communication data output pin, master SPI receive;

[0030] MOSI: Master SPI data output pin, slave 1 / 2 / 3 data input pin;

[0031] SCK: SPI communication clock signal;

[0032] U1: AND gate logic gate (AND gate chip).

[0033] SPI communication principle:

[0034] The host sequentially sends selection communication signals to the slave via CS1 / CS2 / CS3;

[0035] The master sends data to the slave via MOSI. When the slave recognizes the master's chip select CS signal, the MISO sends the corresponding data back to the master. Other devices that have not received the chip select signal remain still.

[0036] By using the U1 logic gate AND gate, different slave MISOs have independent ports, which do not interfere with each other and improve the stability and efficiency of MISO data transmission.

[0037] truth table of logic gates:

[0038]

[0039] Remark:

[0040] A: Logic gate input pin A

[0041] B: Logic gate input pin B

[0042] C: Logic gate input pin C

[0043] Y: Logic gate output pin Y

[0044] H: High-level input

[0045] L: Low-level input.

[0046] SPI Communication Selection Table:

[0047]

[0048] Remark:

[0049] Data feedback: The slave device sends data back to the master device via MISO;

[0050] High level: The MISO of a slave device that is not selected by the master chip can be kept high by an external pull-up resistor.

[0051] Example 2, please refer to Figure 2 This utility model provides a technical solution based on Embodiment 1: Three slave devices are configured, and the number of SPI communication chip select signal interfaces (CS) of the master device is the same as the number of slave devices. Each slave device includes an RTC module, a pressure sensor module, and a memory chip module.

[0052] Analysis of the above content: Based on Example 1, a specific case study will be used to illustrate the following:

[0053] Figure 2 middle:

[0054] U2 (Main Unit): An NXP main chip MCU that communicates and interacts with external devices via SPI.

[0055] U4 (Slave 1): This is where the RTC chip uploads clock information to the master MCU_U1 via SPI communication;

[0056] U6 (Slave 3): Stores MCU information to an external storage chip and writes and reads data via SPI.

[0057] U5 (Slave 2): This is a pressure sensor chip that uploads atmospheric pressure values ​​to the MCU via SPI communication;

[0058] U3 (AND gate chip): A three-channel AND gate chip that selectively outputs three input values ​​to one I / O port. The three input ports do not interfere with each other. For specific output timing, please refer to the logic gate truth table.

[0059] Figure 2 Resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9 in the diagram are current-limiting resistors for the SPI communication bus.

[0060] Figure 2 Resistors R10, R11, and R12 in the diagram are pull-up resistors for the slave SPI-MISO data bus, which remain high when idle.

[0061] Specific workflow:

[0062] RTC Module Communication (U4): When the MCU needs to read RTC data, it keeps the chip select signal PCS3 low and PCS2 and PCS1 high, and sends the data to be called to the RTC module through SOUT. The RTC replies to the MCU through DO. The pressure sensor and memory chip are in an idle state and are kept high through pull-up resistors. The RTC replies to the MCU through an AND gate chip. The communication quality is independent of the pressure sensor chip and memory chip.

[0063] Pressure sensor module communication (U5): When the MCU needs to read pressure sensor data, it keeps the chip select signal PCS2 low and PCS3 and PCS1 high, and sends the data to be called to the pressure sensor module through SOUT. The RTC replies to the MCU through SICO. The RTC module and memory chip are in an idle state and are kept at a high level through pull-up resistors. The pressure sensor replies to the MCU through an AND gate chip. The communication quality is independent of the RTC chip and memory chip.

[0064] Memory chip module communication (U6): When the MCU needs to read data from the memory chip, it keeps the chip select signal PCS1 low and PCS3 and PCS2 high, and sends the data to be called to the memory chip module via SOUT. The memory chip replies to the MCU via Q. The RTC module and pressure sensor are in an idle state and are kept high by pull-up resistors. The memory chip replies to the MCU via AND gate. The communication quality is independent of the RTC chip and pressure sensor.

[0065] Advantages and usage scenarios:

[0066] Advantages: Traditional SPI shared bus connects all slave MISOs in parallel on a single bus. This leads to excessive parasitic capacitance due to the large number of parallel buses, affecting bus communication quality such as excessively long rising and falling edge response times. Because SPI communication is a high-frequency signal, it has high requirements for bus parasitic parameters. The method used in this invention makes all MISO data independent, minimizing parasitic parameters and avoiding direct parallel use of buses, thus reducing the generation of parasitic parameters and preventing signal distortion. This function is implemented using AND gates, resulting in a simple structure, high stability, and improved cost advantages.

[0067] Use case: When there are too many slave devices and the number of MCU_SPIs is limited, a parallel connection method must be used, and it must be ensured that there is no distortion when calling slave data.

[0068] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. It is obvious to those skilled in the art that this utility model is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or basic characteristics of this utility model. Therefore, the embodiments should be considered exemplary and non-limiting in all respects. The scope of this utility model is defined by the appended claims rather than the foregoing description. Therefore, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this utility model, and no reference numerals in the claims should be considered as limiting the scope of the claims.

[0069] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multi-slave SPI communication connection circuit, characterized in that, include: Master, slave, AND gate chip; Wherein, the master's SPI communication chip select signal interface CS is connected to the slave's SPI communication chip select signal interface CS, the master's communication clock signal interface SCK is connected to the slave's communication clock signal interface SCK, and the master's data output pin MOSI is connected to the slave's data input pin MOSI. The slave device's _SPI communication data output pin MISO is connected to an AND gate chip, and the AND gate chip is connected to the master device's _SPI communication data output pin MISO.

2. The multi-slave SPI communication connection circuit according to claim 1, characterized in that: There are three slave devices, and the number of SPI communication chip select signal interfaces (CS) of the master device is the same as the number of slave devices.

3. The multi-slave SPI communication connection circuit according to claim 1, characterized in that: The slave device includes an RTC module, a pressure sensor module, and a storage chip module.

4. The multi-slave SPI communication connection circuit according to claim 2, characterized in that: The AND gate chip is a three-channel AND gate chip, and the input values ​​of the three slave devices are selectively output to one I / O port of the AND gate chip.

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