Measurement switch topology identification module

Abstract

The utility model discloses a measurement switch topology identification module, and relates to the technical field of power system automation. The problems of signal distortion, weak anti-interference capability and poor scene adaptability caused by mismatch of parasitic parameters and interface impedance of discrete devices and insufficient expansibility of an existing module in a high-frequency complex environment are solved. According to the scheme, a gallium nitride switch array is adopted to replace a traditional relay, and a dynamic switch matrix is constructed to reduce signal attenuation; a three-stage filtering structure of a magnetic bead, a common mode choke and a microwave absorption cavity is designed, so that full-band noise suppression is realized; hot plug parallel expansion of the multi-protocol daughter board is supported through the star-shaped expansion contact module and the FMC high-speed interface; a dual-redundancy power supply management module is configured to guarantee the power supply stability under an extreme working condition; the signal transmission fidelity and the topology identification accuracy are obviously improved, and the anti-interference capability in a complex electromagnetic environment is enhanced.

Description

Technical Field

[0001] This utility model relates to the field of power system automation technology, and more specifically to a measurement switch topology identification module. Background Technology

[0002] With the rapid development of electronics and information technology, smart grids and high-precision measurement and control systems are widely used in industrial automation and energy management. The trends of digitalization, modularization, and networking are constantly increasing the requirements of systems for real-time monitoring and fault diagnosis, creating an urgent need for efficient and stable switch topology identification technology, and providing solid technical support for improving system intelligence and security.

[0003] Currently, measurement switch topology identification modules rely on multi-level switch networks, controlling the opening and closing of various components to achieve different topologies, and using measurement circuits to sample voltage and current signals. The system integrates precise signal conditioning, filtering, and data processing units to determine the connection status after signal preprocessing. Existing technologies mostly use discrete components and standardized interfaces. Although they achieve basic identification functions, in high-frequency and complex environments, discrete components and standard interfaces make signal transmission susceptible to parasitic parameters, impedance mismatch, and timing errors, leading to sampled signal distortion and deviations in topology judgment. Furthermore, traditional anti-interference designs struggle to shield against high-frequency noise and electromagnetic interference, reducing system stability. Additionally, due to limitations in expansion design, the module is difficult to adapt to changing scenarios, limiting functional upgrades and compatibility. Utility Model Content

[0004] The purpose of this invention is to design a measurement switch topology identification module to address the shortcomings mentioned in the background technology.

[0005] To achieve the above-mentioned technical effects, the present invention adopts the following technical solution:

[0006] A measurement switch topology identification module includes: a dynamic switch matrix module, an anti-interference signal conditioning module, a communication module, a star-shaped extended contact module, a modular expansion slot interface module, and a dual-redundant power management module;

[0007] The dynamic switch matrix module includes a GaN switch array, an ADC sampling circuit, and an FPGA chip;

[0008] The anti-interference signal conditioning module includes a digital potentiometer, a three-stage filtering unit, and an isolation amplifier;

[0009] The communication module includes a tri-mode substrate unit and a protocol switching unit; the tri-mode substrate unit integrates an HPLC modulation chip, a Bluetooth chip and a LoRa RF front-end, and is connected to the FPGA chip via a PCIe interface.

[0010] The star-shaped extended contact module includes a six-contact gold-plated spring probe array, wherein three power contacts are soldered to the output terminal of the dual redundant power management module, and three signal contacts are connected to the communication module via an FPC cable;

[0011] The modular expansion slot interface module includes an FMC high-speed interface, which is connected to the FPGA chip via an LVDS differential pair.

[0012] The dual-redundant power management module includes a PoE power supply unit and a CT power supply unit connected in parallel. The PoE power supply unit and the CT power supply unit are soldered to the main power bus through an LTC3871 bidirectional DC-DC module.

[0013] The output of the dynamic switch matrix module is connected to the anti-interference signal conditioning module via a shielded twisted pair cable; the anti-interference signal conditioning module is connected to the communication module via a coaxial cable; the output of the communication module is connected to the modular expansion slot interface module via an LVDS differential pair and a grounding copper strip; the modular expansion slot interface module is connected to the star-shaped expansion contact module via an FPC flexible cable; and the dual redundant power management module supplies power to the above modules.

[0014] Furthermore, the GaN switch array is connected to the ADC sampling circuit via an LVDS bus; the FPGA chip is connected to the ADC sampling circuit via an SPI interface; and the ADC sampling circuit is connected in parallel with each switch node of the GaN switch array unit via shielded twisted-pair cables.

[0015] Furthermore, the GaN switch array consists of several gallium nitride (GaN) switches; the GaN switches are arranged in a four-layer PCB layout, including a signal layer, an FR-4 dielectric layer, a power layer, and a ground layer from top to bottom; the copper foil thickness of the power layer is 2 oz, and the thickness of the FR-4 dielectric layer is 0.8 mm; the ground layer is connected to the heat dissipation pads of the GaN switches through an array of vias.

[0016] Furthermore, the digital potentiometer is connected in series at the input of the ADC sampling circuit; the three-stage filtering unit is cascaded and connected to the isolation amplifier, and the output is transmitted to the FPGA chip via a coaxial connector.

[0017] Furthermore, the three-stage filtering unit includes a cascaded ferrite bead, a common-mode choke, and a waveguide cavity. The input end of the ferrite bead is connected in parallel with the output end of the GaN switch array via a shielded twisted-pair cable. The waveguide cavity is composed of an aluminum alloy shell and a ferrite-based broadband microwave absorbing material MCS-30. The outer wall of the waveguide cavity is bonded and fixed to the common-mode choke with conductive adhesive.

[0018] Furthermore, the inner wall of the aluminum alloy shell of the waveguide cavity is provided with a serrated protrusion structure, and the ferrite-based broadband microwave absorbing material MCS-30 is filled into the cavity by injection molding.

[0019] Furthermore, the protocol switching unit includes an ADG1612 analog switch chip. The COM pin of the ADG1612 analog switch chip is connected to the output terminals of the HPLC modulation chip, Bluetooth chip, and LoRa RF front-end through a shielded wire. The NO1-NO4 pins of the ADG1612 analog switch chip are connected to the FMC high-speed interface of the modular expansion slot interface module through an IPEX MHF4 coaxial connector, and the VDD pin of the ADG1612 is soldered to the independent power layer of the four-layer PCB.

[0020] Furthermore, the gold-plated spring probes of the six-contact gold-plated spring probe array adopt a double helical spring structure, and the probe base is fixed to the ceramic insulating substrate by laser welding.

[0021] Furthermore, the interface slot of the modular expansion slot interface module is equipped with an OM3 multimode fiber channel and a magnetically isolated power contact.

[0022] Furthermore, a magnetic isolation barrier is provided between the PoE power supply unit and the CT power supply unit of the dual redundant power management module, and the magnetic isolation barrier is composed of layers of permalloy sheets.

[0023] In summary, due to the adoption of the above technical solution, the beneficial effects of this utility model are:

[0024] 1. By replacing traditional relays with gallium nitride (GaN) switch arrays, parasitic capacitance and inductance effects are significantly reduced, effectively reducing high-frequency signal attenuation and waveform distortion. Combined with dynamic switch matrix and ADC sampling circuit, high-precision switching and parallel acquisition of signal paths are achieved, ensuring the integrity and real-time performance of topology feature signals and significantly improving the accuracy of topology state judgment.

[0025] 2. The three-stage hybrid filtering unit (magnetic bead, common-mode choke, and microwave absorption cavity) covers low-frequency to high-frequency noise suppression. Combined with the physical isolation amplification design, it blocks common-ground path conducted interference. The modular expansion slot's optical and magnetic isolation structure further isolates high and low voltage circuits, resisting complex electromagnetic environment interference from the hardware level and ensuring stable operation of the system in high-noise scenarios.

[0026] 3. The star-shaped expansion contact module's six-contact probe array supports hot-swappable access to multi-protocol daughterboards. Combined with the standardized protocol compatibility of the FMC high-speed interface, it enables plug-and-play and parallel expansion of communication modules (HPLC / Bluetooth / LoRa). The modular slot design allows for flexible adaptation to third-party function daughterboards, meeting the diverse needs of scenarios such as new energy power plants and smart substations.

[0027] 4. The combination of LVDS differential pairs and grounding copper strips ensures the integrity of high-speed signal transmission and anti-crosstalk capability; the dual redundant power management module is powered in parallel through PoE and CT, and seamless switching is achieved by combining with the LTC3871 bidirectional DC-DC module. It can still maintain stable power supply under extreme conditions (such as lightning strikes and load changes) to avoid the risk of system downtime. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0029] Figure 1 This is a diagram of the overall working architecture of this utility model;

[0030] Figure 2 This is a schematic diagram of the architecture of the dynamic switch matrix module of this utility model. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0032] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.

[0033] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediary element present. Conversely, when an element is said to be "directly" connected to another element, there is no intermediary element. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] In such Figure 1 As shown, a measurement switch topology identification module includes: a dynamic switch matrix module, an anti-interference signal conditioning module, a communication module, a star-shaped expansion contact module, a modular expansion slot interface module, and a dual-redundant power management module; the output of the dynamic switch matrix module is connected to the anti-interference signal conditioning module via a shielded twisted pair cable; the anti-interference signal conditioning module is connected to the communication module via a coaxial cable; the output of the communication module is connected to the modular expansion slot interface module via an LVDS differential pair and a grounding copper strip; the modular expansion slot interface module is connected to the star-shaped expansion contact module via an FPC flexible ribbon cable; and the dual-redundant power management module supplies power to the above modules.

[0035] In this plan, such as Figure 2 As shown, the dynamic switch matrix module includes a GaN switch array, an ADC sampling circuit, and an FPGA chip. The GaN switch array is connected to the ADC sampling circuit via an LVDS bus. The FPGA chip is connected to the ADC sampling circuit via an SPI interface. The ADC sampling circuit is connected in parallel with each switch node of the GaN switch array unit via shielded twisted-pair cables. Further, the GaN switch array consists of several gallium nitride (GaN) switches. The GaN switches are arranged in a four-layer PCB layout, including a signal layer, an FR-4 dielectric layer, a power layer, and a ground layer from top to bottom. The copper foil thickness of the power layer is 2 oz, and the thickness of the FR-4 dielectric layer is 0.8 mm. The ground layer is connected to the heat dissipation pads of the GaN switches via an array of vias.

[0036] The GaN switch array uses EPC2053 gallium nitride transistors. Its drive signal terminal (Pin3) receives control signals via an LVDS differential bus (e.g., H11 / H12 pins on the FPGA), and its source terminal (Pin1) is connected in parallel to the differential input pins of the ADC (AIN1+ / AIN1- of the ADS131M08) via shielded twisted-pair cable. The ADC sampling circuit uses the TI ADS131M08 chip, whose SPI interface (SCLK, SDI, SDO, CS) is connected to the FPGA via pins D5-D8 of Bank13. The reference voltage terminal (VREF) is externally connected to an ADR4540 reference source. The power supply pins (VCCINT / VCCIO) of the FPGA chip (Xilinx Artix-7 XC7A50T) are powered through a 2oz copper foil power layer and are linked with the LTC4357 power monitoring chip to ensure power supply stability. The GaN switch array, ADC, and FPGA are connected to the FPGA via a four-layer PCB with signal, power, and ground layers. The ground layer is connected to the GaN heat sink via a via array, forming a complete signal acquisition and control link.

[0037] During implementation, in the topology identification process, the FPGA generates LVDS differential control signals according to preset logic, driving the GaN switch array to rapidly switch conduction states and form the target measurement path. The ADC sampling circuit acquires the voltage and current signals of each switch node in real time through shielded twisted-pair cables, and the 24-bit high-precision ADC ensures accurate quantization of the signal amplitude. The FPGA reads the ADC data at a clock rate of 20MHz via the SPI bus and uses an internal hardwired state machine to achieve strict synchronization between the sampling timing and the switching action (error <1ns). After the acquired data is buffered by a FIFO, it is uploaded to the main control unit for topology analysis via the PCIe interface. Throughout the process, the low parasitic parameter characteristics of the GaN switches reduce high-frequency signal attenuation, while the power and ground plane design of the four-layer PCB effectively suppresses common-mode interference, ensuring the integrity and real-time performance of signal transmission.

[0038] In implementation, the GaN switch array uses EPC2053 devices with an on-resistance of 0.5Ω, a withstand voltage of 100V, and a 3mm×3mm LGA package, supporting high-frequency switching above 10MHz. The ADC sampling circuit uses the ADS131M08 chip, which has 24-bit resolution, 8-channel synchronous sampling capability, an input range of ±2.5V, and a power consumption of 25mW / channel. The FPGA uses a Xilinx Artix-7XC7A50T-2CSG324I with 16,600 logic cells, supporting LVDS 1.25Gbps high-speed transmission. The PCB adopts a four-layer structure: the top layer is the signal layer (1oz copper thickness), the middle layer 1 is FR-4 dielectric (0.8mm thick), the middle layer 2 is a 2oz copper foil power layer, and the bottom layer is a 1oz copper foil ground layer. The heat dissipation pads of the GaN switches are connected to the ground layer through a 0.3mm aperture via array to ensure low-resistance and high-efficiency heat dissipation path. The GaN switch array is centrally located in the right half of the top layer of the PCB, with adjacent switches spaced 2.5mm apart. The heat dissipation pads are connected to the bottom ground plane via a 4×4 via array. The ADC sampling circuit is located near the GaN output, in the left half of the top layer, with differential trace lengths ≤15mm. It is covered by a tin-plated copper mesh shield (coverage ≥90%), and both ends are soldered to the ground copper foil. The FPGA chip is centrally located, with the LVDS bus using serpentine equal-length wiring (error ±0.1mm) and trace lengths ≤30mm. T-Global TG-1000 thermal grease is applied to the bottom of the GaN switches, achieving efficient heat dissipation through the ground copper foil. During PCB mounting, the shielded twisted-pair cable and coaxial connector are bolted to the metal housing to prevent poor contact due to mechanical vibration.

[0039] In implementation, the dynamic switch matrix module replaces traditional relays with GaN switches, significantly reducing parasitic capacitance and inductance in the signal transmission path, minimizing high-frequency signal attenuation and waveform distortion, and improving topology identification accuracy. The combination of LVDS differential bus and shielded twisted-pair cable effectively suppresses electromagnetic interference, ensuring signal transmission integrity and noise immunity. The four-layer PCB power and ground plane design optimizes power supply stability, and combined with via heat dissipation structures, ensures long-term reliability of the module under high loads. Modular layout and standardized interfaces support flexible expansion, adapting to various communication protocols and functional daughterboards to meet the rapid deployment needs of complex scenarios.

[0040] In this solution, the anti-interference signal conditioning module includes a digital potentiometer, a three-stage filtering unit, and an isolation amplifier. The digital potentiometer is connected in series at the input of the ADC sampling circuit. The three-stage filtering unit is cascaded and connected to the isolation amplifier, and its output is transmitted to the FPGA chip via a coaxial connector. The three-stage filtering unit includes a cascaded ferrite bead, a common-mode choke, and a waveguide cavity. The input of the ferrite bead is connected in parallel to the output of the GaN switch array via a shielded twisted-pair cable. The waveguide cavity is composed of an aluminum alloy shell and a ferrite-based broadband microwave absorbing material MCS-30. The outer wall of the waveguide cavity and the common-mode choke are bonded together with conductive adhesive. The inner wall of the aluminum alloy shell of the waveguide cavity has a serrated protrusion structure, and the ferrite-based broadband microwave absorbing material MCS-30 is filled into the cavity by injection molding.

[0041] The digital potentiometer used is an ADI AD5293 digitally controlled potentiometer (10kΩ, 256 taps, 0.1Ω resolution). Its VDD pin (Pin16) is connected to a 3.3V power supply, and the Wiper pin (Pin5) is connected in series with the AIN1+ input of the ADC sampling circuit (ADS131M08) through a 0.5mm PCB trace. The H / L pins (Pin8 / Pin7) are connected through an I... 2 The C bus (SDA / SCL) connects to the GPIO expander (TCA6416A) of the FPGA.

[0042] In the three-stage filtering unit, the first-stage ferrite bead filter uses a Murata BLM18PG121SN1D ferrite bead (120Ω@100MHz). Its input terminal is connected to the output terminal of the GaN switch array via a shielded twisted pair cable (AWG24, shielding coverage ≥90%), and the output terminal is grounded through a 0.1μF ceramic capacitor (model: GRM155R71H104KE14). The second-stage common-mode choke uses a TDKDLW43SH101XQ2K (100Ω@100MHz), and its input / output pins (Pin1-Pin2 / Pin3-Pin4) are connected in series with the output terminal of the ferrite bead. The housing is soldered to the PCB ground plane through a copper shield (thickness 0.5mm). The three-stage waveguide cavity consists of an aluminum alloy shell (6061-T6, 2mm wall thickness) and Eccosorb MCS-30 absorbing material. The cavity depth is 5mm, and the inner wall has serrated protrusions (0.5mm high, 2mm spacing). The MCS-30 material is injection molded (density 1.2g / cm³). 3The cavity is filled with SMA connectors (model: 142-0701-801) soldered to its input / output terminals. The input terminal is connected to the common-mode choke output terminal via a coaxial cable (RG316, length ≤20mm). The isolation amplifier is an ADI ADuM3190 isolation op-amp (5kVrms withstand voltage). Its input terminal (VIN+ / VIN-) is connected to the waveguide cavity output terminal via a coaxial cable, and its output terminal (VOUT) is connected to the FPGA's ADC input pin (Bank14 pin E9) via a shielded wire (twisted pair + aluminum foil).

[0043] In implementation, the FPGA uses I 2 The C-bus adjusts the tap position of the AD5293 to match the impedance of the ADC input in real time (range 10Ω-10kΩ), eliminating signal reflections caused by impedance abrupt changes. A first-stage ferrite bead filter suppresses low-frequency noise below 100kHz (insertion loss >30dB) and attenuates transient current spikes caused by switching actions. A second-stage common-mode choke blocks common-mode interference in the 1MHz-100MHz band (common-mode rejection ratio >60dB) and suppresses crosstalk between power and ground lines. A third-stage waveguide cavity utilizes the electromagnetic wave absorption characteristics of MCS-30 material to attenuate high-frequency radiated noise in the 1GHz-10GHz range (absorption rate >20dB), and the sawtooth structure on the inner wall of the cavity extends the electromagnetic wave reflection path, enhancing absorption efficiency. The filtered signal is level-shifted and electrically isolated by an ADuM3190 isolation amplifier, blocking common-ground interference between high and low voltage circuits. The output signal is transmitted to the FPGA for digital processing via a shielded cable.

[0044] In practice, the digital potentiometer used is an ADI AD5293 with a resistance of 10kΩ, a resolution of 0.1Ω, and a supply voltage of 3.3V. 2 Communication rate 400kHz. Ferrite bead: Murata BLM18PG121SN1D, impedance 120Ω@100MHz, DC resistance 0.5Ω, rated current 500mA. Common-mode choke: TDK DLW43SH101XQ2K, impedance 100Ω@100MHz, rated current 2A, package size 3.2mm×2.5mm. Waveguide cavity shell material: Aluminum alloy 6061-T6, dimensions 25mm×15mm×5mm, inner wall serration height 0.5mm. Absorbing material: Laird Eccosorb MCS-30, density 1.2g / cm³. 3The frequency band covers 1GHz-10GHz, with an absorption rate ≥20dB. The isolation amplifier is an ADI ADuM3190 with a bandwidth of 200kHz, an isolation withstand voltage of 5kVrms, and a gain error of ±0.1%. The filter unit is located on the top layer of a four-layer PCB, with a spacing of ≤5mm between the ferrite bead and the common-mode choke. The waveguide cavity is externally mounted via an SMA connector. The ground plane is connected to the shielding cover and cavity shell via a via array (0.3mm aperture, 1mm spacing).

[0045] In implementation, the PCB layout places the ferrite bead and common-mode choke near the output of the GaN switch array, located in the left half of the top layer of the PCB. The shielded twisted-pair trace length is ≤15mm, and the outer shielding mesh is soldered to the grounding copper foil. The waveguide cavity is vertically mounted on the right edge of the PCB via an SMA connector. Conductive adhesive (model: 3M 9703) is applied to the bottom of the cavity and bonded to the grounding layer. A heat sink (10mm×10mm) is added to the top of the cavity. The isolation amplifier is located near the FPGA's ADC input pin, on the bottom layer of the PCB, and the signal traces use a microstrip line structure (impedance 50Ω). A copper shield (0.5mm thick) is added around the common-mode choke and connected to the grounding layer via solder joints (2mm spacing). Conductive foam (1mm thick) is filled between the waveguide cavity and the PCB to ensure low-impedance conduction between the cavity and the grounding layer. The aluminum alloy shell of the waveguide cavity is connected to the metal housing via a thermal pad (model: Bergquist GF3000), with a thermal resistance <5℃ / W.

[0046] In implementation, the anti-interference signal conditioning module systematically addresses low-frequency noise, common-mode interference, and high-frequency radiation issues in signal transmission through dynamic impedance matching and a three-stage filtering structure. The combination of ferrite beads and common-mode chokes suppresses conducted interference, the physical absorption design of the waveguide cavity eliminates spatial coupling noise, and the isolation amplifier blocks common-path interference. Modular layout and standardized interfaces (SMA / FPC) simplify the installation process and adapt to the electromagnetic environment requirements of different scenarios. The aluminum alloy casing and conductive adhesive fixing process enhance mechanical stability and ensure long-term reliable operation. This solution significantly improves signal integrity at the hardware level, providing anti-interference assurance for high-precision topology identification.

[0047] In this solution, the communication module includes a tri-mode substrate unit and a protocol switching unit. The tri-mode substrate unit integrates an HPLC modulation chip, a Bluetooth chip, and a LoRa RF front-end, and is connected to the FPGA chip via a PCIe interface. The protocol switching unit includes an ADG1612 analog switch chip. The COM pin of the ADG1612 analog switch chip is connected to the output terminals of the HPLC modulation chip, the Bluetooth chip, and the LoRa RF front-end via a shielded wire. The NO1-NO4 pins of the ADG1612 analog switch chip are connected to the FMC high-speed interface of the modular expansion slot interface module via an IPEX MHF4 coaxial connector, and the VDD pin of the ADG1612 is soldered to an independent power layer of a four-layer PCB.

[0048] The HPLC modulation chip of the tri-mode substrate unit uses a RISE3501 chip (carrier frequency 1MHz-10MHz, data rate 50kbps), and its TX / RX pins (Pin15 / Pin16) are connected to the COM1 / COM2 pins of the ADG1612 analog switch via differential traces (impedance 100Ω). The Bluetooth chip is a CYBLE-416045 (Bluetooth 5.2 SOC, output power +10dBm), and its RF_OUT pin (Pin12) is connected to the COM3 pin of the ADG1612 via a 50Ω microstrip line. The LoRa RF front-end uses an SX1276 chip (band 433MHz, transmit power +20dBm), and its RFIO pin (Pin8) is connected to the COM4 pin of the ADG1612 via a π-type matching network (inductor L = 22nH, capacitor C = 3.3pF). The PCIe interface board is connected to Bank15 (pins F12 / F13) of the FPGA via a PCIe×1 interface (pin definitions: PERST# / Pin12, REFCLK+ / Pin14, REFCLK- / Pin15). The data channels (TX+ / TX- / RX+ / RX-) are directly connected to the FPGA's GTX transceiver via differential pairs (0.15mm line width, 0.3mm spacing).

[0049] The ADG1612 analog switch of the protocol switching unit is a four-channel single-pole single-throw switch (on-resistance 0.5Ω). Its COM1-COM4 pins are connected to the output terminals of HPLC, Bluetooth, and LoRa respectively through shielded wires (RG178, length ≤20mm); NO1-NO4 pins are connected to the differential input pins (VITA57.1 specification Pin A1-A8) of the FMC high-speed interface through IPEX MHF4 coaxial connectors (impedance 50Ω).

[0050] The address pins (A0 / A1) of the ADG1612 are connected via a GPIO expander (TCA6416A, I). 2The C address (0x20) is connected to Bank14 (pin G7 / G8) of the FPGA, and the FPGA sends binary codes to select the communication protocol channel.

[0051] In implementation, the FPGA sends control signals (e.g., A0=0, A1=1) via the TCA6416A according to topology identification requirements, driving the ADG1612 to switch the specified channel (e.g., LoRa's COM4) to the NO4 pin of the FMC interface, achieving dynamic protocol selection. In transmit mode: the FPGA sends data packets to the HPLC / Bluetooth / LoRa chip via the PCIe interface, which then outputs a modulated RF signal. The ADG1612 routes the selected protocol signal to the FMC interface, transmitting it to the expansion daughterboard via LVDS differential pairs. In receive mode: the FMC interface receives signals from external devices, which are switched to the corresponding communication chip by the ADG1612, demodulated, and then transmitted back to the FPGA for processing via the PCIe interface.

[0052] The HPLC differential line is covered with a copper foil shielding layer, and the grounding terminal is soldered to the PCB ground plane. RF isolation: Bluetooth and LoRa signal paths use independent ground planes with a spacing ≥5mm to avoid mutual interference. ---#### III. Models and Parameters Used 1. HPLC modulation chip: RISE3501, carrier frequency 1MHz-10MHz, modulation method FSK, power supply voltage 3.3V, power consumption 120mW. Bluetooth chip CYBLE-416045, supports BLE 5.2, transmit power -20dBm to +10dBm, receive sensitivity -97dBm. LoRa RF front-end SX1276, frequency band 433MHz, spreading factor 7-12, bandwidth 125kHz-500kHz. Analog switch ADG1612, on-resistance 0.5Ω, switching time <50ns, power supply voltage 5V, package TSSOP-16. The PCIe interface conforms to the PCIe 1.0 standard, with a speed of 2.5GT / s, a differential impedance of 100Ω, and a mating / removal life of ≥1,000 cycles. 6. PCB Parameters: The four-layer PCB structure is as follows: Top layer (signal layer, 1oz copper thickness), Middle layer 1 (power layer, 2oz copper thickness), Middle layer 2 (ground layer, 1oz copper thickness), and Bottom layer (shielding layer, 1oz copper thickness). RF traces are 50Ω microstrip lines (0.3mm trace width, FR-4 dielectric layer, 0.8mm thickness).

[0053] In implementation, the three-mode substrate layout is as follows: HPLC chip: located near the PCIe interface, in the left half of the top layer of the PCB, with differential pair length ≤25mm, and shielded by an outer copper foil layer. Bluetooth / LoRa chip: located in the right half of the top layer of the PCB, with a spacing of ≥10mm between the two, and a 2mm wide grounding copper strip for isolation. PCIe connector: fixed to the edge of the PCB via SMT pads (0.65mm spacing), with a reinforcing steel plate (0.8mm thick) below the slot.

[0054] Protocol switching unit installation: ADG1612 chip: positioned between the tri-mode substrate and the FMC interface, COM pin shield length ≤15mm, with continuous grounding copper foil below the trace. IPEX connector: fixed by reflow soldering, coaxial cable bending radius ≥3 times the wire diameter to avoid signal reflection. 3. Shielding and heat dissipation: A metal shielding cover (material: nickel-plated copper, thickness 0.3mm) is added to the Bluetooth / LoRa area, connected to the ground layer via conductive foam (model: 3M 9713). Thermal grease (model: T-Global TG-1000) is applied to the back of the HPLC chip, and heat is conducted to the underlying metal heat sink through a via array (0.3mm aperture).

[0055] The communication module, through multi-protocol hardware integration and dynamic switching design, achieves parallel support and seamless switching of multiple communication methods such as HPLC, Bluetooth, and LoRa. The hardware routing mechanism of the ADG1612 analog switch avoids software protocol stack latency, improving real-time performance; the high-speed transmission capability (2.5GT / s) of the PCIe interface ensures efficient interaction of large amounts of topology information. Modular layout and FMC standardized interface design support plug-and-play third-party daughterboards (such as Wi-Fi and ZigBee), significantly expanding application scenarios. Physical isolation and shielding measures for the RF path effectively suppress signal crosstalk, ensuring communication stability in complex electromagnetic environments.

[0056] In this solution, the star-shaped extended contact module includes a six-contact gold-plated spring probe array, wherein three power contacts are welded to the output terminal of the dual redundant power management module, and three signal contacts are connected to the communication module via FPC cables; the gold-plated spring probes of the six-contact gold-plated spring probe array adopt a double helical spring structure, and the probe base is fixed to the ceramic insulating substrate by laser welding.

[0057] In this solution, the modular expansion slot interface module includes an FMC high-speed interface, which is connected to the FPGA chip via an LVDS differential pair; the interface slot of the modular expansion slot interface module is equipped with an OM3 multimode fiber channel and magnetically isolated power contacts.

[0058] The gold-plated spring probes are Harwin M50-3600542 double-helix spring probes, with a probe diameter of 1.0mm, a gold plating thickness of ≥3μm, an elastic stroke of 1.2mm, and a contact resistance of <5mΩ. The tail pins (Pin1-Pin6) of each probe are laser-welded to the gold-plated pads on the ceramic substrate. The ceramic insulating substrate is made of 96% alumina (Al2O3), with dimensions of 25mm × 25mm × 1.5mm, and features a thick-film printed circuit. This includes a power contact group: three contacts (Pin1-Pin3) connected to the VOUT+ / VOUT- output terminals of the dual redundant power management module (Pin8 / Pin9 of the LTC3871) via 0.5mm wide copper foil traces, with a trace spacing ≥2mm to meet safety requirements. Signal contact group: Three contacts (Pin4-Pin6) are connected to the PCIe interface of the communication module (TX+ / TX- pins of the RISE3501 chip) via an FPC cable (model: FFC-10P-0.5mm). The FPC cable uses a 10-core 0.5mm pitch flexible circuit board (0.1mm line width, covered with a polyimide insulating layer), of which three cores are used for power transmission (0.3mm line width, 2A current carrying capacity), and three cores are used for differential signal transmission (100Ω impedance). The two ends of the FPC cable are crimped and fixed by ZIF connectors (model: FH12-6S-0.5SH).

[0059] When an external daughterboard is inserted, the gold-plated probes form a physical connection with the daughterboard's gold fingers (0.8μm thick gold plating layer) through the elastic pressure of a double helical spring (contact force ≥0.5N), ensuring low-impedance power and signal conduction. The 12V / 5A power output from the dual redundant power management module is transmitted to the probes through the copper foil traces on the ceramic substrate, and then powers external devices via the daughterboard's gold fingers. The PCIe differential signals (TX+ / TX-) of the communication module are transmitted to the probes via the FPC cable, and then transmitted back to the main control unit via the daughterboard, supporting 40Gbps high-speed communication. 3. Hot-swapping support: The probes' elastic travel (1.2mm) and the flexibility of the FPC cable allow the daughterboard to be inserted and removed while energized, with a insertion / removal life ≥10,000 cycles.

[0060] In implementation, the probe array is mounted on the right edge of the PCB, with six contacts symmetrically distributed in a 60° star shape. The center-to-center spacing of the probes is 4.5mm, precisely aligned with the daughterboard slot (30mm × 15mm). The ceramic substrate is bonded to the top layer of the PCB using epoxy resin adhesive (model: 3MDP460). The grounding copper foil at the bottom of the substrate is connected to the PCB ground layer via an array of vias (0.3mm diameter, 1mm spacing). The probes are soldered to the ceramic substrate pads using an IPG laser soldering machine, with the soldering temperature controlled below 300℃ to prevent ceramic thermal cracking. After soldering, a 20μm thick conformal coating (model: Humiseal 1B73) is applied to prevent oxidation and moisture corrosion. One end of the FPC cable is inserted into the ZIF connector of the communication module, with the tightening force adjusted by a screw (M1.4, torque 0.1N·m); the other end is fixed to the signal contact area of ​​the ceramic substrate using conductive tape (model: 3M 9703) to avoid stress concentration.

[0061] In implementation, the star-shaped expansion contact module achieves highly reliable and high-density power and signal transmission through a double-helix probe elastic contact and ceramic substrate insulation design. The six-contact star layout supports parallel access of multiple daughterboards and is compatible with various communication protocols such as HPLC, Bluetooth, and LoRa, significantly enhancing the module's scalability. Flexible FPC cable connections and ZIF interface crimping technology ensure signal integrity and support 40Gbps high-speed data transmission. The probe's elastic travel and laser welding fixing process provide vibration resistance and long lifespan characteristics, suitable for frequent insertion and removal scenarios in industrial environments. The high withstand voltage and low dielectric loss characteristics of the ceramic substrate block crosstalk between power and signal paths, ensuring stable operation in complex electromagnetic environments. This solution breaks through the expansion limitations of traditional pin interfaces at the hardware structure level, providing a standardized and highly compatible expansion interface for smart grid equipment.

[0062] In this solution, the dual-redundant power management module includes a PoE power supply unit and a CT power supply unit connected in parallel. The PoE power supply unit and the CT power supply unit are soldered to the main power bus through an LTC3871 bidirectional DC-DC module. A magnetic isolation barrier is provided between the PoE power supply unit and the CT power supply unit of the dual-redundant power management module. The magnetic isolation barrier is composed of layers of permalloy sheets.

[0063] The PoE controller uses the TPS2378 chip (supporting the IEEE 802.3bt standard, input voltage 36V-57V). Its VIN pin (Pin1) is connected to the power supply pair (Pin4 / Pin5) of the RJ45 interface, and its VOUT pin (Pin6) is connected to the SW1 node (Pin12) of the LTC3871 through a MOSFET (model: CSD18540Q5A). The isolation transformer is a Würth Elektronik 7491965111A (1500V withstand voltage, 1:1 turns ratio). Its primary coil (Pin1-Pin2) is connected to the RJ45 interface, and the secondary coil (Pin3-Pin4) is output to the TPS2378 through a rectifier diode (MBRS340T3G). The current transformer for the CT power supply unit uses a VACUUMSCHMELZE T60404-N5040-X312 (500:1 turns ratio, ±0.5%). Its secondary side (Pin5-Pin6) is connected to the SW2 node (Pin14) of the LTC3871 via a full-bridge rectifier circuit (diode: 1N5822G). The voltage regulator circuit uses an LM317T adjustable regulator (output 5V / 3A). Its input terminal (Vin) is connected to the CT rectified output, and the ADJ pin (Pin1) sets the output voltage through a resistor divider network (R1 = 240Ω, R2 = 720Ω). The input pins (SW1 / SW2) of the LTC3871 bidirectional DC-DC module are connected to the PoE and CT power supply outputs respectively, and the output pin (VOUT / Pin8) is connected to the main power layer via a 2oz copper foil power bus. The enable pins (RUN1 / Pin5, RUN2 / Pin7) are connected to the FPGA's GPIO (Bank14 pins B10 / B11) via optocouplers (model: TLP185) to achieve power supply mode switching. The magnetic isolation barrier is constructed from layers of permalloy sheets (model: HyMu 80, thickness 0.1mm) (total thickness 1.2mm), installed between the PoE and CT power supply units, and fixed by epoxy resin adhesive (model: 3M DP460).

[0064] In implementation, this module employs dual-power supply coordination: PoE power supply mode: When the Ethernet cable is connected, the TPS2378 controller detects an effective voltage (36V-57V), activates the isolation transformer output, and boosts the voltage to 12V via the LTC3871 to power the main power bus. CT power supply mode: When the line current is ≥5mA, the current transformer senses electrical energy, which is rectified by a full-bridge rectifier and regulated to 5V by an LM317T. This 5V is then stepped down to 12V by the LTC3871 and connected in parallel to the main power bus.

[0065] In implementation, the LTC3871 monitors the two input voltages in real time. When PoE power fails, the CT power-on mode takes over the power supply within <2ms (via MOSFET switching of SW1 / SW2), ensuring uninterrupted system operation. A permalloy barrier blocks magnetic field coupling between the PoE and CT power-on paths, and in actual measurements, it can attenuate common-mode noise by ≥40dB, preventing high-frequency switching noise from interfering with signal circuits through the power layer. Overcurrent protection is also included: the LTC3871's ISENSE pin (Pin9) monitors current through a 0.01Ω sampling resistor (model: WSL2010), with a trigger threshold of 10A. Overheat protection: the PoE controller TPS2378's TSD pin (Pin10) is connected to an NTC thermistor (model: MF52-103), shutting down the output when the temperature exceeds 85℃.

[0066] In implementation, the PoE power supply unit is located on the left edge of the PCB, near the RJ45 interface (model: HR911105A). The distance between the TPS2378 chip and the isolation transformer is ≤10mm to reduce high-frequency radiation. The CT power supply unit is installed on the right side of the PCB, with the current transformer fixed by clips (model: MISUMI SSF-5). The distance between the rectifier circuit and the LM317T is ≤5mm. The LTC3871 module is centrally located, with the SW1 / SW2 pins connected to the PoE and CT power output terminals via short leads (≤5mm in length). After the permalloy sheets are stacked, they are bonded to the PCB slot (1.5mm wide) between the PoE and CT units using epoxy resin, and both sides are connected to the ground plane via copper pillars (M3 screws). The bottom of the LTC3871 is coated with thermal paste (model: T-Global TG-1000) and connected to the underlying metal heatsink (material: 6063 aluminum, size: 20mm×20mm×5mm) via an array of vias (0.3mm diameter, 1mm spacing). A heatsink fin (model: Aavid 7021) is mounted on top of the PoE isolation transformer and secured with thermal adhesive.

[0067] The dual-redundant power management module, through a parallel design of PoE and CT power supply, significantly improves the system's power supply reliability under extreme conditions (such as grid fluctuations and lightning strikes). The LTC3871 bidirectional DC-DC module enables seamless switching between the two power sources, ensuring stable main power bus voltage (fluctuation <1%) and preventing topology identification interruptions. A permalloy magnetic isolation barrier blocks electromagnetic coupling between power paths, reducing high-frequency noise interference to the signal link. Modular layout and short lead design reduce transmission losses, support 20A high-current output, and meet the parallel power supply requirements of multiple daughterboards. This solution addresses the vulnerability and insufficient anti-interference capabilities of traditional single-power modules at the hardware level, providing a highly reliable and compatible power supply foundation for smart grid equipment.

[0068] While specific embodiments of this utility model have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of this utility model. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result according to substantially the same method falls within the scope of this utility model. Therefore, the scope of this utility model is defined only by the appended claims.

Claims

1. A measurement switch topology identification module, characterized in that: include: Dynamic switch matrix module, anti-interference signal conditioning module, communication module, star-shaped expansion contact module, modular expansion slot interface module, and dual redundant power management module; The dynamic switch matrix module includes a GaN switch array, an ADC sampling circuit, and an FPGA chip; The anti-interference signal conditioning module includes a digital potentiometer, a three-stage filtering unit, and an isolation amplifier; The communication module includes a tri-mode substrate unit and a protocol switching unit; the tri-mode substrate unit integrates an HPLC modulation chip, a Bluetooth chip and a LoRa RF front-end, and is connected to the FPGA chip via a PCIe interface. The star-shaped extended contact module includes a six-contact gold-plated spring probe array, wherein three power contacts are soldered to the output terminal of the dual redundant power management module, and three signal contacts are connected to the communication module via an FPC cable; The modular expansion slot interface module includes an FMC high-speed interface, which is connected to the FPGA chip via an LVDS differential pair. The dual-redundant power management module includes a PoE power supply unit and a CT power supply unit connected in parallel. The PoE power supply unit and the CT power supply unit are soldered to the main power bus through an LTC3871 bidirectional DC-DC module. The output of the dynamic switch matrix module is connected to the anti-interference signal conditioning module via a shielded twisted pair cable; the anti-interference signal conditioning module is connected to the communication module via a coaxial cable; the output of the communication module is connected to the modular expansion slot interface module via an LVDS differential pair and a ground copper strip. The modular expansion slot interface module is connected to the star-shaped expansion contact module via an FPC flexible cable; the dual redundant power management module supplies power to the above modules.

2. The measurement switch topology identification module according to claim 1, characterized in that: The GaN switch array is connected to the ADC sampling circuit via an LVDS bus; the FPGA chip is connected to the ADC sampling circuit via an SPI interface; and the ADC sampling circuit is connected in parallel with each switch node of the GaN switch array unit via shielded twisted-pair cables.

3. The measurement switch topology identification module according to claim 1, characterized in that: The GaN switch array consists of several gallium nitride (GaN) switches; the GaN switches are arranged in a four-layer PCB layout, including a signal layer, an FR-4 dielectric layer, a power layer, and a ground layer from top to bottom; the copper foil thickness of the power layer is 2 oz, and the thickness of the FR-4 dielectric layer is 0.8 mm; the ground layer is connected to the heat dissipation pads of the GaN switches through an array of vias.

4. The measurement switch topology identification module according to claim 1, characterized in that: The digital potentiometer is connected in series at the input of the ADC sampling circuit; the three-stage filtering unit is cascaded and connected to the isolation amplifier, and the output is transmitted to the FPGA chip via a coaxial connector.

5. The measurement switch topology identification module according to claim 1, characterized in that: The three-stage filtering unit includes a cascaded ferrite bead, a common-mode choke, and a waveguide cavity. The input end of the ferrite bead is connected in parallel with the output end of the GaN switch array via a shielded twisted-pair cable. The waveguide cavity is composed of an aluminum alloy shell and ferrite-based broadband microwave absorbing material MCS-30. The outer wall of the waveguide cavity and the common-mode choke are bonded and fixed together with conductive adhesive.

6. The measurement switch topology identification module according to claim 5, characterized in that: The inner wall of the aluminum alloy shell of the waveguide cavity is provided with a serrated protrusion structure, and the ferrite-based broadband microwave absorbing material MCS-30 is filled into the cavity by injection molding.

7. The measurement switch topology identification module according to claim 1, characterized in that: The protocol switching unit includes an ADG1612 analog switch chip. The COM pin of the ADG1612 analog switch chip is connected to the output of the HPLC modulation chip, Bluetooth chip, and LoRa RF front-end through a shielded wire. The NO1-NO4 pins of the ADG1612 analog switch chip are connected to the FMC high-speed interface of the modular expansion slot interface module through an IPEX MHF4 coaxial connector, and the VDD pin of the ADG1612 is soldered to an independent power layer of a four-layer PCB.

8. The measurement switch topology identification module according to claim 1, characterized in that: The gold-plated spring probes of the six-contact gold-plated spring probe array adopt a double helical spring structure, and the probe base is fixed to the ceramic insulating substrate by laser welding.

9. A measurement switch topology identification module according to claim 1, characterized in that: The modular expansion slot interface module is equipped with an OM3 multimode fiber optic channel and magnetically isolated power contacts in its interface slot.

10. A measurement switch topology identification module according to claim 1, characterized in that: A magnetic isolation barrier is provided between the PoE power supply unit and the CT power supply unit of the dual redundant power management module. The magnetic isolation barrier is composed of layers of permalloy sheets.

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