Semiconductor device

Abstract

A semiconductor device including a raised semiconductor region, an isolation structure, a hard mask layer and a dielectric layer is provided. The convex semiconductor region is adjacent to the concave semiconductor region, and the isolation structure is located above the concave semiconductor region; the hard mask layer is over the isolation structure, and the dielectric layer is over the hard mask layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a wide range of electronic devices, such as computers, mobile phones, and other electronic equipment. Semiconductor devices include integrated circuits (ICs), which are formed on a semiconductor wafer by depositing various types of thin films of material on top of the wafer and patterning those thin films. ICs include field-effect transistors (FETs), such as metal-oxide-semiconductor (MOS) transistors.

[0003] One of the goals of the semiconductor industry is to continue shrinking the size of individual FETs and increasing their speed. To achieve these goals, nanosheet fin FETs (FinFETs) or multi-gate devices, such as gate-all-around (GAA) FETs, are being used. FinFETs and multi-gate devices not only increase areal density but also improve gate control of the channel. Utility Model Content

[0004] Some embodiments disclosed herein provide a semiconductor device including: a raised semiconductor region, an isolation structure, a hard mask layer, and a dielectric layer. The raised semiconductor region is adjacent to a recessed semiconductor region, and the isolation structure is located above the recessed semiconductor region; the hard mask layer is located above the isolation structure, and the dielectric layer is located above the hard mask layer.

[0005] Some embodiments disclosed herein provide a semiconductor device including a recessed semiconductor region, an isolation structure, a hard mask layer, and a dielectric layer. The recessed semiconductor region is located between a first raised semiconductor region and a second raised semiconductor region; the isolation structure is located above the recessed semiconductor region; the hard mask layer is located above the isolation structure; and the dielectric layer is located above the hard mask layer.

[0006] Some embodiments disclosed herein provide a semiconductor device including a recessed semiconductor region, an isolation structure, a hard mask layer, a dielectric layer, and a plurality of metal gates. The recessed semiconductor region is located between a first raised semiconductor region and a second raised semiconductor region, extending from the end wall of the first raised semiconductor region to the end wall of the second raised semiconductor region; the isolation structure is located above the recessed semiconductor region; the hard mask layer is located above the isolation structure; the dielectric layer is located above the hard mask layer; and the plurality of metal gates are located above the first raised semiconductor region, above the second raised semiconductor region, and above the isolation structure. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In practice, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a top view of a semiconductor device during the manufacturing stage according to some embodiments;

[0009] Figure 2 for Figure 1 A cross-sectional view of the semiconductor device taken along line 2-2;

[0010] Figure 3 The flowchart illustrates a method according to some embodiments;

[0011] Figures 4 to 10 for Figure 2 A cross-sectional view of a semiconductor device during the continuous manufacturing process;

[0012] Figure 11 and Figure 12 for Figure 2 A cross-sectional view of an alternative embodiment of a semiconductor device during a continuous manufacturing stage;

[0013] Figures 13 to 15 for Figure 2 A cross-sectional view of an alternative embodiment of a semiconductor device during a continuous manufacturing stage;

[0014] Figures 16 to 18 for Figure 15 and Figure 2 A cross-sectional view of an embodiment of a semiconductor device during the continuous manufacturing stage.

[0015] [Symbol Explanation]

[0016] 100: Semiconductor device / apparatus

[0017] 120: Gap

[0018] 130: Trench

[0019] 200: Protruding structure / fin

[0020] 201: First adjacent fin / Adjacent fin

[0021] 202: Second adjacent fin / Adjacent fin

[0022] 205:End wall

[0023] 210: Bottom section / part

[0024] 220: Upper part / section

[0025] 221, 501: top surface

[0026] 300: Structure / Gate

[0027] 301: Sacrificial Material

[0028] 380: Gate Mask

[0029] 390: Gate Mask

[0030] 400:Substrate

[0031] 401, 402: Semiconductor layer / epitaxy layer / epitaxy growth layer

[0032] 403: Epitaxial Stacking

[0033] 500: Shallow Trench Isolation Feature / STI Feature

[0034] 600: Cover layer / Oxide layer / Silicon oxide layer / Material

[0035] 700: Hard Screen

[0036] 710: Rigid Coverage Layer

[0037] 720: Dielectric material

[0038] 730: Nitrogen ions

[0039] 800: Method

[0040] 900: Dielectric layer

[0041] S802, S804, S806, S808, S810, S812, S814, S816, S818, S820:

[0042] operate

[0043] 2-2: Line

[0044] X, Y, Z: Direction Detailed Implementation

[0045] The following disclosure provides numerous different embodiments or instances of various features for implementing the subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific embodiments or instances are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. As used herein, “directly above” means a vertical alignment of features such that when an overlay feature is directly above an underlying feature, the vertical axis passes through both features. Additionally, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0046] Additionally, for ease of description, spatial relative terms (such as "directly above," "above," "overlapping," "on top," "top," "below," "subordinate to," "below," "below," "lower," "bottom," "side," "positive slope," "negative slope," and similar terms) may be used herein to describe the relationship between one component or feature and another as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatial relative descriptive terms used herein may be interpreted accordingly.

[0047] Unless otherwise expressly indicated, all figures indicating quantities, material proportions, physical properties of materials, and / or uses in this specification shall be understood to be modified by the word “about.” When modifying numerical values ​​in the specification or claims, “about” indicates a range of accuracy familiar and acceptable to those skilled in the art. Generally, this range of accuracy is ±10%. Therefore, “about ten” means nine to eleven.

[0048] In some embodiments herein, a “material layer” is a layer comprising at least 50 wt.% of the identified material (e.g., at least 60 wt.% of the identified material, or at least 75 wt.% of the identified material, or at least 90 wt.% of the identified material); and a “material” layer comprises at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, or at least 90 wt.% of the identified material. For example, in some embodiments, each of the titanium nitride layer and the titanium nitride layer is a layer of at least 50 wt.%, at least 60 wt.%, at least 75 wt.% titanium nitride, or at least 90 wt.% titanium nitride.

[0049] For the sake of brevity, well-known technologies related to semiconductor device manufacturing are not described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive processes or procedures with additional functionality not described in detail herein. Specifically, various processes in semiconductor device manufacturing are well-known, and therefore, for the sake of brevity, many processes are simply mentioned or omitted entirely without providing well-known process details. As will be apparent to those skilled in the art upon fully reading this disclosure, the structures disclosed herein can employ various technologies and can be incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures contain varying numbers of elements, and a single element shown in the description may represent multiple elements.

[0050] Some embodiments described herein are generally related to FinFETs or multi-gate transistors. Multi-gate transistors include those transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate devices may comprise p-type metal-oxide-semiconductor devices or n-type metal-oxide-semiconductor multi-gate devices. Specific examples may be presented herein and referred to as gate-all-around (GAA) devices. A GAA device includes any device in which its gate structure or a portion thereof is formed on all four sides of a channel region (e.g., surrounding a portion of the channel region).

[0051] The structures presented herein also include embodiments having channel regions in the form of nanosheets. The term "nanosheet" refers to any portion of material having a nanometer or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to both elongated material portions with circular and substantially circular cross-sections, such as nanowires, and beam-shaped or strip-shaped material portions having, for example, cylindrical or substantially rectangular cross-sections.

[0052] As described herein, a method is provided for protecting shallow trench isolation (STI) features during an etching process. For example, a hard mask layer may be formed over or based on the STI feature. Subsequently, a sacrificial material may be deposited over the hard mask and etched to form a sacrificial structure. Due to the presence of the hard mask layer, the underlying STI feature is not etched, or is only slightly etched, during the etching of the sacrificial material.

[0053] In some embodiments, a hard mask, such as silicon oxide (SiO2) STI features, is selectively formed on the STI (shallow trench isolation). The hard mask serves as a protective layer to prevent the loss of STI oxides downstream, i.e., during later etching processes, such as HR cleaning and dry etching processes in multi / EPI loops. Specifically, the hard mask exhibits stronger resistance to wet / dry etching compared to the STI feature material.

[0054] Methods for forming an STI hard mask may include selectively depositing an N-containing dielectric layer, selectively depositing a dielectric layer followed by nitriding the dielectric layer, or selectively nitriding STI oxides.

[0055] After the STI hard mask is formed, the polysilicon lines are located on the STI hard mask rather than on the oxide layer. This avoids significant loss of STI feature material and, consequently, polysilicon line collapse caused by STI feature material loss. Otherwise, this polysilicon line collapse would reduce electrical efficiency and yield.

[0056] It should be noted that although the accompanying drawings and description illustrate the structure of a gate-all-around (GAA) device, it is contemplated that the methods described herein can be used to manufacture other types of devices, and the devices described herein can be of other types.

[0057] For the purposes of the following discussion, Figure 1 A top view of a semiconductor device 100 during an intermediate stage of manufacturing is provided. As shown, the semiconductor device 100 includes protrusions 200 or fins 200. Parallel fins 200 extend in the X direction and are spaced apart from each other by slots 120 in the Y direction. Furthermore, each fin 200 is separated from its adjacent fin in the X direction by a cavity or trench 130.

[0058] exist Figure 1 During the intermediate stage of the manufacturing process shown, sacrificial structures 300, such as sacrificial gates 300 or polysilicon structures 300, are formed above fins 200 and trenches 130. The parallel sacrificial gates 300 extend in the Y direction and are spaced apart from each other in the X direction.

[0059] Now for reference Figure 2 , showing along Figure 1The line 2-2 in the middle is cut off Figure 1 A cross-sectional view of a semiconductor device 100 in the intermediate stage of manufacturing.

[0060] like Figure 2 As shown, the fin 200 is formed from an underlying semiconductor substrate 400 and alternating semiconductor layers 401 and 402 formed above the semiconductor substrate 400. Therefore, the fin 200 includes a mesa or bottom portion 210 and a nanosheet or upper portion 220. Furthermore, the fin 200 has substantially vertical endwalls 205. Additionally, the fin 200 has an uppermost surface 221.

[0061] The groove 130 extends from the end wall 205 of the first adjacent fin 201 to the end wall 205 of the second adjacent fin 202.

[0062] like Figure 2 As shown, a shallow trench isolation (STI) feature 500 is formed in the trench 130 and extends from the end wall 205 of the first adjacent fin 201 to the end wall 205 of the second adjacent fin 202. The STI feature 500 has an uppermost surface 501.

[0063] like Figure 2 As shown, a cover layer 600, such as an oxide layer 600, is formed above the uppermost surface 221 of the fin 200, along the end wall 205 of the fin 200, and above the uppermost surface 501 of the STI feature 500.

[0064] like Figure 2 As shown, a hard mask 700 is formed above the oxide layer 600 on the uppermost surface 501 of the STI feature 500, i.e. in the trench 130.

[0065] like Figure 2 As shown, the sacrificial gate 300 is formed above the fin 200 and the STI feature 500. Above the fin 200, the sacrificial gate 300 is directly located on the oxide layer 600. Above the STI feature 500, the sacrificial gate 300 is directly located on the hard mask 700.

[0066] like Figure 2 As shown, the first gate mask 380 and the second gate mask 390 can be located above the sacrificial gate 300.

[0067] Figure 3 A flowchart illustrating a method 800 for manufacturing a semiconductor device 100 is provided. (In conjunction with...) Figure 1 and Figure 2 as well as Figures 4 to 12 describe Figure 3 , Figure 1 and Figure 2 as well as Figures 4 to 12This disclosure describes a semiconductor device 100 at various stages of manufacturing according to some embodiments of method 800. Method 800 is merely an example and is not intended to limit this disclosure to the scope expressly described in the claims. Additional steps may be provided before, during, and after method 800, and some steps described may be moved, replaced, or eliminated for additional embodiments of method 800. Additional features may be added to the semiconductor device depicted in the drawings, and some features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0068] As with other method embodiments and apparatuses discussed herein, it should be understood that the various parts of the semiconductor device 100 can be manufactured using typical semiconductor technology process flows, and therefore only some processes are briefly described herein. Furthermore, the semiconductor device may include a variety of other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but are simplified for a better understanding of the inventive concept of this disclosure. In some embodiments, the device includes multiple interconnectable semiconductor devices (e.g., transistors), including PFETs, NFETs, etc. Moreover, it should be noted that the process steps of method 800, including any descriptions given in conjunction with the accompanying drawings, are illustrative only and are not intended to limit the scope beyond that specifically set forth in the claims, as are the remainder of the methods and drawings provided in this disclosure.

[0069] In operation S802, method 800 ( Figure 3 Provide substrate 400, such as Figure 4As shown. In some embodiments, substrate 400 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 400 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 400 may include various doping configurations depending on design requirements known in the art. For example, different doping profiles (e.g., p-wells, n-wells) may be formed in regions on substrate 400 designed for different device types (e.g., n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for p-wells and phosphorus (P) for n-wells. In some embodiments, substrate 400 includes a single crystalline semiconductor layer at least on its surface portion. Substrate 400 may include a single crystalline semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 400 may comprise compound semiconductors and / or alloy semiconductors. In the illustrated embodiment, substrate 400 is made of crystalline Si.

[0070] like Figure 4 As shown, in operation S804, method 800 ( Figure 3 One or more epitaxial layers are formed over a substrate 400. In some embodiments, an epitaxial stack 403 is formed over the substrate 400. The epitaxial stack 403 includes an epitaxial layer 401 of a first composition into which an epitaxial layer 402 of a second composition is inserted. The first composition and the second composition may be different. Embodiments are possible, including those providing a first composition and a second composition with different oxidation rates and / or etch selectivity. In an embodiment, epitaxial layer 401 is SiGe and epitaxial layer 402 is silicon. In an embodiment where epitaxial layer 401 contains SiGe and epitaxial layer 402 contains silicon, the oxidation rate of silicon is less than the oxidation rate of SiGe. It should be noted that the three layers of epitaxial layer 401 and three layers of epitaxial layer 402 are illustrated in the drawings for illustrative purposes only and are not intended to limit the scope beyond that specifically described in the claims. It will be understood that any number of epitaxial layers can be formed in the epitaxial stack 403; the number of layers depends on the number of channel regions required by the device 100. In some embodiments, the number of epitaxial layers 402 is between two and ten, such as six or seven.

[0071] In some embodiments, epitaxial layer 401 has a thickness ranging from about 5 nanometers (nm) to about 15 nm. The thickness of epitaxial layer 401 may be substantially uniform. In some embodiments, epitaxial layer 402 has a thickness ranging from about 5 nm to about 15 nm. In some embodiments, the stacked epitaxial layers 402 have a substantially uniform thickness. As described in more detail below, epitaxial layer 402 may be used as a channel region for a subsequently formed multi-gate device and has a thickness selected based on device performance considerations. Epitaxial layer 401 may be used to define gaps between adjacent channel regions for a subsequently formed multi-gate device and has a thickness selected based on device performance considerations.

[0072] For example, the epitaxial growth of the epitaxial stack 403 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer, such as epitaxial layer 402, comprises the same material as the substrate 400. In some embodiments, epitaxial growth layers 401 and 402 comprise materials different from the substrate 400. As described above, in at least some instances, epitaxial layer 401 comprises epitaxially grown Si. 1-x Ge x The epitaxial layer 401 comprises a silicon (Si) layer epitaxially grown (where x is from about 10% to about 55%), and the epitaxial layer 402 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers 401 and 402 may comprise other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP; or combinations thereof. As discussed, the materials of the epitaxial layers 401 and 402 may be selected based on providing different oxidation, etch selectivity properties. In various embodiments, the epitaxial layers 401 and 402 are substantially dopant-free (i.e., having about 0 cm⁻¹). -3 To approximately 1 x 10 17 cm -3 The concentration of intriguing dopants is specified, for example, during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack 403 are SiGe layers (not shown). In an alternative embodiment, the bottom layer of the epitaxial stack 403 is a Si layer, and the top layer of the epitaxial stack 403 is a SiGe layer (not shown).

[0073] like Figure 4 As shown, in operation S806, method 800 ( Figure 3The epitaxial stack 403 is patterned to form semiconductor fins 200 and trenches 130. In some embodiments, operation S806 includes forming a mask layer (not shown) over the epitaxial stack 403. The mask layer may include a first mask sublayer and a second mask sublayer. A first mask sublayer is a pad oxide layer made of silicon oxide, which may be formed using thermal oxidation. A second mask sublayer is made of silicon nitride (SiN), which may be formed using chemical vapor deposition (CVD), including low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. The mask layer is patterned into a mask pattern using a patterning operation including lithography and etching. Operation S806 then involves patterning the epitaxial stack 403 through openings defined in a patterned mask layer in an etching process such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The stacked epitaxial layers 401 and 402 are thus patterned into fins 200. The process used to form the fins 200 may result in gaps between parallel fins 200 and trenches between adjacent fins 201 and 202.

[0074] In various embodiments, each fin 200 includes an upper portion 220 of staggered epitaxial layers 401 and 402 and a bottom portion 210 formed by etching the substrate 400. Each fin 200 projects upward from the substrate 400 in the Z direction and extends longitudinally in the X direction. The sidewalls of each fin 200 may be straight or inclined (not shown). The fins 200 may have the same width or different widths.

[0075] like Figure 5 As shown, in operation S808, method 800 ( Figure 3Shallow trench isolation (STI) features (also referred to as STI features) 500 are formed in trenches 130 adjacent to each fin 200 having a dielectric layer. Each STI feature 500 contacts the endwall 205 of each adjacent fin 200. The STI feature 500 can be formed by first filling the trenches 130 around each fin 200 with a dielectric material layer to cover the top surface and sidewalls (not shown) of the fin 200. The dielectric material layer may contain one or more dielectric materials. The dielectric material layer may contain silicon oxide (SiO2). Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating techniques. Subsequently, the dielectric material layer is planarized using, for example, chemical mechanical planarization (CMP) until the top surface of the mask layer (not shown) is exposed, and the dielectric material layer is recessed to form a shallow trench isolation (STI) feature (also referred to as STI feature) 500, such as... Figure 5 As shown. In the illustrated embodiment, the STI feature 500 is formed on the substrate 400. Any suitable etching technique can be used to recess the isolation feature 500, including dry etching, wet etching, RIE, and / or other etching methods. In this embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature 500 without etching the fins 200. A mask layer (not shown) can also be removed before, during, and / or after the isolation feature 500 is recessed. In some embodiments, the mask layer is removed using a CMP process performed before the isolation feature 500 is recessed. In some embodiments, the mask layer is removed using an etchant used to recess the isolation feature 500.

[0076] like Figure 6 As shown, in operation S810, method 800 ( Figure 3 As appropriate, a capping layer 600, such as an oxide layer 600, i.e., a silicon oxide layer 600, may be formed over the fin 200 and the shallow trench isolation (STI) feature 500. As shown, the oxide layer 600 contacts the uppermost surface 221 of the fin 200, the end wall 205 of the fin 200, and the uppermost surface 501 of the STI feature 500.

[0077] like Figure 7 As shown, in operation S812, method 800 ( Figure 3A rigid mask layer 710 is formed above the cover layer 600. Figure 7 In this embodiment, the hard mask layer 710 is deposited as a nitrogen-containing dielectric material. For example, the hard mask layer 710 is deposited as a material selected from SiC. x N 1-x SiO x N 1-x SiO x C y N 1-x-y SiN x Nitrogen-containing dielectric materials, or other low-k film materials. In embodiments, a hard mask layer 710 is deposited via an anisotropic deposition process with bias capability to selectively deposit material on the capping layer 600 above the uppermost surface 221 of the fin 200 and above the uppermost surface 501 of the STI feature 500, while restricting deposition on the capping layer 600 on the end wall 205, such that the thickness of the hard mask layer 710 along the end wall 205 is less than the thickness of the hard mask layer 710 above the uppermost surfaces 221 and 501. In some embodiments, the hard mask layer 710 is not formed along the end wall 205.

[0078] like Figure 8 As shown, in operation S814, method 800 ( Figure 3 The hard mask layer 710 is removed from above the uppermost surface 221 of the fin and along the end wall 205. Thus, the hard mask 700 is defined above the STI feature 500 and within the trench 130. In some embodiments, the hard mask 700 has a thickness from 0 nm to 20 nm in the Z direction. For example, the hard mask thickness can be at least 0.1 nm, at least 0.5 nm, at least 1 nm, at least 2 nm, at least 5 nm, at least 10 nm, or at least 15 nm. Furthermore, the hard mask thickness can not exceed 20 nm, such as not exceeding 15 nm, not exceeding 10 nm, not exceeding 6 nm, not exceeding 5 nm, not exceeding 4 nm, not exceeding 2 nm, or not exceeding 1 nm.

[0079] like Figure 9 As shown, in operation S816, method 800 ( Figure 3 A sacrificial material 301 is deposited over device 100. In some embodiments, the sacrificial material 301 may comprise a sacrificial gate dielectric material and a sacrificial gate electrode material. Therefore, operation S816 may comprise first blanket deposition of a sacrificial gate dielectric layer. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 1 nm to about 5 nm.

[0080] Subsequently, a sacrificial gate electrode layer is deposited as a blanket on the sacrificial gate dielectric layer. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nm to about 200 nm. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD.

[0081] Furthermore, a gate mask 380 and a gate mask 390 are formed above the sacrificial material 301. The gate mask 380 may be silicon oxide, and the gate mask 390 may be silicon nitride. Figure 10 As shown, gate masks 380 and 390 are patterned and etched.

[0082] Return to reference Figure 2 In operating S818, method 800 ( Figure 3 Etch the sacrificial material to form the sacrificial structure 300, as described.

[0083] Subsequently, method 800 can continue further processing in operation S820. For example, spacers can be formed, source / drain regions can be defined and formed, the sacrificial gate structure can be removed and replaced with a metal gate structure, additional dielectric and conductive layers can be formed and patterned, and typical back-end-of-line (BEOL) processing can be performed.

[0084] like Figure 18 As shown, further processing may include forming one or more dielectric layers 900, such as interlayer dielectric (ILD) or pre-metal dielectric (PMD) materials, over the device 100. As shown, a portion of the dielectric layer 900 is located within the trench 130 and can directly contact the rigid mask 700. In embodiments including a cover layer 600, which may be selected as appropriate, the cover layer 600 separates the dielectric layer 900 from the end walls 205 and the uppermost surface 221 of the fin 200. In embodiments where the cover layer 600 is not formed, the dielectric layer 900 can contact the end walls 205 and the uppermost surface 221 of the fin 200.

[0085] As described above, operation S812 forms a rigid mask layer 710 above the cover layer 600. Relative to... Figure 7 Operation S812 is described as being performed by depositing a nitrogen-containing dielectric material. However, other embodiments may perform operation S812 in different ways.

[0086] For example, in Figure 11 In operation S812, method 800 ( Figure 3 A hard mask layer 710 is formed above the capping layer 600 by first depositing a nitrogen-free dielectric material 720. The dielectric material 720 can be selected from SiC, SiO, or SiO2. x C y Si or other low-k film materials. In embodiments, dielectric material 720 is deposited via an anisotropic deposition process with bias capability to selectively deposit material on the capping layer 600 above the uppermost surface 221 of fin 200 and above the uppermost surface 501 of STI feature 500, while restricting deposition on the material 600 on end wall 205 such that the thickness of dielectric material 720 along end wall 205 is less than the thickness of dielectric material 720 above the uppermost surfaces 221 and 501. In some embodiments, dielectric material 720 is not formed along end wall 205.

[0087] In addition, Figure 12 In step S812, operation S812 includes performing a nitriding process to nitrid the dielectric material 720. The nitriding process can be a nitrogen implantation process or a nitriding annealing process. For example, nitrogen ions 730 can be implanted into the dielectric material 720. This can be done at energies from 500 eV to 10 keV and at a density of 1 E15 atoms / cm². 2 Up to 1E17 atoms / cm 2 The dosage and the nitrogen implantation process are performed at temperatures ranging from -100°C to 500°C. The nitriding annealing process can be performed using annealing gases selected from NH3, N2, N2+H2, N2O, NH3 radicals, N2 radicals, N2+H2 radicals, N2O radicals, or mixtures thereof at temperatures ranging from 100°C to 1400°C and pressures ranging from 0.01 atm to 25 atm.

[0088] As Figure 12 As a result of the nitriding process, apparatus 100 is formed with the as described above. Figure 7 The structure is such that the method can continue in operation S814.

[0089] As described above, operation S810 for forming the cover layer 600 is selected as appropriate. In some embodiments, the cover layer 600 is not formed. Furthermore, in such embodiments, operation S812 may form a hard mask layer 710 without depositing any additional layers.

[0090] Specifically, such as Figure 13 As shown, Figure 5 The structure of the device 100 can be processed in operation S812 by performing a nitriding process to nitrid the uppermost surface 221 of the fin, the end wall 205 of the fin 200, and the uppermost surface 501 of the STI feature 500 to form a hard mask layer 710. The nitrided portions of the fin 200 and the STI feature 500 form the hard mask layer 710.

[0091] Nitriding processes can be either nitrogen implantation or nitriding annealing. They can be performed at energies from 500 eV to 10 keV, with 1 E15 atoms / cm². 2 Up to 1E17 atoms / cm 2 The dosage and the nitrogen implantation process are performed at temperatures ranging from -100°C to 500°C. The nitriding annealing process can be performed using annealing gases selected from NH3, N2, N2+H2, N2O, NH3 radicals, N2 radicals, N2+H2 radicals, N2O radicals, or mixtures thereof at temperatures ranging from 100°C to 1400°C and pressures ranging from 0.01 atm to 25 atm.

[0092] Figure 14 This describes the process after removing the hardened diaphragm layer 710 above the uppermost surface 221 of the fin and along the end wall 205 during operation S814. Figure 13 The structure of the embodiment is as follows. Therefore, the rigid mask 700 is defined above the STI feature 500 and within the trench 130. In some embodiments, the rigid mask 700 has a thickness from 0 nanometers (nm) to 20 nanometers in the Z direction. For example, the rigid mask thickness can be at least 0.1 nm, at least 0.5 nm, at least 1 nm, at least 2 nm, at least 5 nm, at least 10 nm, or at least 15 nm. Furthermore, the rigid mask thickness can not exceed 20 nm, such as not exceeding 15 nm, not exceeding 10 nm, not exceeding 6 nm, not exceeding 5 nm, not exceeding 4 nm, not exceeding 2 nm, or not exceeding 1 nm. Figure 14 In this context, there is no overlay 600 that can be selected as needed.

[0093] Figure 15 Explanation after executing operations S816 and S818 Figure 13 and Figure 14 The structure of the embodiment makes Figure 15 The structure is in the same position as Figure 2 The same manufacturing stage. Therefore, Figure 15 Provided in Figure 1 Another embodiment of the semiconductor device 100 in the intermediate manufacturing stage, to follow Figure 1 The cross-sectional view taken from line 2-2 is shown.

[0094] like Figure 15 As shown, the fin 200 is formed from an underlying semiconductor substrate 400 and alternating semiconductor layers 401 and 402 formed above the semiconductor substrate 400. Therefore, the fin 200 includes a mesa portion 210 and a nanosheet portion 220. Furthermore, the fin 200 has substantially vertical endwalls 205. Additionally, the fin 200 has an uppermost surface 221.

[0095] The groove 130 extends from the end wall 205 of the first adjacent fin 201 to the end wall 205 of the second adjacent fin 202.

[0096] like Figure 15 As shown, a shallow trench isolation (STI) feature 500 is formed in the trench 130 and extends from the end wall 205 of the first adjacent fin 201 to the end wall 205 of the second adjacent fin 202. The STI feature 500 has an uppermost surface 501.

[0097] like Figure 15 As shown, a hard mask 700 is formed above the uppermost surface 501 of the STI feature 500, i.e. in the groove 130.

[0098] like Figure 15 As shown, the sacrificial gate 300 is formed above the fin 200 and the STI feature 500. Above the fin 200, the sacrificial gate 300 is directly located on the uppermost fin surface 221. Above the STI feature 500, the sacrificial gate 300 is directly located on the hard mask 700.

[0099] like Figure 15 As shown, the first gate mask 380 and the second gate mask 390 can be located above the sacrificial gate 300.

[0100] Now for reference Figure 16 and Figure 17 Each of these describes what happens after some further processing. Figure 15 and Figure 2 A cross-sectional view of the structure. For example, diluted HF cleaning / dry etching can be performed in the EPI loop. As shown, the hard mask 700 covers and protects the underlying STI feature 500. Therefore, the sacrificial structure 300 covering the STI feature 500 is less prone to collapse.

[0101] In an embodiment, the method of forming a semiconductor device includes forming a shallow trench isolation (STI) feature; forming a mask layer over the STI feature; depositing a sacrificial material over the mask layer; and etching the sacrificial material to form a sacrificial structure over the mask layer, wherein the mask layer prevents the STI feature from being etched while etching the sacrificial material.

[0102] In some embodiments, the method further includes forming an oxide layer over the STI feature, wherein a mask layer is formed over the oxide layer, and wherein the mask layer prevents etching of the oxide layer while etching the sacrificial material.

[0103] In some embodiments of the method, the masking layer comprises a nitrogen-containing dielectric material.

[0104] In some embodiments of the method, forming a shallow trench isolation (STI) feature includes etching a semiconductor material to form a cavity between adjacent active regions; and depositing an isolation material in the cavity.

[0105] In some embodiments of the method, forming a mask layer over an STI feature includes performing a nitriding process to form a nitrided layer according to the STI feature, wherein the nitrided layer is a mask layer.

[0106] In some embodiments of the method, forming a mask layer over the STI feature includes forming a dielectric layer over the STI feature; and performing a nitriding process to form a nitrided layer based on the dielectric layer, wherein the nitrided layer is a mask layer.

[0107] In some embodiments of the method, forming a mask layer over the STI feature involves depositing a nitrogen-containing dielectric material over the STI feature.

[0108] In some embodiments of the method, forming a mask layer over the STI feature includes performing a nitriding process to form a nitriding layer, wherein the nitriding process is performed at an energy of 500 eV to 10 keV and 1 E15 atoms / cm². 2 Up to 1E17 atoms / cm 2 The dosage and the nitrogen application process performed at temperatures ranging from -100°C to 500°C.

[0109] In some embodiments of the method, forming a mask layer over the STI feature includes performing a nitriding process to form a nitrided layer, wherein the nitriding process is a nitriding annealing process performed using an annealing gas selected from NH3, N2, N2+H2, N2O, NH3 radical, N2 radical, N2+H2 radical, N2O radical, or mixtures thereof at a temperature of 100°C to 1400°C and a pressure of 0.01 atm to 25 atm.

[0110] In another embodiment, the method of forming a semiconductor device includes: etching a semiconductor material to form a cavity between adjacent active regions; depositing an isolation material in the cavity to form a shallow trench isolation (STI) feature; forming a mask layer over the STI feature and over the adjacent active regions; removing the mask layer from over the adjacent active regions; depositing a sacrificial gate material over the mask layer over the STI feature and over the adjacent active regions; and etching the sacrificial gate material to form a sacrificial gate over the mask layer over the STI feature and over the adjacent active regions, wherein the mask layer prevents the STI feature from being etched while etching the sacrificial gate material.

[0111] In some embodiments, the method further includes forming an oxide layer over the STI feature and over an adjacent active region, wherein a mask layer is formed over the oxide layer, and wherein a sacrificial gate is formed over the oxide layer.

[0112] In some embodiments of the method, forming a mask layer over the STI feature and adjacent active regions includes performing a nitriding process to form a nitrided layer based on the STI feature and adjacent active regions, wherein the nitrided layer is a mask layer.

[0113] In some embodiments of the method, forming a mask layer over the STI feature and over the adjacent active region includes: forming a dielectric layer over the STI feature and over the adjacent active region; and performing a nitriding process to form a nitrided layer based on the dielectric layer, wherein the nitrided layer is a mask layer.

[0114] In some embodiments of the method, forming a mask layer above the STI feature and above the adjacent active region includes depositing a nitrogen-containing dielectric material above the STI feature and above the adjacent active region.

[0115] In some embodiments, the method further includes forming an alternating stack of semiconductor layers to form the semiconductor material before etching the semiconductor material to form a cavity between adjacent active regions.

[0116] In another embodiment, the semiconductor device includes: a raised semiconductor region adjacent to a recessed semiconductor region; an isolation structure located above the recessed semiconductor region; a hard mask layer located above the isolation structure; and a dielectric layer located above the hard mask layer.

[0117] In some embodiments, the device further includes an oxide layer located above the isolation structure and the raised semiconductor region, wherein the hard mask layer is located above the oxide layer.

[0118] In some embodiments of the device, the rigid cover layer is a nitrided layer of an isolation structure.

[0119] In some embodiments of the device, the hard mask layer is a nitrided layer of dielectric material.

[0120] In some embodiments of the device, the rigid shielding layer is a nitrogen-containing dielectric material.

[0121] In some embodiments of the device, the isolation structure contacts the endwall of the raised semiconductor region.

[0122] In another embodiment, the semiconductor device includes a recessed semiconductor region, an isolation structure, a hard mask layer, and a dielectric layer. The recessed semiconductor region is located between a first raised semiconductor region and a second raised semiconductor region; the isolation structure is located above the recessed semiconductor region; the hard mask layer is located above the isolation structure; and the dielectric layer is located above the hard mask layer.

[0123] In some embodiments of the device, the recessed semiconductor region extends from the end wall of the first raised semiconductor region to the end wall of the second raised semiconductor region.

[0124] In some embodiments of the device, the isolation structure extends from the endwall of the first raised semiconductor region to the endwall of the second raised semiconductor region.

[0125] In some embodiments of the device, the semiconductor device further includes a plurality of metal gates located above the first raised semiconductor region, above the second raised semiconductor region, and above the isolation structure.

[0126] In some embodiments of the device, a dielectric layer is located between the plurality of metal gates.

[0127] In another embodiment, the semiconductor device includes a recessed semiconductor region, an isolation structure, a hard mask layer, a dielectric layer, and a plurality of metal gates. The recessed semiconductor region is located between a first raised semiconductor region and a second raised semiconductor region, extending from the end wall of the first raised semiconductor region to the end wall of the second raised semiconductor region; the isolation structure is located above the recessed semiconductor region; the hard mask layer is located above the isolation structure; the dielectric layer is located above the hard mask layer; and the plurality of metal gates are located above the first raised semiconductor region, above the second raised semiconductor region, and above the isolation structure.

[0128] In some embodiments of the device, the plurality of metal gates are located directly on the hard mask layer.

[0129] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a raised semiconductor region adjacent a recessed semiconductor region; an isolation structure over the recessed semiconductor region; a hardmask layer over the isolation structure; and a dielectric layer over the hardmask layer. Further comprising:

2. The semiconductor device according to claim 1, wherein an oxide layer over the isolation structure and over the raised semiconductor region, wherein the hardmask layer is over the oxide layer. The isolation structure contacts an end wall of the raised semiconductor region.

3. The semiconductor device according to claim 1 or 2, wherein Comprising:

4. A semiconductor device, characterized by comprising: a recessed semiconductor region between a first raised semiconductor region and a second raised semiconductor region; an isolation structure over the recessed semiconductor region; a hardmask layer over the isolation structure; and a dielectric layer over the hardmask layer. The recessed semiconductor region extends from an end wall of the first raised semiconductor region to an end wall of the second raised semiconductor region. The isolation structure extends from an end wall of the first raised semiconductor region to an end wall of the second raised semiconductor region.

5. The semiconductor device according to claim 4, wherein Further comprising a plurality of metal gates over the first raised semiconductor region, over the second raised semiconductor region, and over the isolation structure.

6. The semiconductor device according to claim 4 or 5, wherein The dielectric layer is between the plurality of metal gates.

7. The semiconductor device according to claim 4 or 5, wherein Comprising:

8. The semiconductor device according to claim 7, wherein a recessed semiconductor region between a first raised semiconductor region and a second raised semiconductor region, the recessed semiconductor region extending from an end wall of the first raised semiconductor region to an end wall of the second raised semiconductor region; 9. A semiconductor device, characterized by comprising: an isolation structure over the recessed semiconductor region; a hardmask layer over the isolation structure; and a dielectric layer over the hardmask layer; and a plurality of metal gates over the first raised semiconductor region, over the second raised semiconductor region, and over the isolation structure. The plurality of metal gates are directly over the hardmask layer. ​ ​ 10. The semiconductor device according to claim 9, wherein ​

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