Trench gate silicon carbide VDMOS capable of inhibiting bipolar degradation
By designing a trench gate and body diode structure and using a floating gate and buffer to dissipate energy, the bipolar degradation problem of silicon carbide VDMOS devices was solved, achieving high reliability and fast switching of the devices.
Patent Information
- Application Number
- CN202423285941.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Silicon carbide VDMOS devices are prone to bipolar degradation under bipolar operating conditions, which leads to a reduction in the effective active area of the chip and affects device performance.
By designing a trench gate structure and a body diode structure, and employing a floating gate and buffer design, a Schottky diode is constructed to reduce the pn junction area between the P-type well region and the second drift layer. A buffer is also constructed below the floating gate to consume energy and suppress the release of electron-hole recombination energy.
It effectively suppresses the bipolar degradation effect, reduces the energy release inside the device, and improves the device's reliability and switching speed.
Smart Images
Figure CN223798576U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of trench gate silicon carbide VDMOS of inhibiting bipolar degradation. BACKGROUND
[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. The inhibition of bipolar degradation of VDMOS (vertical double-diffused metal-oxide-semiconductor) refers to a kind of degradation phenomenon that body diode in VDMOS device may appear under certain conditions. This degradation phenomenon mainly refers to that, under bipolar operating conditions, the energy released by the recombination of electrons and holes causes the spread of stacking faults at basal plane dislocation (BPD), which eventually leads to the reduction of the effective active area of the chip, thereby affecting the performance of the device. SUMMARY
[0003] The technical problem to be solved by the utility model is to provide a kind of trench gate silicon carbide VDMOS of inhibiting bipolar degradation, by the design of gate structure and body diode structure, the characteristics of inhibiting bipolar degradation effect of device are realized.
[0004] In the first aspect, the utility model provides a kind of trench gate silicon carbide VDMOS of inhibiting bipolar degradation, comprising:
[0005] Silicon carbide substrate,
[0006] First drift layer, the lower side of the first drift layer is connected to the upper side of the silicon carbide substrate;
[0007] Second drift layer, the lower side of the second drift layer is connected to the upper side of the first drift layer, and the second drift layer is provided with a buffer zone, and the lower side of the buffer zone is connected to the upper side of the first drift layer;
[0008] P-type well region, the lower side of the P-type well region is connected to the upper side of the second drift layer, and the P-type well region is provided with N-type source region;
[0009] Gate dielectric layer, the gate dielectric layer is connected to the upper side of the buffer zone through the second drift layer, and the gate dielectric layer is provided with a floating gate, and the gate dielectric layer is provided with a trench, and the trench is located above the floating gate, and the outer side of the gate dielectric layer is connected to the inner side of the P-type well region and the inner side of N-type source region respectively;
[0010] Gate metal layer, the gate metal layer is arranged in the trench;
[0011] Source metal layer, the source metal layer is connected to the upper side of the second drift layer, P-type well region and N-type source region respectively;
[0012] and a drain metal layer connected to the lower side of the silicon carbide substrate.
[0013] The utility model discloses the advantages are:
[0014] One, the utility model source metal layer is in parallel pattern with N type source area top and P type well area top contact area, is connected with P type well area side surface, and source metal layer bottom surface is flush with P type well area bottom surface, and this structure can effectively reduce the pn junction area of P type well area and second drift layer in the device, thereby reducing the energy release caused by electron and hole recombination, and further inhibiting bipolar degradation;
[0015] Two, the utility model constructs Schottky diode, and Schottky diode is single carrier conduction, thereby inhibiting the parasitic pn junction body diode of traditional silicon carbide VDMOS, and the energy release of reverse recovery caused by bipolar conduction, thereby inhibiting bipolar effect;
[0016] Three, the utility model constructs buffer zone below suspension grid, and the buffer zone outer side is flush with P type well area outer side, and by improving the doping concentration in buffer zone, the energy generated from electron hole recombination between P type well area and second drift layer can be consumed, thereby avoiding energy moving to silicon carbide substrate, and further inhibiting the upward extension of silicon carbide substrate defect, and inhibiting the bipolar degradation effect of device. BRIEF DESCRIPTION OF DRAWINGS
[0017] The utility model will be further described in connection with the embodiments with reference to the drawings.
[0018] Figure 1 It is the schematic diagram of the utility model one kind inhibits bipolar degradation's trench gate silicon carbide VDMOS.
[0019] Figure 2 It is the process section of the utility model one kind inhibits bipolar degradation's trench gate silicon carbide VDMOS Figure 1 .
[0020] Figure 3 It is the process section of the utility model one kind inhibits bipolar degradation's trench gate silicon carbide VDMOS Figure 2 .
[0021] Figure 4 It is the process section of the utility model one kind inhibits bipolar degradation's trench gate silicon carbide VDMOS Figure 3 .
[0022] Figure 5 It is the process section of the utility model one kind inhibits bipolar degradation's trench gate silicon carbide VDMOS Figure 4 .
[0023] Figure 6The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 5 .
[0024] Figure 7 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 6 .
[0025] Figure 8 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 7 .
[0026] Figure 9 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 8 .
[0027] Figure 10 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 9 .
[0028] Figure 11 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 10 .
[0029] Figure 12 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 10 One.
[0030] Figure 13 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 10 Two.
[0031] Figure 14 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 10 Three.
[0032] Figure 15 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 10 Four.
[0033] Figure 16 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 10 Five.
[0034] Figure 17 The utility model discloses a process section view of trench gate silicon carbide VDMOS of inhibiting bipolar degeneration Figure 10 Six. Specific embodiments
[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0039] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0040] like Figure 1 As shown, this application embodiment provides a trench-gate silicon carbide VDMOS for suppressing bipolar degradation, comprising:
[0041] Silicon carbide substrate 1,
[0042] The first drift layer 2, the lower side of the first drift layer 2 is connected to the upper side of the silicon carbide substrate 1;
[0043] The second drift layer 3 has its lower side connected to the upper side of the first drift layer 2. The second drift layer 3 has a buffer zone 31, the lower side of which is connected to the upper side of the first drift layer 2.
[0044] P-type well region 4, the lower side of which is connected to the upper side of the second drift layer 3, and an N-type source region 41 is provided on the P-type well region 4;
[0045] A gate dielectric layer 5 passes through the second drift layer 3 and is connected to the upper side of the buffer 31. A floating gate 51 is provided in the gate dielectric layer 5. A trench 52 is provided on the gate dielectric layer 5. The trench 52 is located above the floating gate 51. The outer side of the gate dielectric layer 5 is connected to the inner side of the P-type well region 4 and the inner side of the N-type source region 41, respectively.
[0046] A gate metal layer 6 is disposed within the trench 52;
[0047] Source metal layer 7, which is connected to the upper side of the second drift layer 3, the P-type well region 4 and the N-type source region 41 respectively;
[0048] And a drain metal layer 8, which is connected to the lower side of the silicon carbide substrate 1.
[0049] In this embodiment, preferably, the width of the buffer 31 is equal to the sum of the width of the P-type well region 4 and the width of the gate dielectric layer 5.
[0050] In this embodiment, preferably, the width of the floating gate 51 is smaller than the width of the gate metal layer 6.
[0051] In this embodiment, preferably, the lower side surface of the gate metal layer 6 and the lower side surface of the P-well region 4 are located on the same plane.
[0052] In this embodiment, preferably, the buffer zone 31 is provided with a groove 311, and the lower part of the gate dielectric layer 5 is disposed in the groove 311.
[0053] In this embodiment, preferably, the source metal layer 7 is connected to the upper side of the second drift layer 3, the outer side of the P-type well region 4, the upper side of the P-type well region 4, and the upper side of the N-type source region 41.
[0054] like Figures 1 to 17 As shown, the above-mentioned method for fabricating trench-gate silicon carbide VDMOS includes the following steps:
[0055] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 8; grow epitaxially on the upper side of silicon carbide substrate 1 to form first drift layer 2;
[0056] Step 2: Epitaxial growth is performed above the first drift layer 2 to form the second drift layer 3;
[0057] Step 3: Form a barrier layer 9 on the second drift layer 3, etch the barrier layer 9 to form a via, and perform ion implantation into the second drift layer 3 to form a buffer zone 31;
[0058] Step 4: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions into the second drift layer 3 to form a P-type well region 4.
[0059] Step 5: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions into the P-type trap region 4 to form the N-type source region 41;
[0060] Step 6: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the second drift layer 3 to the buffer zone 31, and deposit the insulating medium.
[0061] Step 7: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and etch the insulating medium to form a groove 53. Deposit metal to form a floating gate 51.
[0062] Step 8: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, deposit the insulating dielectric to form the gate dielectric layer 5;
[0063] Step 9: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, etch the gate dielectric layer 5 to form a trench 52, deposit metal, and form the gate metal layer 6.
[0064] Step 10: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the second drift layer 3, deposit metal, and form the first source metal region 71.
[0065] Step 11: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and etch the second drift layer 3 to the upper side of the P-type well region 4, deposit metal to form the second source metal region 72, the source metal layer 7 includes the first source metal region 71 and the second source metal region 72.
[0066] In another embodiment of this invention, the silicon carbide substrate 1, the first drift layer 2, the second drift layer 3, and the buffer zone 31 are all N-type; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the first drift layer 2 is 1-5e16cm. -3 The doping concentration of the second drift layer 3 is 1-5e17cm. -3 The doping concentration of P-type well region 4 is 1-2e18cm. -3 The doping concentration of N-type buffer 31 is 3-6e17cm. -3 The gate dielectric layer 5 is silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm. -3 The concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type first drift layer 2 and the second drift layer 3 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. In order to suppress the rapid diffusion of defects in the silicon carbide substrate 1, the structure of the first drift layer 2 and the second drift layer 3 is used to suppress the diffusion of substrate defects, thereby achieving the goal of suppressing the bipolar degradation effect. Since the device adopts a floating gate 51 structure, the insulating dielectric thickness of the floating gate 51 is large, and the gate reliability of the device is high, so no additional shielding area is required. The P-type well region 4 is to form the gate switching characteristics of the device, and the concentration of the N-type source region 41 is to reduce the source contact resistance of the device and reduce the on-resistance of the device.
[0067] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the first drift layer 2 is 30-90 μm, the thickness of the second drift layer 3 is 10-20 μm, and the thickness is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The width of the N-type source region 41 is 60-80% of the width of the P-type well region 4, the width of the P-type well region 4 occupies 50-60% of the device cell, the width of the device cell is 100-500 μm, the thickness of the source metal layer 7 is 800 nm, the thickness of the P-type well region 4 is 500 nm, the thickness of the N-type source region 41 is 200 nm, the total width of the insulating medium on the left and right sides of the gate metal layer 6 is 50 nm, the thickness of the insulating medium between the gate metal layer 6 and the floating gate 51 is 100-300 nm, the total width of the insulating medium on the left and right sides of the floating gate 51 is 200-500 nm, and the thickness of the insulating medium at the bottom of the floating gate 51 is 100-200 nm.
[0068] The gate metal layer 6 is designed to achieve complete inversion of the P-type well regions 4 on both sides of the device and increase the electron concentration of the conductive channels, thereby reducing the on-resistance of the device. Therefore, the insulating dielectric in this region is narrow to ensure the gate control capability of the device. The thickness of the insulating dielectric between the gate metal layer 6 and the floating gate 51 only affects the characteristics of the floating gate. The function of the floating gate 51 is to form an inversion region in the device body to reduce the on-resistance of the device, and has little impact on the overall characteristics of the device.
[0069] In this embodiment, the source metal layer 7 is connected to the upper side of the second drift layer 3, the outer side of the P-type well region 4, the upper side of the P-type well region 4, and the upper side of the N-type source region 41. The source metal layer 7 is parallel in the contact area with the top of the N-type source region 41 and the top of the P-type well region 4. The source metal layer 7 is protruding on one side of the P-type well region 4. The bottom of the protruding part of the source metal layer 7 is flush with the bottom of the P-type well region 4. This structure can effectively reduce the pn junction area between the P-type well region 4 and the second drift layer 3 inside the device, thereby reducing the energy release caused by electron and hole recombination and suppressing bipolar degradation.
[0070] The source metal layer 7 and the second drift layer 3 form a Schottky diode. The Schottky diode is a single-carrier conduction diode, which suppresses the energy release of reverse recovery caused by the bipolar conduction of the parasitic pn junction body diode in the traditional silicon carbide VDMOS, thereby suppressing the bipolar effect.
[0071] An N-type buffer 31 is constructed below the floating gate 51 of the device. By increasing the doping concentration in this region, the energy generated by electron-hole recombination between the P-type well region 4 and the second drift layer 3 can be consumed, thereby preventing energy from moving to the silicon carbide substrate. This suppresses the upward extension of defects in the silicon carbide substrate and inhibits the bipolar degradation effect of the device. At the same time, the N-type buffer 31 also forms a capacitive shield for the gate and drain, thereby reducing the gate-drain capacitance of the device and improving the switching speed of the device.
[0072] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A trench-gate silicon carbide VDMOS that suppresses bipolar degradation, characterized by: Comprising: a silicon carbide substrate, a first drift layer, a lower side of which is connected to an upper side of the silicon carbide substrate; a second drift layer, a lower side of which is connected to an upper side of the first drift layer, and a buffer region is arranged in the second drift layer, a lower side of the buffer region being connected to an upper side of the first drift layer; a P-type well region, a lower side of which is connected to an upper side of the second drift layer, and an N-type source region is arranged on the P-type well region; a gate dielectric layer, a lower side of which is connected to an upper side of the buffer region through the second drift layer, and a floating gate is arranged in the gate dielectric layer, a trench is arranged on the floating gate, and an outer side of the gate dielectric layer is connected to an inner side of the P-type well region and an inner side of the N-type source region, respectively; a gate metal layer, which is arranged in the trench; a source metal layer, which is connected to an upper side of the second drift layer, the P-type well region, and the N-type source region, respectively; and a drain metal layer, which is connected to a lower side of the silicon carbide substrate.
2. A trench-gate silicon carbide VDMOS suppressing bipolar degradation as claimed in claim 1, characterized in that: A width of the buffer region is equal to a sum of a width of the P-type well region and a width of the gate dielectric layer.
3. A trench-gate silicon carbide VDMOS suppressing bipolar degradation as recited in claim 1, wherein: A width of the floating gate is less than a width of the gate metal layer.
4. A trench-gate silicon carbide VDMOS suppressing bipolar degradation as recited in claim 1, wherein: A lower side of the gate metal layer and a lower side of the P-type well region are in the same plane.
5. A trench-gate silicon carbide VDMOS suppressing bipolar degradation as recited in claim 1, wherein: A recess is arranged in the buffer region, and a lower part of the gate dielectric layer is arranged in the recess.
6. A trench-gate silicon carbide VDMOS suppressing bipolar degradation as recited in claim 1, wherein: The source metal layer is connected to an upper side of the second drift layer, an outer side of the P-type well region, an upper side of the P-type well region, and an upper side of the N-type source region, respectively.