Display panel and display device

Abstract

The embodiment of the utility model discloses a display panel and a display device. The display panel comprises a capacitor structure provided with a pixel area; the capacitor structure comprises a first polar plate, a second polar plate and a third polar plate which are sequentially stacked; the second interlayer dielectric layer covers the capacitor structure, the first interlayer dielectric layer covers the capacitor structure, the second interlayer dielectric layer and the first interlayer dielectric layer are stacked to form a stacked structure, the stacked structure forms a sunken structure, and the sunken structure and the third polar plate are overlapped in the thickness direction of the display panel; and the flat layer covers the second interlayer dielectric layer and fills the sunken structure. According to the embodiment of the invention, the metal film layer below the first interlayer dielectric layer is adopted to form the third polar plate, the distance between the third polar plate and the second polar plate is reduced, and the capacitance of the capacitor structure is improved; and secondly, a sunken structure is arranged in the area, corresponding to the capacitor structure, of the stacked structure, and the terrain height of the capacitor structure is reduced, so that the flatness of a pixel area is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) panels fabricated using inkjet printing technology have extremely high requirements for the flatness of the terrain within each pixel. If the terrain difference within a pixel is large, the uniformity of the dry film thickness formed after the luminescent material ink dries will be poor, leading to uneven brightness within the pixel. Due to the demands of display technology for high refresh rates and high resolutions, a metal layer is typically added above the source and drain metal layers to form the anode traces and an additional capacitor plate. The addition of this capacitor plate increases the capacitance value of the capacitor structure to meet the requirements of high refresh rates and high resolutions. Since the pixel area is covered by the capacitor structure, the addition of the capacitor plate results in a higher terrain level in the capacitor layer below the pixel, creating a significant terrain difference with other areas within the pixel, thus affecting the flatness within the pixel. Utility Model Content

[0003] This application provides a display panel and display device that can reduce the topographic height of the capacitor structure, thereby improving the flatness layer in the pixel area.

[0004] This application embodiment provides a display panel including multiple pixel areas, which includes:

[0005] substrate;

[0006] A capacitor structure is disposed on the substrate and located in the pixel region; the capacitor structure includes a first electrode plate, a second electrode plate, and a third electrode plate stacked sequentially.

[0007] A buffer layer covers the first electrode plate and the substrate, and the second electrode plate is disposed on the side of the buffer layer away from the substrate;

[0008] A first insulating portion covers the side of the second electrode plate away from the substrate, and a third electrode plate is disposed on the side of the first insulating portion away from the substrate;

[0009] A first interlayer dielectric layer covers the capacitor structure and the buffer layer;

[0010] A second interlayer dielectric layer covers the first interlayer dielectric layer. The second interlayer dielectric layer and the first interlayer dielectric layer are stacked to form a stacked structure. The stacked structure has a recessed structure that overlaps with the third electrode plate in the thickness direction of the display panel.

[0011] A planar layer covers the second interlayer dielectric layer and fills the recessed structure.

[0012] Optionally, in some embodiments of this application, the recessed structure includes a first opening and a second opening that are interconnected in the thickness direction of the display panel. The first opening penetrates the first interlayer dielectric layer and exposes the third electrode plate. The second opening penetrates the second interlayer dielectric layer. The width of the second opening is greater than the width of the first opening.

[0013] Optionally, in some embodiments of this application, the first opening includes a first lower opening and a first upper opening, the first upper opening is connected to the side of the first lower opening near the second opening, and the third electrode plate includes a middle portion and side portions connected to both sides of the middle portion.

[0014] Both the first lower hole and the first upper hole expose the middle portion of the third electrode plate. The width of the first upper hole is greater than the width of the first lower hole, and the side portion of the third electrode plate is located within the area of ​​the first upper hole.

[0015] Optionally, in some embodiments of this application, the second opening includes a second lower opening and a second upper opening, the second upper opening being connected to the side of the second lower opening away from the first opening, and the sidewall of the second lower opening being coplanar with the sidewall of the first upper opening;

[0016] Both the second lower hole and the second upper hole expose the middle portion of the third electrode plate. The width of the second upper hole is greater than the width of the second lower hole. The side portion of the third electrode plate is located within the area of ​​the second upper hole and the second lower hole.

[0017] Optionally, in some embodiments of this application, the thickness of the first insulating portion is between 1 / 4 and 1 / 3 of the thickness of the first interlayer dielectric layer.

[0018] Optionally, in some embodiments of this application, the display panel further includes a thin-film transistor and a light-shielding portion located in the pixel region. The thin-film transistor includes an active portion, a second insulating portion, a gate, a first electrode, and a second electrode. The light-shielding portion is disposed on the substrate in the same layer as the first electrode plate. The buffer layer covers the light-shielding portion. The active portion and the second electrode plate are disposed in the same layer on the side of the buffer layer away from the substrate. The second insulating portion is disposed on the side of the active portion away from the substrate. The gate is disposed on the side of the second insulating portion away from the substrate. The first interlayer dielectric layer covers the gate.

[0019] The first interlayer dielectric layer has a first contact hole and a second contact hole. The first contact hole penetrates the first interlayer dielectric layer, and the second contact hole penetrates the first interlayer dielectric layer and the buffer layer. The first electrode is connected to one side of the active part through one of the first contact holes, and the second electrode is connected to the other side of the active part through another first contact hole. The second electrode is also connected to the light-shielding part through the second contact hole.

[0020] The first interlayer dielectric layer is further provided with a first groove and a second groove. The first groove is connected to the first contact hole, and the second groove is connected to the first contact hole and the second contact hole. The first electrode is disposed in the first groove, and the second electrode is disposed in the second groove.

[0021] Optionally, in some embodiments of this application, the depth of the first groove is greater than or equal to the thickness of the first electrode, and the depth of the second groove is greater than or equal to the thickness of the second electrode.

[0022] Optionally, in some embodiments of this application, the thickness of the first interlayer dielectric layer is between 4,000 angstroms and 6,000 angstroms, and the depth of the first groove and / or the depth of the second groove is between 2,000 angstroms and 3,000 angstroms.

[0023] Optionally, in some embodiments of this application, the distance from the side of the third electrode away from the substrate to the upper surface of the substrate is less than the distance from the side of the first electrode away from the substrate to the upper surface of the substrate.

[0024] Optionally, in some embodiments of this application, the vertical distance from the side of the third electrode away from the substrate to the side of the first electrode away from the substrate is between 700 angstroms and 1200 angstroms.

[0025] Optionally, in some embodiments of this application, the second interlayer dielectric layer covers the first electrode, the second electrode, and the first interlayer dielectric layer, and the second interlayer dielectric layer has a third contact hole that exposes the second electrode; the display panel includes a passivation layer and traces, and the traces are connected to the second electrode through the third contact hole;

[0026] The second interlayer dielectric layer is further provided with a third groove that connects to the third contact hole, and the trace is disposed in the third groove;

[0027] The passivation layer covers the second interlayer dielectric layer, the trace, and the recessed structure, and the planarization layer covers the passivation layer.

[0028] Optionally, in some embodiments of this application, the thickness of the second interlayer dielectric layer is between 2000 angstroms and 3000 angstroms, and the depth of the third groove is between 1000 angstroms and 1500 angstroms.

[0029] Accordingly, this application also provides a display device, which includes a display panel as described in any of the above embodiments.

[0030] The display panel and display device of this application embodiment include a capacitor structure for disposing the pixel area; the capacitor structure includes a first electrode plate, a second electrode plate, and a third electrode plate stacked sequentially, a buffer layer disposed between the first electrode plate and the second electrode plate; a first insulating portion disposed between the second electrode plate and the third electrode plate; a first interlayer dielectric layer covering the capacitor structure, a second interlayer dielectric layer stacked with the first interlayer dielectric layer to form a stacked structure, the stacked structure forming a recessed structure, the recessed structure overlapping the third electrode plate in the thickness direction of the display panel; a planarization layer covering the second interlayer dielectric layer and filling the recessed structure.

[0031] It should be noted that, compared to adding an additional metal layer above the first interlayer dielectric layer to form a capacitor plate, this embodiment uses a metal film layer below the first interlayer dielectric layer to form a third plate, which reduces the distance between the third plate and the second plate and increases the capacitance of the capacitor structure. Secondly, a recessed structure is provided in the region of the stacked structure corresponding to the capacitor structure to reduce the terrain height of the capacitor structure, thereby reducing the height difference between the terrain of the capacitor structure region and the terrain of other regions, so as to improve the flatness of the pixel region. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0033] Figure 2 yes Figure 1 A partial schematic diagram;

[0034] Figure 3 This is a schematic diagram of step B01 in the display panel manufacturing method provided in the embodiments of this application;

[0035] Figure 4 This is a schematic diagram of step B02 in the display panel manufacturing method provided in the embodiments of this application;

[0036] Figure 5 This is a schematic diagram of step B03 in the display panel manufacturing method provided in the embodiments of this application;

[0037] Figure 6 This is a schematic diagram of step B04 in the display panel manufacturing method provided in the embodiments of this application;

[0038] Figure 7 This is a schematic diagram of step B05 in the display panel manufacturing method provided in the embodiments of this application;

[0039] Figure 8 This is a schematic diagram of step B06 in the display panel manufacturing method provided in the embodiments of this application;

[0040] Figure 9 This is a schematic diagram of step B07 in the display panel manufacturing method provided in the embodiments of this application;

[0041] Figure 10 This is a schematic diagram of step B08 in the display panel manufacturing method provided in the embodiments of this application;

[0042] Figure 11 This is a schematic diagram of step B09 in the display panel manufacturing method provided in the embodiments of this application;

[0043] Figure 12 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0044] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first", "second", "third", etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0045] This application provides a display panel and a display device, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0046] Please refer to Figure 1 This application provides a display panel 100, which includes a plurality of pixel regions xs. The display panel 100 includes a substrate 111, a capacitor structure c1, a buffer layer 112, a first insulating portion 113, a first interlayer dielectric layer 114, a second interlayer dielectric layer 115, and a planarization layer 116.

[0047] The capacitor structure c1 is disposed on the substrate 111 and located in the pixel region xs. The capacitor structure c1 includes a first electrode c01, a second electrode c02 and a third electrode c03 stacked in sequence.

[0048] A buffer layer 112 covers the first electrode plate c01 and the substrate 111. A second electrode plate c02 is disposed on the side of the buffer layer 112 away from the substrate 111. A first insulating portion 113 covers the side of the second electrode plate c02 away from the substrate 111, and a third electrode plate c03 is disposed on the side of the first insulating portion 113 away from the substrate 111.

[0049] The first interlayer dielectric layer 114 covers the capacitor structure c1 and the buffer layer 112. The second interlayer dielectric layer 115 covers the first interlayer dielectric layer 114. The second interlayer dielectric layer 115 and the first interlayer dielectric layer 114 are stacked to form a stacked structure. The stacked structure forms a recessed structure a1. In the thickness direction of the display panel 100, the recessed structure a1 overlaps with the third electrode plate c03. The planarization layer 116 covers the second interlayer dielectric layer 115 and fills the recessed structure a1.

[0050] It should be noted that, compared to the area above the first interlayer dielectric layer 114, an additional metal layer is added to form the capacitor plate. In this embodiment, the third plate c03 is formed by a metal film layer below the first interlayer dielectric layer 114, which reduces the vertical distance between the third plate c03 and the second plate c02, thereby increasing the capacitance of the capacitor structure c1. Secondly, a recessed structure a1 is provided in the region of the stacked structure corresponding to the capacitor structure c1, reducing the terrain height of the capacitor structure c1, thereby reducing the height difference between the terrain of the capacitor structure c1 region and the terrain of other regions, and improving the flatness of the pixel region xs.

[0051] It is understood that the pixel region xs is the area enclosed by the boundary of the opening of the pixel definition layer (not shown in the figure), and a light-emitting material layer is disposed within the opening of the pixel definition layer. The light-emitting material layer is disposed within the opening of the pixel definition layer by inkjet printing.

[0052] Please refer to Figure 1 and Figure 2 Optionally, in some embodiments of this application, the recessed structure a1 includes a first opening 11a and a second opening 11b that are interconnected in the thickness direction of the display panel 100. The first opening 11a penetrates the first interlayer dielectric layer 114 and exposes the third electrode plate c03. The second opening 11b penetrates the second interlayer dielectric layer 115. The width of the second opening 11b is greater than the width of the first opening 11a.

[0053] It is understandable that the first opening 11a and the second opening 11b are used to form a recessed structure a1 in order to minimize the terrain height of the capacitor structure c1 region, reduce the terrain height difference between the capacitor structure c1 region and other regions, and improve the flatness of the pixel region sx.

[0054] Optionally, in some embodiments, the recessed structure a1 may also be based on the topography of the first opening 11a. For example, the second interlayer dielectric layer 115 covers the first opening 11a, so that the second interlayer dielectric layer 115 is recessed to form a groove, and the flat layer 116 fills the recess.

[0055] Optionally, in some embodiments, the recessed structure a1 also includes only the second opening 11b, and the planarization layer 116 fills the second opening 11b.

[0056] Optionally, in some embodiments, the recessed structure a1 is formed by stacking two grooves. For example, a first recessed groove corresponding to the third electrode c03 is provided on the first interlayer dielectric layer 114, the second interlayer dielectric layer 115 covers the first recessed groove, and a second recessed groove corresponding to the first recessed groove is provided on the second interlayer dielectric layer 115. The grooves of the first recessed groove and the grooves of the second recessed groove overlap to form the recessed structure a1. Of course, in some embodiments, the recessed structure a1 may also include only the first recessed groove or the second recessed groove.

[0057] Optionally, in some embodiments of this application, the first opening 11a includes a first lower opening a01 and a first upper opening a02, the first upper opening a02 communicating with the side of the first lower opening a01 near the second opening 11b. The third electrode plate c03 includes a middle portion 031 and side portions 032 connecting the two sides of the middle portion 031.

[0058] Both the first lower hole a01 and the first upper hole a02 expose the middle part of the third electrode plate c03. The width of the first upper hole a02 is greater than the width of the first lower hole a01. The side part of the third electrode plate c03 is located in the area of ​​the first upper hole a02.

[0059] Understandably, the first lower aperture a01 exposes the middle portion 031, reducing the terrain height of the middle region of the capacitor structure c1 and also narrowing the width of the first lower aperture a01; while the first upper aperture a02 expands outward from the first lower aperture a01 to reduce the terrain height of the regions on both sides of the capacitor structure c1. Specifically, by narrowing the opening width of the first lower aperture a01, the volume of the first opening 11a is reduced, decreasing the filling amount of the planarization layer 116. This allows the planarization layer 116 to better level the recessed structure a1, providing flatness for the pixel region sx.

[0060] Optionally, in some embodiments of this application, the second opening 11b includes a second lower opening b01 and a second upper opening b02, the second upper opening b02 communicating with the side of the second lower opening b01 away from the first opening 11a. The sidewall of the second lower opening is coplanar with the sidewall of the first upper opening b02.

[0061] The second lower hole b01 and the second upper hole b02 both expose the middle portion 031 of the third electrode plate c03. The width of the second upper hole b02 is greater than the width of the second lower hole b01. The side portion 032 of the third electrode plate c03 is located within the area of ​​the second upper hole b02 and the second lower hole b01.

[0062] It is understandable that the side portion 032 of the third plate c03 is located in the area of ​​the second upper hole b02 and the second lower hole b01, so that the second lower hole b01 and the second upper hole b02 fully cover the capacitor structure c1 in the pixel opening sx, thereby comprehensively reducing the terrain height of the capacitor structure c1 in the pixel opening sx.

[0063] The display panel 100 includes a passivation layer 117 covering a second interlayer dielectric layer 115 and a recessed structure a1. A planarization layer 116 covers the passivation layer 117.

[0064] Understandably, by connecting the first opening 11a and the second opening 11b to form a multi-level stepped opening, the risk of breakage of the passivation layer 117 at the first opening 11a and the second opening 11b is reduced. Secondly, the gradual change in the multi-level stepped opening avoids abrupt height changes along the axial direction of the pixel opening xs, resulting in a smaller height change rate for the planarization layer 116 during the leveling process, thus improving flatness.

[0065] It is understandable that, since the thickness of the first insulating part 113 is less than the thickness of the first interlayer dielectric layer 114, the distance between the third electrode c03 and the second electrode c02 is reduced, thereby increasing the capacitance of the capacitor structure c1 to meet the requirements of high refresh rate and high resolution.

[0066] Optionally, in some embodiments of this application, the thickness of the first insulating portion 113 is between 1 / 4 and 1 / 3 of the thickness of the first interlayer dielectric layer 114.

[0067] Understandably, the smaller the thickness of the first insulating portion 113, the smaller the distance between the third electrode c03 and the second electrode c02, and the larger the capacitance of the capacitor structure c1, but the worse its insulation. Therefore, to increase the capacitance of the capacitor structure c1 while ensuring the insulating properties of the first insulating portion 113, the thickness of the first insulating portion 113 is selected to be between 1 / 4 and 1 / 3 of the thickness of the first interlayer dielectric layer 114. For example, the thickness of the first insulating portion 113 is 1 / 4, 7 / 24, or 1 / 3 of the thickness of the first interlayer dielectric layer 114.

[0068] Optionally, in some embodiments of this application, the display panel 100 further includes a thin-film transistor t1 located in the pixel region xs and a light-shielding portion 121. The thin-film transistor t1 includes an active portion 122, a second insulating portion 123, a gate 124, a first electrode 125, and a second electrode 126. The light-shielding portion 121 is disposed on the substrate 111 in the same layer as the first electrode co2. A buffer layer 112 covers the light-shielding portion 121. The active portion 122 and the second electrode co2 are disposed in the same layer on the side of the buffer layer 112 away from the substrate 111. The second insulating portion 123 is disposed on the side of the active portion 122 away from the substrate 111. The gate 124 is disposed on the side of the second insulating portion 123 away from the substrate 111, and a first interlayer dielectric layer 114 covers the gate 124.

[0069] The first interlayer dielectric layer 114 has a first contact hole k1 and a second contact hole k2. The first contact hole k1 penetrates the first interlayer dielectric layer 114, and the second contact hole k2 penetrates the first interlayer dielectric layer 114 and the buffer layer 112. The first electrode 125 is connected to one side of the active part 122 through one of the first contact holes k1. The second electrode 126 is connected to the other side of the active part 122 through another first contact hole k1, and the second electrode 126 is also connected to the light-shielding part 121 through the second contact hole k2.

[0070] The first interlayer dielectric layer 114 is further provided with a first groove 11c and a second groove 11d. The first groove 11c is connected to a first contact hole k1, and the second groove 11d is connected to another first contact hole k1 and a second contact hole k2. The first electrode 125 is disposed in the first groove 11c, and the second electrode 126 is disposed in the second groove 11d.

[0071] It is understood that by placing the first electrode 125 in the first groove 11c and the second electrode 126 in the second groove 11d, the first electrode 125 and the second electrode 126 are deposited in the first interlayer dielectric layer 114, so as to reduce the height difference between the topography of the thin film transistor t1 and the topography of other areas, thereby improving the flatness.

[0072] Optionally, in some embodiments of this application, the depth of the first groove 11c is greater than or equal to the thickness of the first electrode 125, and the depth of the second groove 11d is greater than or equal to the thickness of the second electrode 126, so that the first electrode 125 is completely submerged in the first groove 11c and the second electrode 126 is completely submerged in the second groove 11d, thereby minimizing the height difference between the topography of the thin-film transistor t1 and the topography of other areas.

[0073] Optionally, in some embodiments of this application, the thickness of the first interlayer dielectric layer 114 is between 4000 angstroms and 6000 angstroms. The depth of the first groove 11c and / or the depth of the second groove 11d is between 2000 angstroms and 3000 angstroms.

[0074] Understandably, the first interlayer dielectric layer 114 needs to separate the metal film layer containing the first electrode 125 from the underlying traces to reduce the risk of increased load due to mutual interference. Therefore, the first interlayer dielectric layer 114 is relatively thick. For example, the thickness of the first interlayer dielectric layer 114 is 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, or 6000 angstroms.

[0075] Secondly, the depths of the first groove 11c and the second groove 11d are equal, and both are between 2000 angstroms and 3000 angstroms. It is understood that, given that the thicknesses of the first electrode 125 and the second electrode 126 are between 2000 angstroms and 3000 angstroms, the depths of the first groove 11c and the second groove 11d are set equal to the thicknesses of the first electrode 125 and the second electrode 126. This ensures that the first electrode 125 and the second electrode 126 are fully submerged in the first groove 11c and the second groove 11d, while avoiding excessively weak insulation of the first interlayer dielectric layer 114.

[0076] Optionally, the depth of the first groove 11c and / or the second groove 11d can be 2000 angstroms, 2100 angstroms, 2200 angstroms, 2300 angstroms, 2400 angstroms, 2500 angstroms, 2600 angstroms, 2700 angstroms, 2800 angstroms, 2900 angstroms or 3000 angstroms.

[0077] Optionally, in some embodiments of this application, the distance from the side of the third electrode plate c03 away from the substrate 111 to the upper surface of the substrate 111 is less than the distance from the side of the first electrode 125 away from the substrate 111 to the upper surface of the substrate 111.

[0078] Understandably, the first electrode 125 and the second electrode 126 of the thin-film transistor t1 are recessed due to the first groove 11c and the second groove 11d, while the third electrode co3 is the highest film layer of the capacitor structure c1. Given that the first interlayer dielectric layer 114 separates the upper and lower metal film layers to avoid the risk of signal interference between the two metal film layers, the first interlayer dielectric layer 114 needs a certain thickness, resulting in a relatively high height for the first electrode 125 and the second electrode 126. Therefore, setting the first electrode 125 to be higher not only ensures that the thin-film transistor t1 has a lower elevation, but also avoids a large difference in height between it and the capacitor structure c1, thus improving flatness.

[0079] Optionally, in some embodiments of this application, the vertical distance from the side of the third electrode plate c03 away from the substrate 111 to the side of the first electrode 125 away from the substrate 111 is between 700 angstroms and 1200 angstroms.

[0080] Understandably, the distance between the third electrode plate c03 and the first electrode 125 is between 700 angstroms and 1200 angstroms. This avoids a large height difference between the thin-film transistor t1 and the capacitor structure c1, and also takes into account the thickness requirements of the first interlayer dielectric layer 114 to avoid the risk of signal interference.

[0081] Optionally, the vertical distance between the side of the third electrode plate c03 away from the substrate 111 and the side of the first electrode 125 away from the substrate 111 is 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms or 1200 angstroms.

[0082] Optionally, in some embodiments of this application, the second interlayer dielectric layer 115 covers the first electrode 125, the second electrode 126, and the first interlayer dielectric layer 114. The second interlayer dielectric layer 115 has a third contact hole k3 exposing the second electrode 126. The display panel 100 also includes a trace 127, which is connected to the second electrode 126 through the third contact hole k3.

[0083] The second interlayer dielectric layer 115 is further provided with a third groove 11f that connects to the third contact hole k3, and the trace 127 is disposed in the third groove 11f. The passivation layer 117 covers the second interlayer dielectric layer 115, the trace 127, and the recessed structure a1. The planarization layer 116 covers the passivation layer 117.

[0084] It is understandable that the trace 127 in the pixel opening sx region is placed in the third groove 11f, so that the trace 127 is sunk in the second interlayer dielectric layer 115, in order to reduce the height difference between the terrain of the area where the thin film transistor t1 is located and the terrain of other areas, thereby improving flatness.

[0085] Optionally, in some embodiments of this application, the thickness of the second interlayer dielectric layer 115 is between 2000 angstroms and 3000 angstroms. The depth of the third groove 11f is between 1000 angstroms and 1500 angstroms.

[0086] It is understandable that the second interlayer dielectric layer 115 is only configured to separate the film layer where the trace 127 is located from the film layer where the first electrode 125 is located. Therefore, compared with the first interlayer dielectric layer 114, the second interlayer dielectric layer 115 does not need to be too thick, as long as it meets the insulation requirements.

[0087] Secondly, given the relatively thin thickness of the second interlayer dielectric layer 115, the depth of the third groove 11f should not be too deep in order to ensure the insulation of the trace 127 and the underlying metal film layer; therefore, the depth of the third groove 11f is set to be between 1000 angstroms and 1500 angstroms, for example, it can be 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms or 1500 angstroms.

[0088] The method for manufacturing the display panel 100 according to this application includes the following steps:

[0089] Please refer to Figure 3 In step B01, a light-shielding layer, a buffer layer 112, an active layer, a first insulating layer, a first metal layer, and a first interlayer dielectric layer 114 are sequentially formed on the substrate 111. Subsequently, a patterned first photoresist layer pr1 is formed on the first interlayer dielectric layer 114.

[0090] Optionally, substrate 111 can be a rigid substrate or a flexible substrate. The light-shielding layer includes a light-shielding portion 121 and a first electrode plate CO1. The light-shielding layer can be a stacked structure of a molybdenum alloy and copper. The buffer layer 112 can be a single layer or a stacked structure, and the material of the buffer layer 112 is one of silicon oxide, silicon nitride, and silicon oxynitride. The active layer includes a second electrode plate CO2 and an active portion 122. The material of the active layer can be a metal oxide material containing indium, gallium, or zinc. The first insulating layer includes a first insulating portion 113 and a second insulating portion 123. The first insulating layer can be a single layer or a stacked structure. The material of the first insulating layer can be silicon oxide. The first metal layer includes a third electrode plate CO3 and a gate 124, and the first metal layer can be a stacked structure of a molybdenum alloy and copper. The material of the first interlayer dielectric layer 114 can be silicon oxide.

[0091] Optionally, a first photoresist layer pr1 is formed using a first halftone mask H1. The first photoresist layer pr1 includes a first stepped aperture p1, a second stepped aperture p2, and a first cutout aperture p3. The cutout area of ​​the first stepped aperture p1 corresponds to the source region of the active part 122, one cutout area of ​​the second stepped aperture p2 corresponds to the drain region of the active part 122, and the other cutout area of ​​the second stepped aperture p2 corresponds to the light-shielding part 121. The first cutout aperture p3 corresponds to the third electrode plate c03. Then, proceed to step B02.

[0092] Please refer to Figure 4 In step B02, while ashing the first photoresist layer pr1, the first interlayer dielectric layer 114 is etched to form a first contact hole k1, a second contact hole k2, and a first via tk1. One first contact hole k1 exposes the source region of the active portion 122, and the other first contact hole exposes the drain region of the active portion 122. The second contact hole k2 exposes the light-shielding portion 121. The first via tk1 exposes the middle portion 031 of the third electrode plate c03. Then proceed to step B03.

[0093] Please refer to Figure 5 In step B03, using the remaining first photoresist layer pr1 as a mask, the first interlayer dielectric layer 114 is etched to form the first groove 11c, the second groove 11d, and the first opening 11a, and the first photoresist layer pr1 is removed. Then proceed to step B04.

[0094] Please refer to Figure 6 In step B04, a first electrode 125 and a second electrode 126 are formed on the first interlayer dielectric layer 114. The first electrode 125 and the second electrode 126 may be a stacked structure of molybdenum alloy and copper.

[0095] Then proceed to step B05.

[0096] Please refer to Figure 7 In step B05, a second interlayer dielectric layer 115 and a patterned second photoresist layer pr2 are formed on the first interlayer dielectric layer 114.

[0097] Optionally, a second photoresist layer pr2 is formed using a second halftone mask H2. The second photoresist layer pr2 includes a third stepped aperture p4 and a second cutout aperture p5. The cutout area of ​​the third stepped aperture p4 corresponds to the second electrode 126, and the second cutout aperture p5 corresponds to the third electrode plate c03. Then proceed to step B06.

[0098] Please refer to Figure 8 In step B06, while ashing the second photoresist layer pr2, the second interlayer dielectric layer 115 is etched to form the third contact hole k3 and the second via tk2. The third contact hole k3 exposes the second electrode 126. The second via tk2 exposes the middle portion 031 of the third electrode c03. Then proceed to step B03.

[0099] Please refer to Figure 9 In step B07, using the remaining second photoresist layer pr2 as a mask, the second interlayer dielectric layer 115 is etched to form the third groove 11f and the second opening 11b, and the second photoresist layer pr2 is removed. Then proceed to step B08.

[0100] Please refer to Figure 10In step B08, a trace 127 is formed on the second interlayer dielectric layer 115. The trace 127 located in pixel region xs is disposed within the third recess 11f. The trace 127 can be a stacked structure of molybdenum alloy and copper. Then proceed to step B09.

[0101] Please refer to Figure 11 In step B09, a passivation layer 117 and a planarization layer 116 are formed on the second interlayer dielectric layer 115. The passivation layer 117 covers the second interlayer dielectric layer 115, the trace 127, and the recessed structure a1 formed by the first aperture 11a and the second aperture 11b. The planarization layer 116 covers the passivation layer 117 and fills the recessed structure a1.

[0102] Accordingly, please refer to Figure 12 This application also provides a display device 1000, which includes a display panel 100 as described in any of the above embodiments.

[0103] The display device 1000 of this application embodiment includes a capacitor structure c1 with a pixel region xs. The capacitor structure c1 includes a first electrode c01, a second electrode c02, and a third electrode c03 stacked sequentially. A buffer layer 112 is disposed between the first electrode c01 and the second electrode c02. A first insulating portion 113 is disposed between the second electrode c02 and the third electrode c03. A first interlayer dielectric layer 114 covers the capacitor structure c1. A second interlayer dielectric layer 115 is stacked with the first interlayer dielectric layer 114 to form a stacked structure, and the stacked structure forms a recessed structure a1. In the thickness direction of the display panel 100, the recessed structure a1 overlaps with the third electrode c03. A planarization layer 116 covers the second interlayer dielectric layer 115 and fills the recessed structure a1.

[0104] It should be noted that, compared to adding an additional metal layer above the first interlayer dielectric layer to form a capacitor plate, this embodiment uses a metal film layer below the first interlayer dielectric layer 114 to form the third plate c03, which reduces the distance between the third plate c03 and the second plate c02, thereby increasing the capacitance of the capacitor structure c1. Secondly, a recessed structure a1 is provided in the region of the stacked structure corresponding to the capacitor structure c1 to reduce the terrain height of the capacitor structure c1, thereby reducing the height difference between the terrain of the capacitor structure c1 region and the terrain of other regions, so as to improve the flatness of the pixel region xs.

[0105] Display device 1000 can be applied to and used in a variety of products, including, for example, televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs).

[0106] Furthermore, the display device 1000 according to some embodiments can be applied to wearable devices and can be used within wearable devices, including smartwatches, watch phones, glasses-type displays, and head-mounted displays. Additionally, according to some embodiments, the display device 1000 can be applied to instrument panels for automobiles, displays in central dashboards or central information displays arranged on instrument panels, interior mirror displays replacing side mirrors in automobiles, and displays for entertainment systems arranged on the back of the front seats for rear-seat passengers in automobiles.

[0107] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel comprising a plurality of pixel areas, characterized in that, include: substrate; A capacitor structure is disposed on the substrate and located in the pixel region; the capacitor structure includes a first electrode plate, a second electrode plate, and a third electrode plate stacked sequentially. A buffer layer covers the first electrode plate and the substrate, and the second electrode plate is disposed on the side of the buffer layer away from the substrate; A first insulating portion covers the side of the second electrode plate away from the substrate, and a third electrode plate is disposed on the side of the first insulating portion away from the substrate; A first interlayer dielectric layer covers the capacitor structure and the buffer layer; The second interlayer dielectric layer covers the first interlayer dielectric layer. The second interlayer dielectric layer and the first interlayer dielectric layer are stacked to form a stacked structure. The stacked structure forms a recessed structure. In the thickness direction of the display panel, the recessed structure overlaps with the third electrode plate. as well as A planar layer covers the second interlayer dielectric layer and fills the recessed structure.

2. The display panel according to claim 1, characterized in that, The recessed structure includes a first opening and a second opening that are interconnected in the thickness direction of the display panel. The first opening penetrates the first interlayer dielectric layer and exposes the third electrode plate. The second opening penetrates the second interlayer dielectric layer. The width of the second opening is greater than the width of the first opening.

3. The display panel according to claim 2, characterized in that, The first opening includes a first lower opening and a first upper opening. The first upper opening is connected to the side of the first lower opening near the second opening. The third electrode plate includes a middle portion and side portions connected to both sides of the middle portion. Both the first lower hole and the first upper hole expose the middle portion of the third electrode plate. The width of the first upper hole is greater than the width of the first lower hole, and the side portion of the third electrode plate is located within the area of ​​the first upper hole.

4. The display panel according to claim 3, characterized in that, The second opening includes a second lower opening and a second upper opening. The second upper opening is connected to the side of the second lower opening away from the first opening, and the sidewall of the second lower opening is coplanar with the sidewall of the first upper opening. Both the second lower hole and the second upper hole expose the middle portion of the third electrode plate. The width of the second upper hole is greater than the width of the second lower hole. The side portion of the third electrode plate is located within the area of ​​the second upper hole and the second lower hole.

5. The display panel according to any one of claims 1-4, characterized in that, The thickness of the first insulating portion is between 1 / 4 and 1 / 3 of the thickness of the first interlayer dielectric layer.

6. The display panel according to any one of claims 1-4, characterized in that, The display panel further includes a thin-film transistor and a light-shielding portion located in the pixel region. The thin-film transistor includes an active portion, a second insulating portion, a gate, a first electrode, and a second electrode. The light-shielding portion is disposed on the substrate in the same layer as the first electrode. The buffer layer covers the light-shielding portion. The active portion and the second electrode are disposed in the same layer on the side of the buffer layer away from the substrate. The second insulating portion is disposed on the side of the active portion away from the substrate. The gate is disposed on the side of the second insulating portion away from the substrate. The first interlayer dielectric layer covers the gate. The first interlayer dielectric layer has a first contact hole and a second contact hole. The first contact hole penetrates the first interlayer dielectric layer, and the second contact hole penetrates the first interlayer dielectric layer and the buffer layer. The first electrode is connected to one side of the active part through one of the first contact holes, and the second electrode is connected to the other side of the active part through another first contact hole. The second electrode is also connected to the light-shielding part through the second contact hole. The first interlayer dielectric layer is further provided with a first groove and a second groove. The first groove is connected to the first contact hole, and the second groove is connected to the first contact hole and the second contact hole. The first electrode is disposed in the first groove, and the second electrode is disposed in the second groove.

7. The display panel according to claim 6, characterized in that, The depth of the first groove is greater than or equal to the thickness of the first electrode, and the depth of the second groove is greater than or equal to the thickness of the second electrode.

8. The display panel according to claim 7, characterized in that, The thickness of the first interlayer dielectric layer is between 4,000 angstroms and 6,000 angstroms, and the depth of the first groove and / or the depth of the second groove is between 2,000 angstroms and 3,000 angstroms.

9. The display panel according to claim 6, characterized in that, The distance from the side of the third electrode away from the substrate to the upper surface of the substrate is less than the distance from the side of the first electrode away from the substrate to the upper surface of the substrate.

10. The display panel according to claim 9, characterized in that, The vertical distance from the side of the third electrode away from the substrate to the side of the first electrode away from the substrate is between 700 angstroms and 1200 angstroms.

11. The display panel according to claim 6, characterized in that, The second interlayer dielectric layer covers the first electrode, the second electrode, and the first interlayer dielectric layer, and the second interlayer dielectric layer has a third contact hole that exposes the second electrode; the display panel includes a passivation layer and traces, and the traces are connected to the second electrode through the third contact hole; The second interlayer dielectric layer is further provided with a third groove that connects to the third contact hole, and the trace is disposed in the third groove; The passivation layer covers the second interlayer dielectric layer, the trace, and the recessed structure, and the planarization layer covers the passivation layer.

12. The display panel according to claim 11, characterized in that, The thickness of the second interlayer dielectric layer is between 2000 angstroms and 3000 angstroms, and the depth of the third groove is between 1000 angstroms and 1500 angstroms.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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