Display substrate and display device

Abstract

The utility model provides a display substrate and a display device. The display substrate comprises a substrate, a first insulating layer, a conductive layer, a second insulating layer and a first wiring layer, wherein the first insulating layer, the conductive layer, the second insulating layer and the first wiring layer are arranged on one side of the substrate. A groove located in the bending area is formed in the side, away from the substrate, of the first insulating layer. The second insulating layer is provided with an opening in the bending area. The first wiring layer comprises a plurality of first wires, main body sections of the first wires are located in the bending area, lap joint sections of the first wires extend to the fan-out area from the bending area and are erected on the second insulating layer on the top of the first insulating layer, and an insulating protection layer is arranged between the first wiring layer and the side face of the groove.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] To achieve a full-screen effect, a bending area is typically incorporated into the display area of ​​flexible display products. This bending area bends the bonding area used for connecting circuitry towards the backlight side of the display substrate. The bending area is covered with a protective adhesive, such as MCL (MicroCoating Layer), to protect it. However, a thick protective adhesive layer hinders the reduction of the display product's thickness and makes it difficult to narrow the bottom bezel. Therefore, the width of the bottom bezel can be reduced by thinning or omitting the protective adhesive layer in the bending area. Utility Model Content

[0003] This disclosure provides a display substrate and a display device through some embodiments, which helps to improve the reliability of the wiring in the bending area of ​​the display substrate.

[0004] In a first aspect, some embodiments of this disclosure provide a display substrate, including a display area and a fan-out area and a bending area located on one side of the display area. The display substrate includes: a substrate; a first insulating layer disposed on one side of the substrate, covering the display area and the fan-out area, wherein a groove is provided on the side of the first insulating layer away from the substrate, located in the bending area; a second insulating layer disposed on the side of the first insulating layer away from the substrate, the second insulating layer being an organic material layer, covering the display area and the fan-out area, and having an opening in the bending area, the opening at least partially overlapping the orthographic projection of the bottom surface of the groove on the substrate; a conductive layer disposed between the first insulating layer and the second insulating layer; a first wiring layer disposed on the side of the second insulating layer away from the substrate, the first wiring layer including a plurality of first wirings spaced apart, each first wiring including a main body segment and an overlapping segment connected to each other, the main body segment being located in the bending area and disposed on the bottom surface of the groove exposed from the opening, the overlapping segment extending from the bending area to the fan-out area and overlapping the second insulating layer on top of the first insulating layer, and an insulating protective layer being disposed between the first wiring layer and the side of the groove.

[0005] In some embodiments, the distance between the bottom edge of the side surface of the groove and the central axis of the groove is less than the distance between the top edge of the side surface of the groove and the central axis. The central axis of the groove is an axis passing through the geometric center point of the bottom surface of the groove and perpendicular to the substrate. The bottom edge of the side surface is the end of the side surface closer to the substrate, and the top edge of the side surface is the end of the side surface farther from the substrate. The insulating protective layer covers the edge region of the bottom surface of the groove near the side surface of the groove, the corner region between the side surface of the groove and the bottom surface of the groove, and at least a portion of the side surface of the groove.

[0006] In some embodiments, the sides and bottom of the groove form a stepped structure, the stepped structure including a first tread, a first slope, a second slope, and a second tread connecting the first slope and the second slope. The first tread is the bottom surface of the groove, and the bottom end of the first slope is connected to the first tread. The insulating protective layer covers the edge region of the first tread near the first slope, the corner region between the first tread and the first slope, and the corner region between the second tread and the second slope.

[0007] In some embodiments, the stepped structure further includes a third slope and a third tread connecting the second slope and the third slope, wherein the second slope is closer to the substrate than the third slope. The insulating protective layer also covers the first slope, the second tread, the second slope, the third tread, the third slope, and the corner region between the third tread and the third slope.

[0008] In some embodiments, the display substrate further includes a driving circuit layer disposed on one side of the substrate and located in the display area. The driving circuit layer includes: a first source / drain metal layer; a first planarization layer disposed on the side of the first source / drain metal layer away from the substrate; a second source / drain metal layer disposed on the side of the first planarization layer away from the substrate; a first insulating layer including an inorganic insulating layer between the first source / drain metal layer and the substrate; a conductive layer disposed in the same layer as the first source / drain metal layer; a second insulating layer including the first planarization layer; an opening disposed in the first planarization layer; and a first trace layer disposed in the same layer as the second source / drain metal layer.

[0009] In some embodiments, the orthographic projection of the lower port of the opening onto the substrate lies within the orthographic projection range of the bottom surface of the groove onto the substrate, and the lower port is an opening region on a surface close to the substrate. The first planarization layer includes a flat portion and a ramp portion connected to the flat portion, the flat portion covering the display area and the fan-out area, and the ramp portion covering the side of the groove. The insulating protective layer includes the ramp portion, and the overlap section of the first trace overlaps on the ramp portion and extends to the top of the flat portion.

[0010] In some embodiments, the orthographic projection of the ramp portion on the substrate is a first projection area, and the orthographic projection of the side of the groove on the substrate is a second projection area, wherein the second projection area is located within the first projection area.

[0011] In some embodiments, the distance between the first boundary line of the first projection area and the second boundary line of the second projection area is 8 to 15 micrometers, wherein the first boundary line is the boundary line of the first projection area near the bending area, and the second boundary line is the boundary line of the second projection area near the bending area.

[0012] In some embodiments, the surface of the climbing portion facing the bending area includes a first slope and a second slope connected to the first slope, the bottom end of the first slope is connected to the bottom surface of the groove, and the slope angle of the first slope is greater than that of the second slope.

[0013] In some embodiments, the surface of the climbing portion facing the bending area includes a first slope, a second slope, and a connecting surface connecting the first slope and the second slope. The bottom end of the first slope is connected to the bottom surface of the groove. The slope angle of the connecting surface is smaller than that of the first slope and the slope angle of the first slope. The slope angle of the second slope is greater than or equal to that of the first slope.

[0014] In some embodiments, the orthographic projection of the bottom surface of the groove onto the substrate is located within the orthographic projection range of the lower port of the opening onto the substrate. The display substrate further includes a cover layer located in the bending region, disposed on the side of the first wiring layer near the substrate, covering at least a portion of the bottom surface of the groove and the side surface of the groove, and the insulating protective layer includes the cover layer located between the side surface of the groove and the first wiring layer.

[0015] In some embodiments, the first planarization layer covers a portion of the sidewall of the groove near the top, the overlay layer covers a portion of the sidewall of the groove near the bottom, and the insulating protective layer includes the overlay layer and the first planarization layer located between the sidewall of the groove and the first trace layer.

[0016] In some embodiments, the sides and bottom of the groove form a stepped structure, the stepped structure including a first tread, a first slope, a second slope, and a second tread connecting the first slope and the second slope. The first tread is the bottom surface of the groove, and the bottom end of the first slope is connected to the first tread. The covering layer covers the corner area between the first tread and the first slope, the first slope, the second tread, and the corner area between the second tread and the second slope.

[0017] In some embodiments, the cover layer is an inorganic insulating material layer, and the thickness of the cover layer in the direction perpendicular to the substrate is less than 3000 angstroms.

[0018] In some embodiments, the driving circuit layer further includes: a passivation layer disposed between the first source / drain metal layer and the first planarization layer, covering the first source / drain metal layer, wherein the cover layer and the passivation layer are disposed in the same layer.

[0019] In some embodiments, the display substrate further includes a bonding region, and the fan-out region includes a first fan-out region and a second fan-out region. The first fan-out region is located between the bending region and the display region, the second fan-out region is located on the side of the bending region away from the display region, and the bonding region is located on the side of the second fan-out region away from the display region. The display substrate further includes: a second wiring layer located in the first fan-out region, including a plurality of second wirings; a third wiring layer located in the second fan-out region, including a plurality of third wirings; the bonding region is provided with a plurality of bonding pads, the third wirings are electrically connected to the bonding pads, the overlap portion of the first wiring near the first fan-out region is electrically connected to the second wirings through vias, and the overlap portion of the first wiring near the second fan-out region is electrically connected to the third wirings through vias.

[0020] In some embodiments, the first insulating layer includes a plurality of stacked inorganic layers, and the depth of the groove along a direction perpendicular to the substrate is greater than or equal to the sum of the thicknesses of the plurality of inorganic layers.

[0021] In some embodiments, the display substrate further includes a pixel defining layer and a plurality of light-emitting devices. The pixel defining layer is disposed on the side of the second insulating layer away from the substrate. The pixel defining layer has a plurality of pixel openings spaced apart. The pixel openings are located in the display area, and the light-emitting devices are disposed at the pixel openings.

[0022] Secondly, some embodiments of this disclosure provide a display device, including the display substrate provided in the first aspect of this disclosure.

[0023] In some embodiments of the display substrate provided in this disclosure, by providing an opening in the bending region of the second insulating layer, the main body segment of the first trace in the bending region is disposed on the film layer exposed at the opening of the second insulating layer. This helps to reduce the strain of the first trace when it is bent in the bending region, even when the protective adhesive in the bending region is thinned or not provided in the bending region, thereby reducing the risk of breakage of the first trace in the bending region. Furthermore, a groove in the bending region is provided on the side of the first insulating layer away from the substrate. By providing an insulating protective layer between the first trace layer and the side of the groove, even if conductive layer material remains at the side step of the groove, the first trace is insulated from the residual conductive layer material, reducing the risk of short circuit due to contact between the first trace and the residual conductive layer material, thus improving the reliability of the traces in the bending region of the display substrate.

[0024] The above description is merely an overview of the technical solutions provided by the embodiments of this disclosure. In order to better understand the technical means of the embodiments of this disclosure and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and effects of the embodiments of this disclosure more obvious and understandable, specific implementation methods of the embodiments of this disclosure are described below. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0026] Figure 1 A plan view of a display substrate according to some embodiments of the present disclosure is shown;

[0027] Figure 2 It shows Figure 1 A schematic diagram of region A in the diagram;

[0028] Figure 3A It shows Figure 2 An exemplary cross-sectional view along section line AA in the middle;

[0029] Figure 3B It shows Figure 3A A schematic diagram of the groove structure;

[0030] Figure 4 It shows Figure 2 Cross-sectional view along section line BB;

[0031] Figure 5 It shows Figure 2 Another exemplary cross-sectional view along section line AA;

[0032] Figure 6 It shows Figure 2 Another exemplary cross-sectional view along section line AA;

[0033] Figure 7 A schematic diagram of the structure of a display device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0034] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0035] It should be noted that the use of "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The term "at least one" includes one or more cases, and "multiple" includes two or more cases. Words such as "including" or "contains" mean that the element or object preceding the word covers the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "up," "down," "left," and "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] As used herein, “about” includes the value stated and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0037] As used herein, “parallel,” “perpendicular,” “equal,” and “identical” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°. “Equal” and “identical” include absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0038] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0039] The phrase "the orthographic projection of B lies within the orthographic projection range of A" as described in this article means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0040] In this document, the bottom surface of a groove refers to the surface opposite to the opening of the groove, and the bottom surface of the groove is closer to the substrate than the opening of the groove. The side surface of a groove refers to the surface that connects to the bottom surface of the groove and extends from the bottom surface to the opening of the groove. The "side top" of the side surface refers to the end of the side surface away from the substrate, and the "side bottom" refers to the end of the side surface closer to the substrate.

[0041] The "co-layer configuration of A and B" described in this article refers to the simultaneous formation of A and B through the same patterning process. For example, the formation process may include: first forming at least one film layer using the same film deposition process, and then performing the same patterning process on these at least one film layer to form a layer structure containing a specific pattern. Depending on the specific pattern, the patterning process may include multiple coating, exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights (or thicknesses).

[0042] The “slope angle” described in this article refers to the angle between the slope and the plane parallel to the surface of the substrate.

[0043] With the development of display technology, display products are constantly being updated and iterated, and users' requirements for display products are also getting higher and higher. In addition to high requirements for screen display performance (such as clarity, color gamut, viewing angle, and brightness), higher requirements are also being placed on bezel width. Bezel width is one of the key indicators for measuring the design aesthetics and technical strength of display products, and display products as a whole are developing towards narrow bezels. For example, in the current wave of mobile phone technology development, QHD (Quarter High Definition, 1 / 4 of the full HD screen resolution) displays have advantages such as higher pixel density, better color reproduction, wider viewing angle, and higher screen brightness, and are widely used in major flagship mobile phone fields. QHD combined with ultra-narrow bezels is conducive to improving the user experience.

[0044] To achieve a full-screen effect, a pad-bending area is typically created on the display area side of the flexible display substrate. This bends the bonding area used for connecting circuits towards the backlight side of the display substrate. The pad-bending area is covered with a protective adhesive, such as MCL adhesive, to protect it. For example, the thickness of the protective adhesive can be approximately 90 micrometers.

[0045] To achieve an ultra-narrow bezel, it's necessary to reduce the screen's border size and "slim down" the screen. One way to do this is to thin the protective adhesive in the bending area, such as reducing it to half, one-third, or one-quarter of its usual thickness, or even skipping the protective adhesive in the bending area. However, the inventors of this application have discovered that thinning or omitting the protective adhesive in the bending area alters the neutral layer, increasing the risk of signal trace breakage. Therefore, the inventors propose that, while thinning or omitting the protective adhesive in the bending area, the organic insulating layer (such as a planarization layer) originally located between the signal trace and the substrate can be omitted at the bending area. Instead, the organic insulating layer can be opened at the bending area, placing the signal trace in a lower film layer. This reduces the strain on the signal trace when the bending area is bent, thereby lowering the risk of breakage. For example, by opening the aforementioned organic insulating layer at the bending area, the signal trace in the bending area can be placed in the neutral layer of the bending area to prevent the signal trace from breaking.

[0046] However, further research by the inventors of this application revealed that the risk of short circuits in the signal traces at the bend area increases when the aforementioned organic insulating layer is not provided. The reason for this is that without the organic insulating layer at the bend area, the signal traces directly contact the film layer beneath the organic insulating layer, thereby increasing the risk of short circuits caused by contact between the signal traces and other conductive layer materials remaining in the bend area.

[0047] Taking a display substrate with a driving circuit layer comprising a first source / drain metal layer (SD1), a second source / drain metal layer (SD2), and a planarization layer (PLN1) between the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2), and the signal trace in the bending region being located in the second source / drain metal layer (SD2) as an example. To ensure the signal trace is located in the neutral layer of the bending region or experiences minimal strain, the bending region may not have a PLN1, meaning the PLN1 is open in the bending region. However, in actual fabrication, the bending region will have a step due to the need to etch away the underlying inorganic layer material. During the etching of SD1, residual SD1 material may remain at the edge steps of the bending region. If the bending region does not have a PLN1, the signal trace is prone to contacting the residual SD1 material, thus increasing the risk of a short circuit.

[0048] In view of this, a display substrate according to an embodiment of the present disclosure is proposed. The frame area design scheme adopted therein can reduce the risk of signal trace breakage in the bending area by thinning or eliminating the protective adhesive in the bending area, and reduce the risk of short circuit caused by contact between the signal trace in the bending area and the conductive material (such as the SD1 material mentioned above) remaining in the bending area, which is beneficial to improving the reliability of the bending area trace of the display substrate.

[0049] The display substrate provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0050] This disclosure provides a display substrate in some embodiments, the display substrate including a display area and a fanout area and a pad bending area located on one side of the display area. From the perspective of film layer structure, the display substrate includes a substrate substrate and a first insulating layer, a second insulating layer, a conductive layer and a first wiring layer disposed on the substrate substrate.

[0051] A first insulating layer is disposed on one side of the substrate, covering the display area and the fan-out area. A groove is formed on the side of the first insulating layer away from the substrate, located in the bending area. A second insulating layer is disposed on the side of the first insulating layer away from the substrate. The second insulating layer is an organic material layer, covering the display area and the fan-out area, and has an opening in the bending area. This opening at least partially overlaps with the orthographic projection of the bottom surface of the aforementioned groove onto the substrate. A conductive layer is disposed between the first and second insulating layers. A first wiring layer is disposed on the side of the second insulating layer away from the substrate. The first wiring layer includes a plurality of first wirings spaced apart. Each first wiring includes a main body segment and an overlapping segment connected to each other. The main body segment is located in the bending area and is disposed on the bottom surface of the groove exposed from the aforementioned opening in the second insulating layer. The overlapping segment extends from the bending area to the fan-out area, overlapping the second insulating layer on top of the first insulating layer. An insulating protective layer is disposed between the first wiring layer and the side of the aforementioned groove.

[0052] The display substrate provided in some embodiments of this disclosure provides an opening in the second insulating layer located in the bending region, exposing at least a portion of the bottom surface of the aforementioned groove through the opening. This allows the main body segment of the first trace located in the bending region to be disposed on the bottom surface of the groove exposed through the opening. This is beneficial for reducing the strain of the first trace when it is bent in the bending region, even when the protective adhesive in the bending region is thinned or not provided in the bending region, thereby reducing the risk of the first trace breaking in the bending region.

[0053] Because the first insulating layer has a groove in the bending region on the side away from the substrate, some conductive layer material may remain on the side steps of the groove during etching of the conductive layer material in the bending region. Considering that the second insulating layer, which could originally insulate against the residual conductive layer material, has the aforementioned opening in the bending region, the overlapping section of the first trace extends from the bending region to the fan-out region, requiring it to pass through the side of the groove. If the first trace directly overlaps the side of the groove, it is easy to come into contact with the residual conductive layer material on the side of the groove, thereby increasing the risk of short circuit of the first trace in the bending region. The display substrate provided in some embodiments of this disclosure provides an insulating protective layer between the first trace layer and the side of the groove, which can insulate against the residual conductive layer material on the side steps of the groove. This helps to reduce the risk of short circuit caused by the first trace coming into contact with the residual conductive layer material, thereby improving the reliability of the traces in the bending region of the display substrate.

[0054] In some embodiments, the distance between the bottom edge of the side of the groove and the central axis of the groove is less than the distance between the top edge of the side of the groove and the central axis of the groove. The central axis of the groove is an axis that passes through the geometric center point of the bottom surface of the groove and is perpendicular to the substrate.

[0055] Considering that conductive layer material is prone to remain in the edge region of the groove bottom surface (i.e., the region near the side of the groove bottom surface) and the corner region between the groove bottom surface and the side surface, in some embodiments, the aforementioned insulating protective layer can cover the edge region of the groove bottom surface near the side surface, the corner region between the groove side surface and the groove bottom surface, and at least a portion of the side surface of the groove. This effectively insulates against residual conductive layer material, reducing the risk of short circuits caused by contact between the first trace and residual conductive layer material at these locations. It should be noted that the extent of the aforementioned edge region can be determined based on the residual conductive layer material at that location during actual testing.

[0056] In some embodiments, the stepped structure formed by the side and bottom surfaces of the groove includes at least a first tread, a first slope, a second slope, and a second tread connecting the first slope and the second slope. The first tread is the bottom surface of the groove, the bottom end of the first slope is connected to the first tread, the top end of the first slope is connected to the end of the second tread near the central axis of the groove, and the bottom end of the second slope is connected to the end of the second tread away from the central axis of the groove. Considering that conductive layer material can easily remain in the corner area of ​​the side steps, in some embodiments, the aforementioned insulating protective layer covers the edge area of ​​the first tread near the first slope, i.e., the edge area of ​​the bottom surface of the groove, the corner area between the first tread and the first slope, and the corner area between the second tread and the second slope. In some embodiments, the first slope and the second slope can be sloping surfaces, and the distance between the bottom end of the slope and the central axis of the groove is less than the distance between the top end of the slope and the central axis of the groove; the first tread and the second tread can be substantially parallel to the surface of the substrate.

[0057] In some embodiments, the stepped structure may further include a third slope and a third tread connecting the second slope and the third slope. The second slope is closer to the substrate than the third slope. The top of the second slope is connected to the end of the third tread near the central axis of the groove, and the bottom of the third slope is connected to the end of the third tread away from the central axis of the groove. In some embodiments, the third slope may be a ramp, and the distance between the bottom of the slope and the central axis of the groove is less than the distance between the top of the slope and the central axis of the groove. The third tread may be substantially parallel to the surface of the substrate.

[0058] Research revealed that residual conductive layer material is mainly concentrated in the edge region of the bottom surface of the groove (i.e., the first tread of the stepped structure) (i.e., near the corner between the bottom surface of the groove and the first slope) and the corner region between the second tread and the second slope. Therefore, the aforementioned insulating protective layer covering the edge region of the first tread near the first slope, the corner region between the first tread and the first slope, and the corner region between the second tread and the second slope is beneficial for the residual conductive layer material at the side steps of the insulating groove and the first wiring passing through that location, thereby reducing the risk of short circuits in the first wiring in the bending area.

[0059] In some embodiments, in addition to covering the edge region of the first tread near the first slope, the corner region between the first tread and the first slope, and the corner region between the second tread and the second slope, the insulating protective layer may also cover the first slope, the second tread, the second slope, the third tread, the third slope, and the corner region between the third tread and the third slope; that is, the insulating protective layer covers the entire side step of the groove. This provides more comprehensive protection and further reduces the risk of short circuits caused by contact between the first wiring and the conductive layer material remaining at the side step of the groove.

[0060] In some embodiments, the first insulating layer comprises an inorganic insulating material layer. During actual fabrication, this inorganic insulating material layer at the bending region needs to be etched away to ensure the bending performance of the bending region. Thus, the aforementioned groove is formed at the bending region on the side of the first insulating layer away from the substrate. In some embodiments, the first insulating layer is a multi-layer structure comprising multiple stacked inorganic layers. These inorganic layers do not cover the bending region; that is, the portions of these inorganic layers located at the bending region need to be etched away during fabrication, thereby forming the aforementioned groove together with the exposed underlying film layer. The sides of the groove include the sides of these inorganic layers facing the bending region. Along a direction perpendicular to the substrate, the depth of the groove can be greater than or equal to the thickness of the multiple inorganic layers. For example, the depth of the groove can be approximately equal to the sum of the thicknesses of the multiple inorganic layers.

[0061] For example, when the first insulating layer comprises multiple stacked inorganic layers, the portion of the first insulating layer located in the bending region can be etched using a two-stage etching process. Alternatively, the portion of the first insulating layer located in the bending region can be etched using a single, triple, or more etching processes.

[0062] When the portion of the first insulating layer located in the bending region is etched using a two-step etching process, the first etching process can be called edge bending step A+ILD etch (EBI), and the second etching process can be called edge bending step B (EBB). The aforementioned groove may include a first sub-groove and a second sub-groove. The first sub-groove is located on the substrate side of the second sub-groove and communicates with the second sub-groove in a direction perpendicular to the substrate. The orthographic projection of the opening of the first sub-groove onto the substrate is within the orthographic projection range of the opening of the second sub-groove onto the substrate. The second sub-groove can be formed by the aforementioned EBI process, and the first sub-groove can be formed by the aforementioned EBB process. The side surface of the first sub-groove may include the aforementioned first slope, and the side surface of the second sub-groove may include the aforementioned second slope, a third step, and a third slope.

[0063] In some embodiments, the display substrate includes a driving circuit layer disposed on one side of a substrate. The driving circuit layer is located in the display area and configured to form a pixel driving circuit. In some embodiments, the driving circuit layer includes a first source / drain metal layer, a first planarization layer, and a second source / drain metal layer. The first planarization layer is disposed on the side of the first source / drain metal layer away from the substrate. The second source / drain metal layer is disposed on the side of the first planarization layer away from the substrate. The first insulating layer may include an inorganic insulating layer between the substrate and the first source / drain metal layer. The conductive layer may be the first source / drain metal layer. The first wiring layer in the bending region may be disposed in the same layer as the second source / drain metal layer. The second insulating layer may include the first planarization layer. The opening of the second insulating layer in the bending region may be disposed in the first planarization layer. For example, when the second insulating layer is the first planarization layer, in actual fabrication, the first planarization layer is not made at the bending region, so that the first planarization layer has an opening in the bending region.

[0064] In some embodiments, in addition to the first source / drain metal layer and the second source / drain metal layer, the display substrate may include a second planarization layer, a third source / drain metal layer, and a third planarization layer. The second planarization layer is disposed on the side of the second source / drain metal layer away from the substrate, the third source / drain metal layer is disposed on the side of the second planarization layer away from the substrate, and the second planarization layer is disposed on the side of the second source / drain metal layer away from the substrate.

[0065] In some embodiments where the driving circuit layer includes three source-drain metal layers, the first trace layer of the bending region can be disposed on the same layer as the second source-drain metal layer, the conductive layer is disposed on the same layer as the first source-drain metal layer, the second insulating layer can be a first planarization layer, and the opening of the second insulating layer in the bending region can be disposed on the first planarization layer. The second planarization layer covers the display area, the fan-out area, and the bending region. In other embodiments, the first trace layer of the bending region can also be disposed on the same layer as the third source-drain metal layer, the conductive layer is disposed on the same layer as the second source-drain metal layer, the first insulating layer can include the first planarization layer, the second insulating layer can include the second planarization layer, the opening of the second insulating layer in the bending region can be disposed on the second planarization layer, and the third planarization layer covers the display area, the fan-out area, and the bending region.

[0066] Figure 1 A plan view of a display substrate according to some embodiments of the present disclosure is shown. Figure 2 It shows Figure 1 A schematic diagram of region A in the diagram. It should be noted that... Figure 1 The display substrate shown is for illustrative purposes only and does not limit the shape and size of the display substrate. The shape and size of the display substrate are determined according to the needs of the actual display product application.

[0067] like Figure 1As shown, the display substrate 10 may include a display area AA and a non-display area NA. For example, the non-display area NA may be located on one side of the display area AA, or it may be located on multiple sides of the display area AA, such as the non-display area NA surrounding the outside of the display area AA.

[0068] In some embodiments, the display area AA may include a plurality of pixel units arranged in an array, the actual arrangement of which can be determined according to the needs of the product. For example, the display area AA is provided with a plurality of pixel units arranged in an array in a first direction and a second direction. The first direction is the pixel row direction, and the second direction is the pixel column direction. The first direction and the second direction intersect, for example, they may be perpendicular to each other. For example, the first direction may be... Figure 1 The X-axis direction, the second direction can be Figure 1 The Y-axis direction in the diagram. For example, multiple pixel units can be arranged in M ​​rows and N columns, where M and N are integers greater than or equal to 2.

[0069] Each pixel unit comprises multiple sub-pixels, and each sub-pixel can display a single color. For example, the aforementioned multiple sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, each a sub-pixel of a different color, such as displaying one of the three primary colors: red, green, and blue. The brightness (grayscale) of the different colored sub-pixels within each pixel unit can be adjusted. Through color combination and superposition, multiple colors can be displayed, thus achieving full-color display.

[0070] Each subpixel may include a light-emitting device and a pixel driving circuit that drives the light-emitting device to emit light. For example, the light-emitting device may be an electroluminescent device such as an OLED or a QLED (Quantum Dot Light Emitting Diode).

[0071] Pixel driving circuits can include multiple electronic components such as transistors and capacitors. For example, a pixel driving circuit can typically include three transistors and one capacitor, forming a 3T1C (i.e., one driving transistor, two switching transistors, and one capacitor). It can also include more than three transistors and at least one capacitor, such as a 4T1C (i.e., one driving transistor, three switching transistors, and one capacitor), a 5T1C (i.e., one driving transistor, four switching transistors, and one capacitor), or a 7T1C (i.e., one driving transistor, six switching transistors, and one capacitor). The transistors can be thin-film transistors (TFTs), metal oxide semiconductors (MOS), or other switching devices with similar characteristics.

[0072] It is understandable that a transistor can include a control electrode, a first electrode, and a second electrode. The control electrode is the gate of the transistor, the first electrode is one of the source and drain electrodes, and the second electrode is the other of the source and drain electrodes. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. Therefore, the source of a transistor is called either the first electrode or the second electrode.

[0073] In some embodiments, each pixel unit may include a first color subpixel, a second color subpixel, and a third color subpixel. The first color subpixel emits light of a first color, the second color subpixel emits light of a second color, and the third color subpixel emits light of a third color.

[0074] In some embodiments, a light-emitting device of a first color can emit light of the first color, a light-emitting device of a second color can emit light of the second color, and a light-emitting device of a third color can emit light of the third color. In other embodiments, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel can also use white light-emitting devices, and through color filter layer filtering, achieve the following: the first color sub-pixel emits light of the first color, the second color sub-pixel emits light of the second color, and the third color sub-pixel emits light of the third color. For example, the first color, the second color, and the third color can each be one of the three primary colors (i.e., red, green, and blue).

[0075] like Figure 2 As shown, the non-display area NA may include a fan-out area and a bend area BEND located on one side of the display area AA. In some embodiments, the fan-out area may include a first fan-out area FOUT1 and a second fan-out area FOUT2. The first fan-out area FOUT1 is located between the bend area BEND and the display area, and the second fan-out area FOUT2 is located on the side of the bend area BEND away from the display area. The display substrate 10 also includes a second wiring layer and a third wiring layer. The first wiring layer 140 is located in the first fan-out area FOUT1 and includes a plurality of second wirings. The third wiring layer is located in the second fan-out area FOUT2 and includes a plurality of third wirings. The overlap portion of the first wiring 141 near the first fan-out area FOUT1 is electrically connected to the second wirings through vias, and the overlap portion of the first wiring 141 near the second fan-out area FOUT2 is electrically connected to the third wirings through vias.

[0076] In some embodiments, the non-display area NA may further include a bonding area located on the side of the bending area BEND away from the display area AA. During the fabrication of the display module, by bending the bending area BEND, the bonding area can be bent to the non-display side of the display substrate 10, thereby utilizing the space on the non-display side of the display substrate 10 and reducing the overall size of the display substrate 10. Figure 2As shown, the bonding area can be located, for example, on the side of the first fan-out area FOUT1 away from the display area. The bonding area has multiple bonding pads, and the aforementioned third trace is electrically connected to the corresponding bonding pad. For example, the multiple bonding pads include data pads for receiving display data signals. The data signal lines connected to each sub-pixel in the display area AA can be connected to the corresponding data pads via the second trace of the first fan-out area FOUT1, the first trace 141 of the bend area BEND, and the third trace of the second fan-out area FOUT2.

[0077] In some embodiments, the bonding area may include a first sub-bonding area BOND1 and a second sub-bonding area BOND2. In some embodiments, the bonding pads of the first sub-bonding area BOND1 can be used to bond a display driver integrated circuit (DDIC). Of course, in other embodiments, other methods can be used to package the display driver chip onto the display substrate 10, depending on the needs of the actual product, and this disclosure does not impose any limitations on this. The bonding pads of the second sub-bonding area BOND2 are used to bond a flexible circuit board, which is used to transmit external signals to the display driver chip.

[0078] In some embodiments, the non-display area NA may further include an electrostatic discharge (ESD) area located on one side of the display area AA. For example... Figure 2 As shown, the electrostatic discharge (ESD) zone can be set between the second fan-out zone FOUT2 and the first sub-binding zone BOND1.

[0079] Figure 3A It shows Figure 2 An exemplary cross-sectional view along section line AA in the middle. Figure 3B It shows Figure 3A A schematic diagram of the structure of the groove 111 in the middle. Figure 4 It shows Figure 2 Cross-sectional view along section line BB.

[0080] like Figure 3A As shown, the display substrate 10 includes a substrate 100 and a first insulating layer 110, a conductive layer 120, a second insulating layer 130, and a first wiring layer 140 disposed on one side of the substrate 100. It should be noted that the conductive layer 120 refers to a conductive film layer located below the first wiring layer 140 (closer to the substrate 100) and adjacent to the first wiring layer 140. That is, in actual fabrication, the conductive layer 120 is fabricated before the first wiring layer 140, and no other conductive film layer is formed between the conductive layer 120 and the first wiring layer 140.

[0081] In some embodiments, the display substrate 10 is a flexible display substrate, and the substrate 100 includes at least one flexible substrate. For example... Figure 3A As shown, the substrate 100 may include a first flexible substrate layer 101, a second flexible substrate layer 103, and a first barrier layer 102 stacked between the first flexible substrate layer 101 and the second flexible substrate. The material of the flexible substrate layer may include, for example, a PI (Polyimide) substrate, a PET (Polyethylene Terephthalate) substrate, or a PEN (Polyethylene Naphthalate Dicarbonate) substrate.

[0082] like Figure 3A As shown, a groove 111 located in the bending region BEND is provided on the side of the first insulating layer 110 away from the substrate 100. For example, the groove 111 can be formed by the substrate 100 and the sidewall of the first insulating layer 110 facing the bending region BEND. A second insulating layer 130 is provided on the side of the first insulating layer 110 away from the substrate 100, covering the display area and the fan-out area, and is provided with an opening 131 located in the bending region BEND. A conductive layer 120 is located between the first insulating layer 110 and the second insulating layer 130. A first wiring layer 140 is provided on the side of the second insulating layer 130 away from the substrate 100. The first wiring layer 140 includes a plurality of first wirings 141 spaced apart. Figure 3A Only one of the first traces 141 is shown in the diagram. The first trace 141 includes a main body segment 1411 and an overlapping segment 1412 connected to each other. The main body segment 1411 is located in the bend area BEND and is disposed on the bottom surface of the groove 111 exposed from the opening 131 of the second insulating layer 130. The overlapping segment 1412 extends from the bend area BEND across the side 1112 of the groove 111 to the fan-out area, overlapping the second insulating layer 130 on top of the first insulating layer 110. An insulating protective layer is provided between the first trace layer 140 and the side 1112 of the groove 111, which serves to insulate the residual conductive layer 120 material at the step of the side 1112 of the groove 111 and the first trace 141, thereby reducing the risk of short circuit of the first trace 141 due to the residual conductive layer 120 material.

[0083] like Figure 4As shown, the display substrate 10 may include a driving circuit layer disposed on one side of the substrate 100, located in the display area. The driving circuit layer is configured to form a pixel driving circuit for a sub-pixel, and may include transistors and capacitors, as well as multiple signal lines. For example, the multiple signal lines may include power signal lines, data signal lines, reset signal lines, scan signal lines (also called gate lines), enable signal lines, and initialization signal lines, etc., as detailed in related technologies, which will not be elaborated here. The pixel driving circuit may be an LTPO (Low Temperature PolyCrystalline Oxide) pixel driving circuit, or an LTPS (Low Temperature Poly-Silicon) pixel driving circuit, depending on the needs of the actual product, and this disclosure does not impose any limitations on this. Figure 4 The following is an example of using an LTPO pixel driving circuit.

[0084] In some embodiments, the driving circuit layer may include a first active layer 241, a first gate dielectric layer 242, a first gate metal layer 243, a second gate dielectric layer 244, a second gate metal layer 245, a first interlayer insulating layer 246, a second buffer layer 247, a second active layer 248, a third gate dielectric layer 249, a third gate metal layer 251, a second interlayer insulating layer 252, a first source / drain metal layer 253, a passivation layer 254, a first planarization layer 255, a second source / drain metal layer 256, a second planarization layer 257, a third source / drain metal layer 258, and a third planarization layer 259. For example, the material of the first active layer 241 includes low-temperature polysilicon to form a low-temperature polysilicon transistor. The material of the second active layer 248 includes a metal oxide such as IGZO (Indium Gallium Zinc Oxide) to form an oxide transistor. The first gate metal layer 243 (Gate1), the second gate metal layer 245 (Gate2), and the third gate metal layer 251 (Gate3) can be configured to form the gate of each transistor of the pixel driving circuit, form a capacitor, and form a scan signal line; the first source-drain metal layer 253 (SD1) can be configured to form a data signal line and the source and drain of each transistor; the second source-drain metal layer 256 (SD2) can be configured to form a power signal line; and the third source-drain metal layer 258 (SD3) can be configured to form an anode connection portion of the light-emitting device, through which the pixel driving circuit can be electrically connected to the anode of the light-emitting device.

[0085] It should be noted that, Figure 4The functional layers of the driving circuit layer shown are for illustrative purposes only. In other embodiments, the driving circuit layer may include more or fewer functional layers. For example, it may not include the third source / drain metal layer 258 (SD3) and the third planarization layer 259. The specific configuration depends on the actual product requirements, and this embodiment does not impose any restrictions on this.

[0086] like Figure 4 As shown, the display substrate 10 may further include a second barrier layer 210, a bottom shield metal (BSM) 220, and a first buffer layer 230 disposed between the substrate 100 and the driving circuit layer. For example, the second barrier layer 210 may include a first sub-barrier layer 211 and a second sub-barrier layer 212, the bottom shield metal (BSM) 220 may be disposed between the first sub-barrier layer 211 and the second sub-barrier layer 212, and the first buffer layer 230 may be disposed between the second sub-barrier layer 212 and the first active layer 241. In some embodiments, the orthographic projection of the bottom shield metal (BSM) 220 onto the substrate 100 may cover the orthographic projection of the driving transistor in the pixel driving circuit onto the substrate 100, which is beneficial for shielding the influence of static electricity on the driving transistor and reducing the influence of external light incident from one side of the substrate 100 on the active layer of the driving transistor.

[0087] When the conductive layer 120 and the first source / drain metal layer 253 are disposed on the same layer, the first insulating layer 110 may include an inorganic insulating layer located between the substrate 100 and the first source / drain metal layer 253. Figure 4 Taking the display substrate 10 shown as an example, the first insulating layer 110 may include a second barrier layer 210, a first buffer layer 230, a first gate dielectric layer 242, a second gate dielectric layer 244, a first interlayer insulating layer 246, a second buffer layer 247, a third gate dielectric layer 249, and a second interlayer insulating layer 252. Correspondingly, the side surface 1112 of the groove 111 may include the side surface of the second barrier layer 210, the first buffer layer 230, the first gate dielectric layer 242, the second gate dielectric layer 244, the first interlayer insulating layer 246, the second buffer layer 247, the third gate dielectric layer 249, and the second interlayer insulating layer 252 facing the bending region BEND. The depth of the groove 111 may be approximately equal to the sum of the thicknesses of the second barrier layer 210, the first buffer layer 230, the first gate dielectric layer 242, the second gate dielectric layer 244, the first interlayer insulating layer 246, the second buffer layer 247, the third gate dielectric layer 249, and the second interlayer insulating layer 252.

[0088] like Figure 3A and Figure 3BAs shown, a stepped structure is formed between the side surface 1112 and the bottom surface 1111 of the groove 111. The stepped structure includes a first tread T1, a first slope P1, a second tread T2, a second slope P2, a third tread T3, and a third slope P3 connected in sequence.

[0089] In some embodiments, the first step surface T1 can be the bottom surface 1111 of the groove 111, for example, it can be a portion of the surface of the substrate 100 near the second barrier layer 210; the first slope surface P1 can be the side of the second barrier layer 210 facing the bending region BEND; the second step surface T2 can be a portion of the surface of the second barrier layer 210 away from the substrate 100, and the second slope surface P2 can include the side of the first buffer layer 230, the first gate dielectric layer 242, the second gate dielectric layer 244 and the first interlayer insulating layer 246 facing the bending region BEND; the third step surface T3 can be a portion of the surface of the first interlayer insulating layer 246 away from the substrate 100; the third slope surface P3 can include the side of the second buffer layer 247, the third gate dielectric layer 249 and the second interlayer insulating layer 252 facing the bending region BEND.

[0090] by Figure 3A In the example where the second insulating layer 130 is a first planarization layer 255, and the first wiring layer 140 and the second source / drain metal layer 256 are configured in the same layer, the position of the first planarization layer 255 at the edge of the opening 131 of the bending region BEND can be controlled so that the first planarization layer 255 can cover the side step 1112 of the groove 111. This portion of the first planarization layer 255 covering the side step 1112 of the groove 111 can then serve as the aforementioned insulating protective layer, insulating the material of the first source / drain metal layer 253 remaining at the side step 1112 of the groove 111. For example, in... Figure 3A When the second insulating layer 130 is the first planarization layer 255, and the first routing layer 140 and the second source / drain metal layer 256 are disposed on the same layer,... Figure 3A The membrane layer 150 can be a second planarization layer 257, which covers the bending region BEND.

[0091] As shown in 4A, the orthographic projection of the lower port of the opening 131 in the bending region BEND of the first planarization layer 255 onto the substrate 100 is located within the orthographic projection range of the bottom surface 1111 of the groove 111 onto the substrate 100. Since the first planarization layer 255 has a certain thickness, due to process limitations, the area of ​​the opening 131 region on the surface closer to the substrate 100 may differ from the area of ​​the opening 131 region on the surface farther from the substrate 100. For ease of distinction, this paper uses the upper port and lower port to differentiate the opening 131 regions on these two surfaces; the lower port is the opening 131 region on the surface closer to the substrate 100.

[0092] like Figure 3A As shown, the first planarization layer 255 includes a planar portion PL1 and a ramp portion PL2 connected to the planar portion PL1. The planar portion PL1 covers the display area and the fan-out area. The ramp portion PL2 covers the side surface 1112 of the groove 111. One end of the ramp portion PL2 near the substrate 100 contacts the bottom surface 1111 of the groove 111. That is, the ramp portion PL2 covers the entire side surface of the groove 111 and the corner area between the bottom surface 1111 and the side surface, so as to achieve a better insulation effect. The above-mentioned insulating protective layer includes the ramp portion PL2. For example, the ramp portion PL2 can be used as the above-mentioned insulating protective layer. The overlap section 1412 of the first trace 141 is laid on the ramp portion PL2 and extends to the top of the planar portion PL1. In other words, the main body segment 1411 of the first wiring 141 is set on the bottom surface 1111 of the groove 111 to reduce the strain of the main body segment 1411 when the bending area BEND is in a bent state, so as to reduce the risk of the main body breaking. The overlapping segment 1412 of the first wiring 141 is electrically connected to the main body segment 1411 at the corner between the bottom surface of the groove 111 and the climbing part PL2. Starting from the corner between the bottom surface of the groove 111 and the climbing part PL2, it extends along the surface of the climbing part PL2 toward the bending area BEND toward the fan-out area, and extends to the top of the flat part PL1, where it is electrically connected to the wiring in the fan-out area.

[0093] When the traces in the fan-out area (such as the second and third traces mentioned above) are disposed on the same layer as the first gate metal layer 243, or on the same layer as the second gate metal layer 245, or partially on the same layer as the first gate metal layer 243 and partially on the same layer as the second gate metal layer 245, the overlap section 1412 of the first trace 141 can be electrically connected to the traces in the fan-out area through a via. For example, the fan-out area can also be provided with a transition section disposed on the same layer as the first source / drain metal layer 253. The overlap section 1412 can be electrically connected to the transition section through a first via penetrating the first planarization layer 255, and the transition section can then be electrically connected to the traces in the fan-out area through a via.

[0094] In some embodiments, the orthographic projection of the ramp portion PL2 onto the substrate 100 is a first projection area, and the orthographic projection of the side surface 1112 of the groove 111 onto the substrate 100 is a second projection area, with the second projection area located within the first projection area. That is, the ramp portion PL2 covers the entire side surface of the groove 111.

[0095] While ensuring that the ramp portion PL2 covers the side step 1112 of the groove 111, in order to minimize the strain of the first trace 141 when it is bent in the bending region BEND, the opening 131 of the first planarization layer 255 in the bending region BEND should be as large as possible. Therefore, the lower edge of the surface of the ramp portion PL2 facing the bending region BEND and the lower edge of the side of the groove 111 can be adjacent to each other. Here, the lower edge refers to the edge closer to the substrate 100. The lower edge of the side of the groove 111 is the edge of the side of the groove 111 that connects with the bottom surface of the groove 111.

[0096] The coverage distance of the ramp PL2 over the bottom of the side 1112 of the groove 111 can be determined based on the distance between the material of the first source drain metal layer 253 remaining in the edge area of ​​the actual bottom surface of the groove 111 and the bottom of the side 1112 of the groove 111, so that the ramp PL2 can cover this part of the remaining first source drain metal layer 253 material. Figure 3A In this context, d1 represents the coverage distance of the ramp portion PL2 over the side of the groove 111, which is the distance between the lower edge of the surface of the ramp portion PL2 facing the bending area BEND and the lower edge of the side of the groove 111. In some embodiments, d can be 8 to 15 micrometers, for example, 8 micrometers, 10 micrometers, 13 micrometers, or 15 micrometers. In this way, even if there is residual material of the first source / drain metal layer 253 at the step of the side 1112 of the groove 111, it will be covered by the ramp portion PL2 of the first flat layer 255, and will not short-circuit with the first trace 141.

[0097] The boundary line of the first projection area near the bending area BEND is called the first boundary line, and the boundary line of the second projection area near the bending area BEND is called the second boundary line. The first boundary line and the second boundary line are adjacent to each other. The covering distance d of the climbing part PL2 to the bottom end of the side 1112 of the groove 111 is the distance between the first boundary line of the first projection area and the second boundary line of the second projection area.

[0098] The surface morphology of the ramp portion PL2 facing the bending region BEND can be determined according to the actual film structure and process conditions of the product. At least a portion of the surface of the ramp portion PL2 facing the bending region BEND is inclined relative to a direction perpendicular to the substrate 100. For example... Figure 3AAs shown, the surface of the climbing section PL2 facing the bending area BEND may include a first ramp surface M1 and a second ramp surface M2 connected to the first ramp surface M1. The bottom end of the first ramp surface M1 is in contact with the bottom surface 1111 of the groove 111. The slope angle of the first ramp surface M1 can be greater than the slope angle of the second ramp surface M2. This is beneficial for maximizing the area of ​​the lower port of the opening 131 of the first flat layer 255 in the bending area BEND while covering the side steps 1112 of the groove 111, thus ensuring the bending performance of the bending area BEND.

[0099] For example, when preparing the first planarization layer 255, an organic material layer for preparing the first planarization layer 255 is first coated on the entire surface; a transparent resin material can be used. Because the aforementioned groove 111 exists at the bending region BEND, there will be a step difference between the organic material layer formed at the bending region BEND and the organic material layers formed at the fan-out area and the display area; that is, a slope is formed at the position corresponding to the side of the groove 111. Then, the organic material layer at the bending region BEND is removed, forming the first planarization layer 255 with an opening 131 at the bending region BEND. For example, an etching process is used to remove the organic material layer at the bending region BEND. The aforementioned first slope surface M1 is the slope formed by etching the opening 131 of the bending region BEND, and the aforementioned second slope surface M2 is the slope formed due to the aforementioned step difference. The slope angle of the etched slope can be greater than the slope angle of the slope formed due to the aforementioned step difference.

[0100] In some embodiments, during the fabrication of the first planarization layer 255, an iline ultraviolet (IUV) bleaching instrument can be turned on during the MASK process of the first planarization layer 255. This can reduce the slope angle of the ramp portion PL2 on the side of the covered groove 111, thereby reducing the step difference at this location and reducing the risk of residual material in the second source / drain metal layer 256. This reduces the risk of short circuit in the first trace 141 due to residual material in the second source / drain metal layer 256.

[0101] Figure 5 It shows Figure 2 Another exemplary cross-sectional view along section line AA. (See also...) Figure 5As shown, the surface of the ramp portion PL2 facing the bending region BEND may include a first ramp surface M1', a second ramp surface M2', and a connecting surface M3 connecting the first ramp surface M1' and the second ramp surface M2'. The bottom end of the first ramp surface M1' is in contact with the bottom surface 1111 of the groove 111. The slope angle of the connecting surface M3 is smaller than that of the first ramp surface M1' and the first ramp surface M1'. For example, the connecting surface M3 may be approximately parallel to the surface of the substrate 100. In some embodiments, the slope angle of the second ramp surface M2' may be greater than or equal to that of the first ramp surface M1', sufficient to cover the side surface 1112 of the groove 111. By providing a step on the surface of the ramp portion PL2 facing the bending region BEND, the step difference formed in the bending region BEND due to the opening 131 of the first flat layer 255 in the bending region BEND can be reduced, thereby helping to reduce the risk of material residue in the second source / drain metal layer 256 during the fabrication of the first wiring layer 140.

[0102] For example, during the fabrication of the first planarization layer 255, when removing the organic material layer of the bending region BEND using an etching process, a halftone mask can be used above a portion of the side area near the opening 131 of the groove 111. This halftone mask can etch away a portion of the organic material layer covering this side area, forming a step on the surface of the ramp portion PL2 facing the bending region BEND, reducing the slope there, and thus minimizing the step difference formed in the bending region BEND due to the first planarization layer 255 at the opening 131 of the bending region BEND. For example, if the first insulating layer 110 comprises multiple stacked inorganic layers, the halftone mask can be used above the side 1112 of the second sub-groove 111 formed by the EBI process.

[0103] Figure 6 It shows Figure 2 Another exemplary cross-sectional view along section line AA. For example... Figure 6As shown, the area of ​​the opening 131 in the bending region BEND of the first planarization layer 255 can also be larger than the area of ​​the bottom surface of the groove 111, that is, the entire bottom surface of the groove 111 is exposed from the opening 131. In other words, the orthographic projection of the bottom surface 1111 of the groove 111 onto the substrate 100 is located within the orthographic projection range of the lower port of the opening 131 onto the substrate 100. The display substrate 10 also includes a cover layer 200 located in the bending region BEND, disposed on the side of the first wiring layer 140 near the substrate 100, covering at least a portion of the bottom surface 1111 of the groove 111 and the side surface 1112 of the groove 111. In this case, the aforementioned insulating protective layer includes the cover layer 200 located between the side surface 1112 of the groove 111 and the first wiring layer 140. It should be noted that the capping layer 200 is prepared after the conductive layer 120 (such as the first source / drain metal layer 253), thereby covering at least a portion of the bottom surface 1111 and the side surface 1112 of the groove 111, and serving to insulate the conductive layer 120 material remaining at the step of the side surface 1112 of the groove 111.

[0104] In some embodiments, the first planarization layer 255 may cover a portion of the side surface of the groove 111 near the top, and the cover layer 200 may cover a portion of the side surface of the groove 111 near the bottom. The aforementioned insulating protective layer includes the cover layer 200 and the first planarization layer 255 located between the side surface 1112 of the groove 111 and the first wiring layer 140. The cover layer 200 and the first planarization layer 255 may be connected to the side surface 1112 of the groove 111 to cover the entire side step of the groove 111; alternatively, the cover layer 200 and the first planarization layer 255 may not be connected to the side surface 1112 of the groove 111, i.e., there may be a gap between them.

[0105] In some embodiments, the side surface 1112 and bottom surface 1111 of the groove 111 are configured as follows: Figure 6 In the case of the step structure shown, the cover layer 200 can cover the corner area between the first tread T1 and the first slope P1, the first slope P1, the second tread T2, and the corner area between the second tread T2 and the second slope P2 of the step structure. In this way, the cover layer 200 can cover the conductive layer 120 material that may remain on the side 1112 step of the groove 111, thereby reducing the risk of short circuit caused by the residue of the conductive layer 120 material.

[0106] In some embodiments, the capping layer 200 may be an inorganic insulating material layer, for example, the material of the capping layer 200 may include silicon oxide. When the capping layer 200 is an inorganic insulating material layer, the thickness of the capping layer 200 in the direction perpendicular to the substrate 100 may be less than 3000 angstroms, so as to reduce the influence of the capping layer 200 on the bending characteristics of the bending region BEND.

[0107] In some embodiments, when the driving circuit layer includes a passivation layer 254 disposed between the first source / drain metal layer 253 and the first planarization layer 255, the cover layer 200 may be disposed on the same layer as the passivation layer 254. The passivation layer 254 covers the first source / drain metal layer 253, thus protecting the first source / drain metal layer 253. For example, when fabricating the passivation layer 254, a portion of the passivation layer 254 in the bending region BEND may be left unetched as the cover layer 200. Considering that over-etching usually occurs when etching the first planarization layer 255 in the bending region BEND, the thickness of the passivation layer 254 may be 3000 angstroms. After removing a certain thickness of the passivation layer 254 due to over-etching of the first planarization layer 255, the thickness of the remaining passivation layer 254, i.e., the cover layer 200, can be less than 3000 angstroms.

[0108] In some embodiments, the display substrate 10 further includes a pixel defining layer 260 and a plurality of light-emitting devices 270. The pixel defining layer 260 is disposed on the side of the second insulating layer 130 away from the substrate 100. The pixel defining layer 260 has a plurality of pixel openings 261 spaced apart in the display area. The light-emitting devices 270 are disposed at the pixel openings 261, and the pixel openings 261 are configured to define the light-emitting area of ​​the light-emitting device 270. For example, one light-emitting device 270 may be disposed at one pixel opening 261.

[0109] In some embodiments, the pixel defining layer 260 may be disposed on the side of the driving circuit layer away from the substrate 100, for example... Figure 4 The pixel defining layer 260 is disposed on the side of the third planarization layer 259 away from the substrate 100. For example, the pixel defining layer 260 may cover the bending region BEND. Figure 3A The film layer 160 in the middle can be the pixel defining layer 260.

[0110] For example, taking an OLED device as an example, along the direction away from the substrate 100, the light-emitting device 270 may include an anode layer 271, a light-emitting layer 272, and a cathode layer 273 stacked sequentially. The anode layer 271 is disposed between the pixel defining layer 260 and the driving circuit layer, and the anode layers 271 of two adjacent light-emitting devices 270 are spaced apart and insulated from each other. The anode layer 271 is electrically connected to the pixel driving circuit, and at least a portion of the anode layer 271 is exposed at the pixel opening 261. For example, the orthographic projection of the lower port of the pixel opening 261 (i.e., the opening 131 on the surface near the substrate 100) onto the substrate 100 is within the orthographic projection range of the anode layer 271 onto the substrate 100.

[0111] The light-emitting layer 272 is disposed on the side of the anode away from the substrate 100. For example, at least a portion of the light-emitting layer 272 is located within the pixel opening 261 of the corresponding sub-pixel, forming an electrical connection with the anode layer 271 of the corresponding light-emitting device 270. In some embodiments, the light-emitting layer 272 may include a light-emitting material layer (EML) and a functional material layer stacked on top of the light-emitting material layer. For example, the functional material layer may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), specifically configured according to actual needs, and this disclosure does not limit this.

[0112] A cathode layer 273 is stacked and disposed on the side of the light-emitting layer 272 away from the substrate 100. In some embodiments, the cathode layers 273 of adjacent light-emitting devices 270 can be interconnected, such as... Figure 4 The cathode layers 273 of each light-emitting device 270 are arranged as shown to facilitate access to the cathode voltage signal of each light-emitting device 270. In other embodiments, the cathode layers 273 of each light-emitting device 270 may also be spaced apart from each other and electrically connected to each other through additional conductive structures such as metal isolation pillars.

[0113] In some embodiments, the anode layer 271 can be a composite structure formed by sequentially stacking a transparent conductive oxide film, a metal film, and another transparent conductive oxide film. The transparent conductive oxide film is made of, for example, any one of ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), and the metal film is made of, for example, any one or more of aluminum (Al), silver (Ag), titanium (Ti), and molybdenum (Mo). In other embodiments, the anode layer 271 can also be a single-layer structure, such as a single-layer structure made of any one of aluminum (Al), silver (Ag), titanium (Ti), and molybdenum (Mo).

[0114] In some embodiments, the cathode layer 273 can be any one of the following metals: lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag), or an alloy of any combination of these materials, such as a magnesium-silver alloy or an aluminum-lithium alloy. In some embodiments, the anode layer 271 can serve as a reflective electrode, and the cathode layer 273 is configured to partially transmit and partially reflect the light emitted by the light-emitting layer 272. By utilizing the microcavity effect, the light-emitting device 270 achieves a better color gamut and luminous efficiency.

[0115] by Figure 4Taking the fabrication process of the shown display substrate 10 as an example, a first flexible substrate layer 101, a first barrier layer 102, and a second flexible substrate layer 103 are formed sequentially first; then a first sub-barrier layer 211 is formed on the second flexible substrate layer 103, a metal material layer is formed on the first sub-barrier layer 211, and the metal material layer is patterned and etched to form a shielding layer 220, followed by the formation of a second sub-barrier layer 212; on the second sub-barrier layer 212, a first buffer layer 230, a first active layer 241, a first gate dielectric layer 242, a first gate metal layer 243, a second gate dielectric layer 244, a second gate metal layer 245, a first interlayer insulating layer 246, a second buffer layer 247, a second active layer 248, a third gate dielectric layer 249, a third gate metal layer 251, and a second interlayer insulating layer 252 are formed sequentially. For example, the first buffer layer 230 and the second interlayer insulating layer 252 can be multilayer structures, such as a stacked structure of silicon oxide and silicon nitride layers. Next, vias for the driving circuit layer are fabricated, and the inorganic insulating layer covering the substrate 100 where the bending region (BEND) is etched away is formed. Then, a first source / drain metal layer 253, a passivation layer 254, a first planarization layer 255, a second source / drain metal layer 256, a second planarization layer 257 (PLN2), a third source / drain metal layer 258, a third planarization layer 259, an anode layer 271, and a pixel defining layer 260 are formed. The above fabrication process can utilize a total of 17 masks.

[0116] It should be noted that, in addition to the above-mentioned film layer structure, the display substrate 10 may also include other film layer structures, which can be set according to the needs of the actual product.

[0117] In some embodiments, the display substrate 10 may further include a PS layer (Photo Spacer). Figure 4 (not shown in the image), the PS layer can be set on top of the pixel delimiting layer 260, that is, in the area between adjacent pixel openings 261.

[0118] In some embodiments, the display substrate 10 may further include an encapsulation layer 280. The encapsulation layer 280 covers the plurality of light-emitting devices 270 to protect the light-emitting devices 270 from water and oxygen corrosion. For example, the encapsulation layer 280 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked together. For example, the first and second inorganic encapsulation layers may be made of inorganic insulating materials such as nitrides, oxides, nitrogen oxides, nitrates, carbides, or any combination thereof. The organic encapsulation layer may be made of organic insulating materials such as acrylic fibers, hexamethyldisiloxane, polyacrylates, polycarbonates, or polystyrene.

[0119] In some embodiments, the display substrate 10 may further include a touch structure layer 290 disposed on the side of the encapsulation layer away from the substrate 100 to facilitate touch functionality. For example, the touch structure layer 290 may be fabricated using FMLOC (Flexible Multi Layer On Cell) technology, as detailed in related technologies. For example, the touch structure layer 290 may include a first touch metal layer, a second touch metal layer, and a touch insulating layer disposed between the first touch metal layer and the second touch metal layer. The orthographic projections of the first touch metal layer and the second touch metal layer on the substrate 100 do not overlap with the orthographic projections of the pixel opening 261 on the substrate 100. One of the first touch metal layer and the second touch metal layer is configured to provide a first touch electrode and a second touch electrode, while the other is configured to provide a bridging portion bridging the first touch electrode or the second touch electrode. The extending directions of the first touch electrode and the second touch electrode intersect each other, for example, they may be perpendicular to each other. Taking a first touch metal layer with bridging electrodes and a second touch metal layer with first and second touch electrodes as an example, the second touch electrode includes multiple electrode units. Two adjacent electrode units are disconnected at the position that crosses the first touch electrode, and a via is provided in the touch insulating layer, which is then bridged by the bridging electrodes provided in the first touch metal layer.

[0120] In some embodiments, the display substrate 10 may further include a color filter layer and a light-shielding layer (not shown in the figure), disposed on the side of the encapsulation layer away from the substrate 100. The light-shielding layer may include a plurality of light-transmitting openings spaced apart, and the color filter layer may include a plurality of color filters. Each color filter is disposed at one light-transmitting opening. For example, the plurality of color filters may include a red filter, a green filter, and a blue filter. A red filter is disposed corresponding to a red subpixel, a green filter is disposed corresponding to a green subpixel, and a blue filter is disposed corresponding to a blue subpixel. In some embodiments, the light-shielding layer may be formed of a black light-shielding material, also known as a black matrix, or BM for short.

[0121] In some embodiments, the display substrate 10 may further include a protective layer 300 (also referred to as TOC) disposed on the side of the pixel defining layer 260 away from the substrate 100. For example, when the display substrate 10 includes a touch structure layer 290, the protective layer 300 may be disposed on the side of the touch structure layer 290 away from the substrate 100 to protect the display substrate 10 from water and oxygen corrosion in the air. For example, the protective layer 300 may cover the display area, the fan-out area, and the bending area (BEND), depending on the needs of the actual product. Figure 3A , Figure 5 and Figure 6 The membrane layer 170 in the middle can be a protective layer TOC.

[0122] The display substrate 10 provided in some embodiments of this disclosure can reduce the risk of short circuits caused by residual conductive layer 120 material (such as the first source / drain metal layer 253 material described above) and / or first wiring layer 140 material (such as the second source / drain metal layer 256 material described above) without adding a mask.

[0123] Figure 7 A schematic diagram of a display device according to some embodiments of the present disclosure is shown. For example... Figure 7 As shown, the display device 1000 provided in some embodiments of this disclosure includes the display substrate 10 provided in any of the embodiments described above. Therefore, the display device 1000 has technical effects corresponding to the beneficial technical effects of the aforementioned display substrate 10.

[0124] For example, the display device 1000 can be any electronic product or component with display function, such as a mobile phone, laptop computer, tablet computer, wearable display device (such as a smartwatch or smart glasses), television, digital photo frame, etc.

[0125] The above description does not provide detailed technical specifications regarding the layout of each layer of the product. However, those skilled in the art should understand that layers and regions of the desired shape can be formed using various technical means. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0126] It should be noted that the accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with conventional designs. Where there is no conflict, the embodiments of this disclosure and the features described therein can be combined with each other to obtain new embodiments.

[0127] Although some embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area and a fan-out area and a bending area located on one side of the display area. Substrate; A first insulating layer is disposed on one side of the substrate, covering the display area and the fan-out area. A groove located in the bending area is provided on the side of the first insulating layer away from the substrate. A second insulating layer is disposed on the side of the first insulating layer away from the substrate. The second insulating layer is an organic material layer that covers the display area and the fan-out area. An opening is provided in the bending area, and the opening at least partially overlaps with the orthographic projection of the bottom surface of the groove on the substrate. A conductive layer is disposed between the first insulating layer and the second insulating layer; A first wiring layer is disposed on the side of the second insulating layer away from the substrate. The first wiring layer includes a plurality of first wirings spaced apart. Each first wiring includes a main body segment and an overlapping segment connected to each other. The main body segment is located in the bending area and is disposed on the bottom surface of the groove exposed from the opening. The overlapping segment extends from the bending area to the fan-out area and overlaps the second insulating layer on top of the first insulating layer. An insulating protective layer is disposed between the first wiring layer and the side of the groove.

2. The display substrate according to claim 1, characterized in that, The distance between the bottom end of the side of the groove and the central axis of the groove is less than the distance between the top end of the side of the groove and the central axis. The central axis of the groove is an axis that passes through the geometric center point of the bottom surface of the groove and is perpendicular to the substrate. The bottom end of the side is the end of the side closer to the substrate, and the top end of the side is the end of the side away from the substrate. The insulating protective layer covers the edge region of the bottom surface of the groove near the side surface of the groove, the corner region between the side surface of the groove and the bottom surface of the groove, and at least a portion of the side surface of the groove.

3. The display substrate according to claim 1, characterized in that, The side and bottom surfaces of the groove form a stepped structure. The stepped structure includes a first tread, a first slope, a second slope, and a second tread connecting the first slope and the second slope. The first tread is the bottom surface of the groove, and the bottom end of the first slope is connected to the first tread. The insulating protective layer covers the edge region of the first tread near the first slope, the corner region between the first tread and the first slope, and the corner region between the second tread and the second slope.

4. The display substrate according to claim 3, characterized in that, The stepped structure further includes a third slope and a third tread connecting the second slope and the third slope, wherein the second slope is closer to the substrate than the third slope. The insulating protective layer also covers the first slope, the second tread, the third tread, the third slope, and the corner area between the third tread and the third slope.

5. The display substrate according to any one of claims 1-4, characterized in that, It also includes a driving circuit layer disposed on one side of the substrate, located in the display area, the driving circuit layer comprising: First source / drain metal layer; A first planarization layer is disposed on the side of the first source / drain metal layer away from the substrate. The second source / drain metal layer is disposed on the side of the first planarization layer away from the substrate. The first insulating layer includes an inorganic insulating layer between the first source / drain metal layer and the substrate, the conductive layer is disposed in the same layer as the first source / drain metal layer, the second insulating layer includes the first planarization layer, the opening is disposed in the first planarization layer, and the first trace layer is disposed in the same layer as the second source / drain metal layer.

6. The display substrate according to claim 5, characterized in that, The orthographic projection of the lower port of the opening onto the substrate is located within the orthographic projection range of the bottom surface of the groove onto the substrate, and the lower port is an opening area on the surface close to the substrate. The first flat layer includes a flat portion and a ramp portion connected to the flat portion, the flat portion covering the display area and the fan-out area, and the ramp portion covering the side of the groove; The insulating protective layer includes the ramp portion, the overlapping section of the first wiring is laid on the ramp portion and extends to the top of the flat portion.

7. The display substrate according to claim 6, characterized in that, The orthographic projection of the ramp portion onto the substrate is a first projection area, and the orthographic projection of the side of the groove onto the substrate is a second projection area, with the second projection area located within the first projection area.

8. The display substrate according to claim 7, characterized in that, The distance between the first boundary line of the first projection area and the second boundary line of the second projection area is 8 to 15 micrometers, wherein the first boundary line is the boundary line of the first projection area near the bending area, and the second boundary line is the boundary line of the second projection area near the bending area.

9. The display substrate according to claim 6, characterized in that, The surface of the climbing section facing the bending area includes a first slope surface and a second slope surface connected to the first slope surface. The bottom end of the first slope surface is connected to the bottom surface of the groove, and the slope angle of the first slope surface is greater than that of the second slope surface.

10. The display substrate according to claim 6, characterized in that, The surface of the climbing section facing the bending area includes a first slope, a second slope, and a connecting surface connecting the first slope and the second slope. The bottom end of the first slope is connected to the bottom surface of the groove. The slope angle of the connecting surface is smaller than that of the first slope and the first slope. The slope angle of the second slope is greater than or equal to that of the first slope.

11. The display substrate according to claim 5, characterized in that, The orthographic projection of the bottom surface of the groove onto the substrate is located within the orthographic projection range of the lower port of the opening onto the substrate. The display substrate further includes a cover layer located in the bending area, disposed on the side of the first wiring layer near the substrate, covering at least a portion of the bottom surface and side surface of the groove, and the insulating protective layer includes the cover layer located between the side surface of the groove and the first wiring layer.

12. The display substrate according to claim 11, characterized in that, The first planarization layer covers a portion of the side of the groove near the top, the cover layer covers a portion of the side of the groove near the bottom, and the insulating protective layer includes the cover layer and the first planarization layer located between the side of the groove and the first trace layer.

13. The display substrate according to claim 11, characterized in that, The side and bottom surfaces of the groove form a stepped structure. The stepped structure includes a first tread, a first slope, a second slope, and a second tread connecting the first slope and the second slope. The first tread is the bottom surface of the groove, and the bottom end of the first slope is connected to the first tread. The covering layer covers the corner area between the first tread and the first slope, the first slope, the second tread, and the corner area between the second tread and the second slope.

14. The display substrate according to claim 11, characterized in that, The cover layer is an inorganic insulating material layer, and the thickness of the cover layer in the direction perpendicular to the substrate is less than 3000 angstroms.

15. The display substrate according to claim 11, characterized in that, The driving circuit layer further includes: A passivation layer is disposed between the first source / drain metal layer and the first planarization layer, covering the first source / drain metal layer, and the cover layer and the passivation layer are disposed in the same layer.

16. The display substrate according to claim 1, characterized in that, It also includes a binding area, and the fan-out area includes a first fan-out area and a second fan-out area. The first fan-out area is located between the bending area and the display area, the second fan-out area is located on the side of the bending area away from the display area, and the binding area is located on the side of the second fan-out area away from the display area. The display substrate further includes: The second routing layer is located in the first fan-out area and includes multiple second routing layers; The third routing layer, located in the second fan-out area, includes multiple third routing layers; The bonding area is provided with multiple bonding pads. The third trace is electrically connected to the bonding pads. The overlap portion of the first trace near the first fan-out area is electrically connected to the second trace through a via. The overlap portion of the first trace near the second fan-out area is electrically connected to the third trace through a via.

17. The display substrate according to claim 1, characterized in that, The first insulating layer comprises a plurality of inorganic layers stacked together, and the depth of the groove along a direction perpendicular to the substrate is greater than or equal to the sum of the thicknesses of the plurality of inorganic layers.

18. The display substrate according to claim 1, characterized in that, Also includes: The system includes a pixel defining layer and multiple light-emitting devices. The pixel defining layer is disposed on the side of the second insulating layer away from the substrate. The pixel defining layer has multiple pixel openings spaced apart. The pixel openings are located in the display area, and the light-emitting devices are disposed at the pixel openings.

19. A display device, characterized in that, include: The display substrate according to any one of claims 1-18.

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