Integrated device
By forming a semiconductor region between the inner sidewalls of the substrate vias and covering the polymer residue with an insulating layer, the problem of polymer residue contamination is solved, resulting in a more efficient etching process and reduced production costs.
Patent Information
- Application Number
- CN202422982289.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-29
- Filing Date
- 2024-12-04
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2034-12-04
AI Technical Summary
In existing technologies, polymer residues contaminate the copper seed tool during substrate via formation, leading to increased production costs and excessively long etching times, which affects production efficiency.
By forming a semiconductor region between the inner sidewalls of the substrate via and covering polymer residues on the first insulating layer, the first and second insulating layers are used as hard masks to reduce the second etching process time and prevent polymer residues from contaminating the seed crystal tool.
It effectively reduces the time of the second etching process, protects the seed crystal tool, avoids contamination by polymer residues, improves production efficiency, and reduces production costs.
Smart Images
Figure CN223798686U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to an integrated device. Background Technology
[0002] Through-vias (Vias) are integrated circuit components used to couple different circuit layers together. Using Via allows for the fabrication of three-dimensional circuitry, thereby reducing the area of a single package. Another advancement in reducing device form factor is through-substrate vias (TSVs). Multiple TSVs extend through the substrate to couple multiple circuit layers formed on different sides of the substrate. The use of TSVs increases the area available for front-end-of-line (FEOL) devices. TSVs further increase the flexibility of multi-chip devices, where integrated circuits can be formed on different chips that are subsequently bonded together. Utility Model Content
[0003] This invention provides an integrated device comprising a substrate having a first side and a second side relative to the first side, the substrate being a first material; a first conductive layer located on the second side of the substrate and having a first conductive line; a second conductive layer located on the first side of the substrate and having a second conductive line; a substrate via extending from the first conductive line through the substrate to the second conductive line; a shallow trench isolation region surrounding the substrate via on the second side of the substrate; and a semiconductor region located between the shallow trench isolation region and the substrate via, the semiconductor region comprising the first material.
[0004] An integrated device according to the present invention includes: a substrate having a first side and a second side opposite to the first side; a substrate via extending from the first side to the second side; a shallow trench isolation region forming a continuous loop around the substrate via on the second side; and a first insulating layer spaced apart from the substrate via, wherein the first insulating layer is separated from the shallow trench isolation region.
[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description
[0006] The figures and the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.
[0007] Figures 1A to 1BCross-sectional and top views are shown of some embodiments of substrate vias having shallow trench isolation (STI) regions that surround and are spaced apart from the substrate vias.
[0008] Figure 2 A cross-sectional view is shown of an additional embodiment of a substrate via having a shallow trench isolation region that surrounds and is spaced apart from the substrate via.
[0009] Figures 3A to 3B A top view is shown of an additional embodiment of a substrate via having a shallow trench isolation region that surrounds and is spaced apart from the substrate via, wherein the semiconductor region between the shallow trench isolation region and the substrate via has various shapes when viewed from the top view.
[0010] Figures 4A to 4B A top view illustrating an additional embodiment of a substrate via having a shallow trench isolation region surrounding and spaced apart from the substrate via, wherein a plurality of substrate vias extend through the shallow trench isolation region.
[0011] Figures 5 to 14 A series of cross-sectional views are shown illustrating some embodiments of a method for forming substrate vias having shallow trench isolation regions that surround and are spaced apart from the substrate vias.
[0012] Figure 15 The flowchart illustrates some embodiments of a method for forming a substrate via having a shallow trench isolation region that surrounds and is spaced apart from the substrate via.
[0013] Explanation of reference numerals in the attached figures
[0014] 100a, 200, 400a, 400b, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400: Sectional View
[0015] 100b, 300a, 300b, 500: Top view
[0016] 102: Substrate
[0017] 102a: First side
[0018] 102b: Second side
[0019] 104: Substrate via
[0020] 106: Shallow trench isolation zone
[0021] 106a: Lateral wall
[0022] 106b: Inner wall
[0023] 108: First Conductor Layer
[0024] 109: First conductor
[0025] 110: Second conductor layer
[0026] 111: Second conductor
[0027] 112: Semiconductor Zone
[0028] 112b: Bottom surface
[0029] 114: Resistance-protected oxide layer
[0030] 116: Contact Etching Stop Layer
[0031] 118: First interlayer dielectric layer
[0032] 120: Second interlayer dielectric layer
[0033] 122: First high dielectric layer
[0034] 124: Passivation layer
[0035] 126: First insulating layer
[0036] 128: Second insulating layer
[0037] 130: Polymer residues
[0038] 202: Semiconductor Devices
[0039] 204: Doped region
[0040] 206: Gate stack
[0041] 208: Contact element
[0042] 210: Opening
[0043] 212a: First Angle
[0044] 212b: Second Angle
[0045] 402: Second substrate via
[0046] 404: Third conductor
[0047] 406: Fourth conductor
[0048] 408: Second Semiconductor Region
[0049] 502: First etching process
[0050] 504: First mask layer
[0051] 504a: Peripheral section
[0052] 504b: Central Part
[0053] 506: First Opening
[0054] 1002: Third Etching Process
[0055] 1004: Third mask layer
[0056] 1006: Third opening
[0057] 1202: Fourth Etching Process
[0058] 1204: Fourth mask layer
[0059] 1206: Fourth opening
[0060] 1402: Additional conductor layer
[0061] 1404: Additional through-hole layer
[0062] 1500: Flowchart
[0063] 1502, 1504, 1506, 1508, 1510, 1512, 1514: Actions
[0064] A-A': section line Detailed Implementation
[0065] This utility model provides numerous different embodiments or examples for implementing various features of the present utility model. Specific examples of components and arrangements are described below to simplify the present utility model. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various embodiments of the present utility model. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.
[0066] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.
[0067] A substrate via is a conductive through-hole extending from a first side of a substrate to a second side. Substrate vias are used to couple multiple devices and interconnect structures on the first side of the substrate to multiple devices and interconnect structures on the second side of the substrate. This connection results in the formation of a larger integrated circuit on the substrate, thereby increasing the possible size and complexity of the integrated circuit on the substrate. In some embodiments, the substrate via is also thermally conductive, allowing heat to be transferred from the semiconductor device to the entire device, thereby reducing the likelihood of thermal damage to the connected devices.
[0068] Before forming substrate vias, various semiconductor devices can be formed on a first and second side of the substrate. The use of silicification processes and the application of stress to the channels of the semiconductor devices can improve their performance, and a resistive protective oxide (RPO) and a contact etch stop layer (CESL) are required on the second side of the substrate. Furthermore, in some cases, one or more layers, including layers containing highly dielectric materials, are present on the first side of the substrate. Some methods for forming substrate vias use multiple etching steps to expose the underlying wiring. In some embodiments, a first etching step etches through the substrate to a shallow trench isolation region. The shallow trench isolation region isolates multiple surrounding devices and multiple doped wells from the substrate via. Then, a second etching step etches through the shallow trench isolation region, the resistive protective oxide, the contact etch stop layer, and the interlayer dielectric to reach the underlying layer. During the first etching, the highly dielectric layer is etched.
[0069] The high dielectric layer may include a polymer, such that the first etching causes polymer residue to accumulate on multiple inner sidewalls of the substrate and one or more passivation layers. If the copper seed tool used to initiate the formation of substrate vias is exposed to the polymer residue, the residue will contaminate the copper seed tool, causing tool damage and increasing production costs. A first insulating layer is formed over the polymer residue to prevent the copper seed tool from being exposed to the polymer residue. A second insulating layer is further formed over the first insulating layer and serves as a hard mask for the second etching step.
[0070] However, because the second etching step involves etching through the shallow trench isolation region, the resistive protective oxide layer, the contact etch stop layer, and the interlayer dielectric layer, it has a sufficiently long process time, causing it to also etch through the first and second insulating layers. Etching through the first and second insulating layers exposes polymer residues that contaminate the copper seed tool. Therefore, a method is needed to reduce the process time of the second etching step without completely removing the aforementioned layers.
[0071] This invention provides a substrate via extending through a semiconductor region between multiple inner sidewalls of a shallow trench isolation region. The shallow trench isolation region is defined with a first opening, at which the substrate via extends through the semiconductor region. The first opening is filled by the semiconductor region and is located between multiple inner sidewalls of the shallow trench isolation region. A first etching creates an opening extending from a first side of the substrate through the semiconductor region to a resistive protective oxide layer on a second side of the substrate. A second etching then etches through a portion of a first insulating layer, the resistive protective oxide layer, a contact etch stop layer, and an interlayer dielectric layer at the bottom of the substrate. Directly removing a portion of the shallow trench isolation region in the second etching path reduces the process time of the second etching, causing the first insulating layer to continue covering polymer residues. The continued covering of polymer residues by the first insulating layer prevents contamination of seed layer tools or other deposition tools.
[0072] Figures 1A to 1B Cross-sectional view 100a and top view 100b illustrate some embodiments of substrate vias having shallow trench isolation regions that surround and are spaced apart from the substrate vias. Figure 1A The cross-sectional view 100a can, for example, be along... Figure 1B The section line A-A' is used to cut out the section.
[0073] like Figure 1AAs shown in cross-sectional view 100a, a substrate via 104 extends through the substrate 102. The substrate via 104 extends from a first side 102a of the substrate 102 to a second side 102b. The substrate via 104 is continuously surrounded by a shallow trench isolation region 106 at the second side 102b of the substrate 102. The substrate via 104 is coupled to a first conductor 109 of a first conductive layer 108 passing through the second side 102b of the substrate and a second conductor 111 of a second conductive layer 110 passing through the first side 102a of the substrate 102. The substrate via 104 is spaced apart from the shallow trench isolation region 106 by a semiconductor region 112 and a first insulating layer 126. The substrate via 104 extends above the top surface of the first insulating layer 126 and below the bottom surface of the first insulating layer 126.
[0074] A resistive protective oxide layer 114 is located on a second side 102b of substrate 102. A contact etch stop layer 116 extends over the resistive protective oxide layer 114. A first interlayer dielectric layer 118 is located on the contact etch stop layer 116 and surrounds the first conductor 109 of the first conductive layer 108. A first high dielectric layer 122 is located on a first side 102a of substrate 102. In some embodiments, the first high dielectric layer 122 is or comprises a high dielectric polymer. A passivation layer 124 is located on the first high dielectric layer 122. A first insulating layer 126 is located on the passivation layer 124 and extends along a plurality of inner sidewalls of substrate 102. A second insulating layer 128 covers the top surface of the first insulating layer 126. A second interlayer dielectric layer 120 covers the second insulating layer 128 and surrounds the second conductor 111 of the second conductive layer 110. In some embodiments, the second insulating layer 128 has a top surface flush with the top surface of the substrate via 104.
[0075] Polymer residue 130 from the first high dielectric layer 122 extends along the passivation layer 124 and multiple inner sidewalls of the substrate 102. If exposed to a seed layer tool used to form the substrate via 104, polymer residue 130 could contaminate the seed layer tool. A first insulating layer 126 covers the polymer residue 130, preventing contamination of the seed layer tool. Semiconductor region 112 is part of substrate 102 and has substantially the same etch rate as substrate 102. The spacing between semiconductor region 112 and shallow trench isolation region 106 causes a second etch not to etch through shallow trench isolation region 106, thereby reducing the process time for the second etch. The lower process time protects the first insulating layer 126 covering the polymer residue 130, preventing contamination of the seed layer tool.
[0076] like Figure 1BAs shown in top view 100b, the shallow trench isolation region 106 forms a continuous loop surrounding the substrate via 104. A semiconductor region 112 continuously surrounds the substrate via 104, separating the substrate via 104 from the shallow trench isolation region 106. A first insulating layer 126 continuously surrounds the substrate via 104, separating the semiconductor region 112 from the substrate via 104.
[0077] Figure 2 Cross-sectional view 200 illustrates an additional embodiment of a substrate via having a shallow trench isolation region surrounding and spaced apart from the substrate via.
[0078] In some embodiments, a semiconductor device 202 is located on a second side 102b of a substrate 102. The semiconductor device 202 has a plurality of doped regions 204 (e.g., a plurality of source / drain regions, etc.) extending into the substrate 102. A shallow trench isolation region 106 extends between the doped regions 204 and a substrate via 104, thereby insulating the plurality of doped regions 204 from the substrate via 104. In some embodiments, the semiconductor device 202 also includes a gate stack 206. The gate stack 206 and the doped regions 204 are coupled to a first conductive layer 108 via a plurality of contacts 208. A resistive protective oxide layer 114 extends upward to a plurality of sidewalls of the gate stack 206 and has a plurality of openings 210 over the plurality of doped regions 204. A silicide layer is located on the surface of the gate stack 206 and over the plurality of doped regions 204 in the plurality of openings 210. A contact etch stop layer 116 is conformal to the surface of the gate stack 206 and a plurality of outer surfaces of the resistive protective oxide layer 114.
[0079] The shallow trench isolation region 106 has an outer sidewall 106a forming a first angle 212a with the second side 102b of the substrate 102. The shallow trench isolation region 106 also has an inner sidewall 106b forming a second angle 212b with the bottom surface 112b of the semiconductor region 112. In some embodiments, both the first angle 212a and the second angle 212b are obtuse angles. The interior angle formed by the outer sidewall 106a and the surface of the shallow trench isolation region 106 flush with the second side 102b of the substrate 102 is an acute angle. The interior angle formed by the inner sidewall 106b and the surface of the shallow trench isolation region 106 flush with the second side 102b of the substrate 102 is an acute angle. In some embodiments, the first angle 212a and the second angle 212b are different.
[0080] Figures 3A to 3B Top views 300a, 300b illustrate additional embodiments of substrate vias having shallow trench isolation regions that surround and are spaced apart from the substrate vias, wherein the semiconductor region between the shallow trench isolation regions and the substrate vias has various shapes when viewed from the top view.
[0081] like Figure 3AAs shown in the top view 300a, when viewed from a top-down angle, the outer walls of the semiconductor region 112 can have a square profile. That is, etching of the shallow trench isolation region 106 can be performed around the square portion of the mask layer, thereby leaving a semiconductor region 112 retaining a square profile between the plurality of inner sidewalls 106b of the shallow trench isolation region 106. Figure 3B As shown in the top view 300b, when viewed from a top-down angle, the outer walls of the semiconductor region 112 can have a hexagonal profile. That is, etching of the shallow trench isolation region 106 can be performed around the hexagonal portion of the mask layer, thereby leaving a semiconductor region 112 retaining a hexagonal profile between the plurality of inner sidewalls 106b of the shallow trench isolation region 106. Figure 3A as well as Figure 3B In the illustrated embodiment, when viewed from a top-down angle, the substrate via 104 and the plurality of outer sidewalls of the first insulating layer 126 have a circular profile. In other embodiments, when viewed from a top-down angle, the substrate via 104 and the plurality of outer sidewalls of the first insulating layer 126 may have a square or hexagonal profile.
[0082] Figures 4A to 4B Cross-sectional and top views of an additional embodiment of a substrate via having a shallow trench isolation region surrounding and spaced apart from the substrate via are illustrated, wherein a plurality of substrate vias extend through the shallow trench isolation region.
[0083] like Figure 4A As shown in cross-sectional view 400a, in some embodiments, in addition to the first substrate via 104, a second substrate via 402 also extends through the shallow trench isolation region 106. The second substrate via 402 extends from the third conductor 404 in the second conductor layer 110 to the fourth conductor 406 in the first conductor layer 108. The second substrate via 402 extends through the second semiconductor region 408. The second semiconductor region 408 is separated from the semiconductor region 112 by the shallow trench isolation region 106. The outer sidewalls of the second semiconductor region 408 may have, for example, […]. Figure 1B , Figure 3A and Figure 3B The outline shown is circular, square, or hexagonal. A first insulating layer 126 extends along a plurality of inner sidewalls of the substrate 102 surrounding the first substrate via 104 and the second substrate via 402, and extends through the top surface of the passivation layer 124 between the first substrate via 104 and the second substrate via 402. Figure 4B As shown in the cross-sectional view 400b, the outer sidewall of the second semiconductor region 408 may have the same profile as the outer sidewall of the semiconductor region 112.
[0084] Figures 5 to 14A series of cross-sectional views illustrating some embodiments of a method for forming substrate vias having shallow trench isolation regions surrounding and spaced apart from the substrate vias are drawn. Although Figures 5 to 14 The description is a series of actions; however, it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the described methods are applicable to other structures. In other embodiments, some actions may be shown and / or described, in whole or in part.
[0085] like Figure 5 As shown in top view 500, a first mask layer 504 is formed on a substrate 102. The substrate 102 can be any suitable type of substrate and / or can be, for example, a semiconductor wafer, one or more dies on a wafer, or any other suitable type of semiconductor body and / or epitaxial layer. In some embodiments, the substrate 102 is or includes silicon, sapphire, or any combination thereof. The first mask layer 504 can be formed, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin-on processes, etc. The first mask layer 504 is then patterned to expose multiple portions of the substrate 102 corresponding to the shallow trench isolation region (see shallow trench isolation region 106 in FIG. 1) to be subsequently formed. In some embodiments, the first mask layer 504 is or includes photoresist and / or is patterned using photolithography. The first mask layer includes a peripheral portion 504a and a central portion 504b. The peripheral portion 504a covers the substrate 102 across the shallow trench isolation region 106 that will be formed later (see...). Figure 1A Multiple portions of the outer sidewalls of the substrate 102. The central portion 504b covers the semiconductor region 112 of the substrate 102.
[0086] After patterning the first mask layer 504, a first etching process 502 is performed on the substrate 102 with the first mask layer 504 in place. The first etching process 502 removes multiple portions of the substrate 102 exposed by the first mask layer 504, thereby etching a first opening 506 in the substrate 102. The first opening 506 continuously surrounds the semiconductor region 112 of the substrate 102. In some embodiments, the first etching process 502 is a dry etching process. The first mask layer 504 is then removed.
[0087] like Figure 6As shown in cross-sectional view 600, a shallow trench isolation region 106 is formed in the first opening 506. In some embodiments, the shallow trench isolation region 106 is or includes an insulating material, such as silicon dioxide, etc. In some embodiments, chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal treatment, or a combination thereof are used to form the shallow trench isolation region 106 to form a conformal insulating layer. A planarization process (e.g., chemical-mechanical planarization, CMP) is then performed to remove multiple portions of the conformal insulating layer above the second side 102b of the substrate 102.
[0088] like Figure 7 As shown in cross-sectional view 700, a resistive protective oxide layer 114, a contact etch stop layer 116, and a second interlayer dielectric layer 120 are formed on the second side 102b of the substrate 102. In some embodiments, the resistive protective oxide layer 114, the contact etch stop layer 116, and the second interlayer dielectric layer 120 are formed using one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. In some embodiments, the resistive protective oxide layer 114 is or includes an insulating material, such as silicon dioxide, silicon oxynitride, silicon nitride, etc. In some embodiments, the contact etch stop layer 116 is or includes an insulating material, such as silicon nitride, etc. In some embodiments, the second interlayer dielectric layer 120 is or includes an insulating material, such as silicon dioxide, silicon oxynitride, silicon nitride, etc.
[0089] like Figure 8 As shown in cross-sectional view 800, a first conductive layer 108 is formed in a first interlayer dielectric layer 118. The first conductive layer 108 includes first conductive lines 109 covering the semiconductor region 112. In some embodiments, the first conductive lines 109 are formed using one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, damascene processes, planarization processes, etc., or a combination thereof. In some embodiments, the first conductive lines 109 are or include conductive materials, such as copper, tungsten, aluminum, titanium nitride, etc.
[0090] like Figure 9 As shown in cross-sectional view 900, a first high dielectric layer 122 and a passivation layer 124 are formed on a first side 102a of a substrate 102. In some embodiments, the first high dielectric layer 122 and the passivation layer 124 are formed using one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. In some embodiments, the first high dielectric layer 122 is or includes a high dielectric material, such as hafnium dioxide, zirconium dioxide, hafnium silicate, zirconium silicate, high dielectric polymer, etc. In some embodiments, the passivation layer 124 is or includes an insulating material, such as silicon dioxide, undoped silicate glass, etc.
[0091] like Figure 10As shown in cross-sectional view 1000, a third mask layer 1004 is formed on the passivation layer 124. The third mask layer 1004 can be formed, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, etc. The third mask layer 1004 is then patterned to expose a portion of the passivation layer 124 directly covering a portion of the semiconductor region 112 between the plurality of inner sidewalls of the shallow trench isolation region 106. In some embodiments, the third mask layer 1004 is or includes photoresist and / or is patterned using photolithography.
[0092] After patterning the third mask layer 1004, a third etching process 1002 is performed on the passivation layer 124, the first high dielectric layer 122, and the substrate 102 having the third mask layer 1004. The third etching process 1002 removes multiple portions of the passivation layer 124, the first high dielectric layer 122, and the substrate 102 exposed by the third mask layer 1004, etching a third opening 1006 in the substrate 102 and penetrating the semiconductor region 112 to expose the resistive protective oxide layer 114. In some embodiments, the third etching process 1002 is a dry etching process. The third mask layer 1004 is then removed.
[0093] like Figure 11 As shown in cross-sectional view 1100, a first insulating layer 126 and a second insulating layer 128 are deposited over the passivation layer 124 and within the third opening 1006. In some embodiments, when the first high-dielectric layer 122 contains a high-dielectric polymer, polymer residue 130 may form on multiple sidewalls of the substrate 102, the first high-dielectric layer 122, and the passivation layer 124 during the third etching process 1002. The polymer residue 130 may contaminate multiple tools used for subsequent etching and atomic layer deposition steps. The first insulating layer 126 covers multiple inner sidewalls of the third opening, thereby sealing the polymer residue 130 between the substrate 102 and the first insulating layer 126. In some embodiments, the second insulating layer 128 is not lined with the multiple inner sidewalls of the first insulating layer 126 due to the deposition process used to form the second insulating layer 128 with poor step coverage. In some embodiments, the first insulating layer 126 is or includes silicon dioxide, etc. In some embodiments, the second insulating layer 128 is or includes silicon nitride, etc. The first insulating layer 126 is made of a different material than the second insulating layer 128.
[0094] like Figure 12As shown in cross-sectional view 1200, a fourth mask layer 1204 is formed on the second insulating layer 128. The fourth mask layer 1204 can be formed, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other similar processes. The fourth mask layer 1204 is then patterned to expose the third opening 1006. In some embodiments, the fourth mask 1204 is or includes photoresist and / or photolithography is used to pattern the fourth mask layer 1204.
[0095] After the fourth mask layer 1204 is formed, a fourth etching process 1202 is performed on the substrate 102. The fourth mask layer 1204 covers multiple top surfaces of the first insulating layer 126 and the second insulating layer 128. The fourth etching process 1202 forms a fourth opening 1206 under the third opening 1006. The etching rate of the material through the second insulating layer 128 in the fourth etching process 1202 is lower than the etching rate of the material through the resistive protective oxide layer 114 and the first interlayer dielectric layer 118 in the fourth etching process 1202. The fourth opening 1206 extends through the resistive protective oxide layer 114, the contact etch stop layer 116, and the first interlayer dielectric layer 118 to reach the first conductor 109 of the first conductor layer 108. The semiconductor region 112 remaining in the substrate 102 surrounding the third opening 1006 causes the fourth etching process 1202 to begin not from the shallow trench isolation region 106, but from the resistive protective oxide layer 114, thereby reducing the process time of the fourth etching process 1202. The shorter process time of the fourth etching process 1202 results in the second insulating layer 128 remaining on the substrate 102 and the first insulating layer 126 remaining above the plurality of inner sidewalls of the third opening 1006, preventing polymer residues 130 from being exposed during etching.
[0096] like Figure 13 As shown in cross-sectional view 1300, at the third opening (see...) Figure 12 The third opening (1006) and the fourth opening (see Figure 12 A substrate via 104 is formed at the fourth opening 1206. In some embodiments, a seed layer is formed along a plurality of inner sidewalls of the second insulating layer 128, the first interlayer dielectric layer 118, and the contact etch stop layer 116 to form the substrate via 104. Polymer residue 130 is separated from the substrate via 104 through the first insulating layer 126 and the second insulating layer 128, protecting the tools used to form the seed layer from contamination by the polymer residue 130. After the seed layer is formed, a third opening (see...) is formed at the third opening 1206. Figure 12 The third opening (1006) and the fourth opening (see Figure 12The fourth opening 1206 is filled with a conformal conductive layer. A planarization process is then performed to remove multiple portions of the conformal conductive layer located above the top surface of the second insulating layer 128, leaving the substrate via 104 in the substrate 102. In some embodiments, the substrate via is or includes a conductive metal, such as copper.
[0097] like Figure 14 As shown in cross-sectional view 1400, a second conductive layer 110 is formed over a second insulating layer 128 and a substrate via 104. The second conductive layer 110 includes a second interlayer dielectric layer 120 and second conductive lines 111 coupled to the substrate via 104. In some embodiments, the second conductive layer 110 may be coupled to a plurality of additional conductive layers 1402 vias covering the second conductive layer 110. In some embodiments, the second conductive lines 111 are formed using one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, damascene processes, planarization processes, or combinations thereof. In some embodiments, the second conductive lines 111 are or comprise conductive materials such as copper, tungsten, aluminum, titanium nitride, etc.
[0098] Figure 15 A flowchart 1500 illustrates some embodiments of a method for forming a substrate via having a shallow trench isolation region surrounding and spaced apart from the substrate via. Although the methods and other methods shown and / or described herein are depicted as a series of actions or events, it should be understood that the invention is not limited to the shown order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.
[0099] At operation 1502, a shallow trench isolation region is formed around a semiconductor region on a substrate having a first side and a second side, the shallow trench isolation region being formed on the second side of the substrate. See, for example, [link to relevant documentation]. Figure 6 .
[0100] At action 1504, a first interlayer dielectric layer is formed over the shallow trench isolation region and the semiconductor region. For example, see... Figure 7 .
[0101] At action 1506, a first conductive line is formed within the first interlayer dielectric layer covering the semiconductor material. See, for example, [link to example]. Figure 8 .
[0102] At action 1508, a second opening is etched from the first side of the substrate to the second side of the substrate. This second opening extends through the semiconductor material and, through the semiconductor material, separates the shallow trench isolation regions. For example, see... Figure 10 .
[0103] At action 1510, a first insulating layer is formed above the substrate and along a plurality of inner sidewalls of the substrate surrounding the second opening. See, for example, [link to example]. Figure 11 .
[0104] At action 1512, a third opening is etched from the first side of the substrate through the second opening to the second side of the substrate. This third opening extends through the first insulating layer and the first interlayer dielectric layer, exposing the first conductive line. See, for example, [link to example]. Figure 12 .
[0105] At action 1514, the second and third openings are filled with a conductive material to form a substrate via coupled to the first wire. See, for example, [link to example]. Figure 13 .
[0106] Some embodiments of the integrated device include a substrate having a first side and a second side relative to the first side, the substrate being a first material; a first conductive layer located on the second side of the substrate and having a first conductive line; a second conductive layer located on the first side of the substrate and having a second conductive line; a substrate via extending from the first conductive line through the substrate to the second conductive line; a shallow trench isolation region surrounding the substrate via on the second side of the substrate; and a semiconductor region located between the shallow trench isolation region and the substrate via, the semiconductor region comprising the first material. In other embodiments, the semiconductor region has circular outer sidewalls when viewed from a top-down angle. In other embodiments, the semiconductor region has rectangular outer sidewalls when viewed from a top-down angle. In other embodiments, the semiconductor region has hexagonal outer sidewalls when viewed from a top-down angle. In other embodiments, the integrated device further includes a first insulating layer extending from the first side to the second side along a plurality of inner sidewalls of the substrate, wherein the substrate via extends above a top surface of the first insulating layer and below a bottom surface of the first insulating layer. In other embodiments, the integrated device further includes a second insulating layer covering the first insulating layer and extending along the outer wall of the substrate via, the second insulating layer including a top surface flush with the top surface of the substrate via. In other embodiments, the shallow trench isolation region has an outer wall facing away from the substrate via and an inner wall facing the substrate via, wherein the outer wall of the shallow trench isolation region has a first obtuse angle formed between the outer wall and the second side of the substrate, wherein the inner wall of the shallow trench isolation region has a second angle formed between the inner wall and the bottom surface of the semiconductor region, and wherein the second angle is obtuse.
[0107] Another embodiment of the integrated device includes: a substrate having a first side and a second side opposite to the first side; a substrate via extending from the first side to the second side; a shallow trench isolation region forming a continuous loop around the substrate via on the second side; and a first insulating layer spaced between the substrate via and the substrate, wherein the first insulating layer is separated from the shallow trench isolation region. In other embodiments, the integrated device further includes: a resistive protective oxide layer located on the second side of the substrate; a contact etch stop layer located on the resistive protective oxide layer; an interlayer dielectric layer located on the contact etch stop layer; and a conductive layer located in the interlayer dielectric layer, including a first conductive line, wherein the substrate via extends through the resistive protective oxide layer, the contact etch stop layer, and the interlayer dielectric layer to reach the first conductive line of the conductive layer. In other embodiments, the integrated device further includes: a first high-dielectric layer located on the first side of the substrate, comprising a first material; and a passivation layer located on the first high-dielectric layer, wherein the first material of the first high-dielectric layer extends over a plurality of inner sidewalls of the substrate and the passivation layer, and wherein a first insulating layer spaces the first material on the plurality of inner sidewalls of the substrate and the passivation layer from the substrate vias. In other embodiments, the integrated device further includes: a second insulating layer covering the first high-dielectric layer, the passivation layer, and the first insulating layer, wherein the material of the second insulating layer is different from the material of the first insulating layer. In other embodiments, the integrated device further includes: a semiconductor device located on the second side of the substrate, the semiconductor device having a plurality of doped regions within the substrate, the plurality of doped regions being spaced from the substrate vias by the shallow trench isolation regions. In other embodiments, the integrated device further includes: a second substrate via extending from the first side to the second side, wherein a shallow trench isolation region forms a second continuous loop around the second substrate via, and wherein the first insulating layer further spaces the second substrate via from the substrate and extends across the first side of the substrate between the substrate via and the second substrate via.
[0108] Please understand that in this written description and the following claims, the terms "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish different elements of a figure or series of figures. In themselves, these terms do not indicate any temporal order or structural proximity of the components and are not intended to describe corresponding components in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.
[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.
Claims
1. An integrated device, characterized in that, include: A substrate, including a first side and a second side relative to the first side, the substrate comprising a first material; A first conductive layer is located on the second side of the substrate and includes a first conductive layer; A second conductive layer is located on the first side of the substrate and includes a second conductive layer; A substrate perforation extends from the first conductor through the substrate to the second conductor; Shallow trench isolation region, substrate vias surrounding the second side of the substrate; as well as A semiconductor region is located between the shallow trench isolation region and the substrate via, and the semiconductor region includes the first material.
2. The integrated device according to claim 1, characterized in that, When viewed from above, the semiconductor region has a circular outer wall.
3. The integrated device according to claim 1, characterized in that, When viewed from a top-down angle, the semiconductor region has a rectangular outer wall.
4. The integrated device according to claim 1, characterized in that, When viewed from a top-down angle, the semiconductor region has hexagonal outer walls.
5. The integrated device according to claim 1, characterized in that, It further includes a first insulating layer extending from the first side to the second side along a plurality of inner sidewalls of the substrate, wherein the substrate perforations extend above the top surface of the first insulating layer and below the bottom surface of the first insulating layer.
6. The integrated device according to claim 1, characterized in that, The shallow trench isolation region has an outer sidewall facing away from the substrate via and an inner sidewall facing the substrate via. The outer sidewall of the shallow trench isolation region has a first obtuse angle formed between the outer sidewall and the second side of the substrate. The inner sidewall of the shallow trench isolation region has a second angle formed between the inner sidewall and the bottom surface of the semiconductor region. The second angle is obtuse.
7. An integrated device, characterized in that, include: The substrate includes a first side and a second side relative to the first side; Substrate perforations extend from the first side to the second side; Shallow trench isolation region, forming a continuous loop around the substrate via on the second side; as well as A first insulating layer separates the substrate via from the substrate, wherein the first insulating layer is separated from the shallow trench isolation region.
8. The integrated device according to claim 7, characterized in that, Including: A resistive protective oxide layer is located on the second side of the substrate; A contact etch stop layer is located on the resistive protective oxide layer; Interlayer dielectric layer, located on the contact etch stop layer; and A conductive layer, located within the interlayer dielectric layer, includes a first conductive line, wherein the substrate via extends through the resistive protective oxide layer, the contact etch stop layer, and the interlayer dielectric layer to reach the first conductive line of the conductive layer.
9. The integrated device according to claim 7, characterized in that, Including: A semiconductor device is located on the second side of the substrate, the semiconductor device having a plurality of doped regions within the substrate, the plurality of doped regions being spaced apart from the substrate vias by the shallow trench isolation region.
10. The integrated device according to claim 7, characterized in that, Including: A second substrate via extends from the first side to the second side, wherein a shallow trench isolation region forms a second continuous loop around the second substrate via, and wherein the first insulating layer further spaces the second substrate via from the substrate and extends across the first side of the substrate between the substrate via and the second substrate via.