Semiconductor power module substrate structure and module

Abstract

The utility model provides a semiconductor power module substrate structure and a module, and relates to the technical field of electronic power. Comprising an upper substrate and a lower substrate; the lower substrate is sequentially divided into a first region, a second region and a third region along a first direction through the grooves; the upper substrate is sequentially divided into a fourth region and a fifth region along the first direction through the groove; at least one chip is arranged in the first area and the third area; each chip is provided with a first conductive block; the first conductive block in the first area is connected with the fourth area; the first conductive block located in the third area is connected with the fifth area; second conductive blocks are also arranged in the first region and the second region on the lower substrate; one side, far away from the lower substrate, of the second conductive block in the first region is connected with the fifth region; and one side, far away from the lower substrate, of the second conductive block in the second region is connected with the fourth region, so that the problems of complicated operation and low production efficiency due to the fact that most of existing substrate structures need to be manually designed according to chips are solved.

Description

Technical Field

[0001] This utility model relates to the field of electronic power technology, and in particular to a semiconductor power module substrate structure and module. Background Technology

[0002] With the rapid development of new energy systems and electric vehicle drive systems, the demand for power density and current carrying capacity of power modules is increasing. Multiple chips are typically packaged together in a power module. However, the high-speed switching of the chips and the parasitic inductance of the power module substrate circuitry can limit chip performance. Therefore, reducing and balancing the parasitic inductance within the power module through substrate design is crucial for improving its performance and safety.

[0003] However, existing substrate designs are often manually designed for specific chips and application scenarios, and substrate designs for different application scenarios are difficult to reuse, resulting in complicated designs and low production efficiency. Utility Model Content

[0004] In order to overcome the above-mentioned technical defects, the purpose of this utility model is to provide a semiconductor power module substrate structure and module, so as to solve the problem that most existing substrate structures need to be manually designed according to the chip, which is cumbersome and has low production efficiency.

[0005] This utility model discloses a semiconductor power module substrate structure.

[0006] Including the upper substrate and the lower substrate;

[0007] The lower substrate is divided into a first region, a second region, and a third region sequentially along a first direction by trenches;

[0008] The upper substrate is divided into a fourth region and a fifth region sequentially along the first direction by trenches;

[0009] At least one chip is provided in the first region and the third region;

[0010] Each of the aforementioned chips is provided with a first conductive block;

[0011] The first conductive block on the chip located in the first region is connected to the fourth region on the side away from the chip.

[0012] The first conductive block on the chip located in the third region is connected to the fifth region on the side away from the chip.

[0013] A second conductive block is further provided on the lower substrate in the first and second regions;

[0014] The second conductive block located in the first region is connected to the fifth region on the side away from the lower substrate.

[0015] The second conductive block located in the second region is connected to the fourth region on the side away from the lower substrate.

[0016] Preferably, the trenches forming the second region are arranged symmetrically along the centerline of the lower substrate perpendicular to the first direction.

[0017] Preferably, the chip located in the first region and the chip located in the third region are arranged symmetrically along the centerline on the lower substrate perpendicular to the first direction.

[0018] Preferably, multiple chips are provided in the first region and / or the third region;

[0019] Each of the chips is arranged along a second direction, wherein the second direction is perpendicular to the first direction.

[0020] Preferably, a metal cladding layer is provided on the lower substrate and / or the upper substrate, and the trench passes through the metal cladding layer to form the first region, the second region, and the third region.

[0021] Preferably, the chip includes an IGBT chip, a MOSFET chip, and / or an FRD chip.

[0022] Preferably, it is also connected with a number of electrical connection elements and electrodes;

[0023] The electrical connection element and the electrode are arranged opposite each other on both sides of the lower substrate.

[0024] Preferably, the electrodes are arranged in three parts, located in the first region, the second region, and the third region, respectively.

[0025] Preferably, the electrical connection element is fixed to the lower substrate by a metal sheet;

[0026] The chip is connected to the corresponding electrical connection element via a connection line.

[0027] This utility model also provides a semiconductor power module.

[0028] The semiconductor power module substrate structure described in any of the above descriptions is applied.

[0029] Compared with existing technologies, the above technical solution has the following advantages:

[0030] This application provides a semiconductor power module substrate structure and module. The lower substrate is divided into three regions, each connected to an electrode. The first and third regions can accommodate different chip arrangements without altering the underlying substrate structure, depending on the output power requirements of the application scenario. Conductive blocks (first conductive block / second conductive block) connect the lower and upper substrates, enabling reuse of the upper and lower substrates. This solves the problem that existing substrate structures often require manual design based on the chip, resulting in cumbersome operations and low production efficiency. Furthermore, the arrangement of each chip along a predetermined direction in each region ensures a relatively symmetrical chip distribution on the substrate, facilitating uniform stress distribution during the molding process and improving the final power module performance. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the semiconductor power module substrate structure and module embodiment described in this utility model;

[0032] Figure 2 This is a schematic diagram illustrating the substrate structure of a semiconductor power module according to the present invention and in a module embodiment.

[0033] Figure 3 This is a schematic diagram illustrating the structure of the upper substrate in a semiconductor power module substrate structure and module embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram illustrating the structure of the semiconductor power module substrate and the corresponding upper and lower substrates in the module embodiment of the present invention.

[0035] Figure label:

[0036] 1-Upper substrate; 11-Fourth region; 12-Fifth region; 2-Lower substrate; 21-First region; 22-Second region; 23-Third region; 3-Chip; 41-First conductive block; 42-Second conductive block; 5-Trench; 6-Metal cladding; 7-Electrical connection element; 8-Electrode; 91-Connecting line; 92-Metal sheet. Detailed Implementation

[0037] The advantages of this utility model are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0039] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0040] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0041] In the description of this utility model, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0042] In the description of this utility model, unless otherwise specified and limited, it should be noted that the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two components. They can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0043] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrating this invention and has no specific meaning in itself. Therefore, "module" and "part" can be used interchangeably.

[0044] Example: This example discloses a semiconductor power module substrate structure. This substrate structure can accommodate various structural variations with different chip areas 3, depending on the output power requirements of the application scenario, without changing the absolute position of the substrate size and signal terminals (such as electrical connection elements 7 / electrodes 8). This allows for the production of semiconductor modules with multiple power levels without changing the production fixture, thereby improving production efficiency and enabling the reuse of the upper substrate 1 and the lower substrate 2 in the substrate structure.

[0045] For details, please refer to Figures 1-4 The substrate structure includes an upper substrate 1 and a lower substrate 2. The upper substrate 1 and the lower substrate 2 mostly contain a ceramic substrate and conductive layers located on both sides of the ceramic substrate. The lower substrate 2 is divided into a first region 21, a second region 22 and a third region 23 in sequence along a first direction by trenches 5. The upper substrate 1 is divided into a fourth region 11 and a fifth region 12 in sequence along the first direction by trenches 5. The conductive layers are separated by trenches 5, and electrical isolation is achieved by the ceramic substrate.

[0046] In this embodiment, optionally, a metal cladding layer is provided on the lower substrate 2 and / or the upper substrate 1, and the trench 5 passes through the metal cladding layer 6 to form the first region 21, the second region 22, and the third region 23. That is, the metal cladding layer can be used as the above-mentioned conductive layer, or the metal cladding layer can be added to improve conductivity, etc. The trench 5 passes through the metal cladding layer 6 to expose the ceramic substrate.

[0047] Furthermore, at least one chip 3 is provided in the first region 21 and the third region 23; each chip 3 is provided with a first conductive block 41; the first conductive block 41 on the chip 3 located in the first region 21 is connected to the fourth region 11 on the side away from the chip 3; the first conductive block 41 on the chip 3 located in the third region 23 is connected to the fifth region 12 on the side away from the chip 3; that is, the chip 3 can be directly arranged on the lower substrate 2 by solder or the like, and then connected to the upper substrate 1 by the conductive block; it can be understood that the chip 3 can be arranged at any position in the first region 21 and / or the third region 23, or it can be arranged in a personalized manner according to the size / requirements of the chip 3, that is, the chip 3 can be freely arranged in a specific region, and the substrate can be reused without damaging the substrate and trench 5, etc., which can realize mass production and improve production efficiency.

[0048] Furthermore, a second conductive block 42 is also provided on the lower substrate 2 in the first region and the second region 22; the side of the second conductive block 42 located in the first region 21 away from the lower substrate 2 is connected to the fifth region 12; the side of the second conductive block 42 located in the second region 22 away from the lower substrate 2 is connected to the fourth region 11. It can be understood that this embodiment includes two types of conductive blocks, a first conductive block 41 and a second conductive block 42, both of which are used to form a current path after the upper substrate 1 and the lower substrate 2 are connected. It can be understood that the first conductive block 41 is located on the chip 3, while the second conductive block 42 is directly located on the lower substrate 2 to achieve conduction. It can be understood that the specific positions of the first conductive block 41 / second conductive block 42 in each region can also be adjusted according to the output power and / or the size of the conductive block.

[0049] In this embodiment, the substrate structure is further connected (arranged) with a plurality of electrical connection elements 7 and electrodes 8; the electrical connection elements 7 and the electrodes 8 are arranged opposite each other on both sides of the lower substrate 2, and are electrically connected to the chip 3 / upper substrate 1 / lower substrate 2. Specifically, the electrical connection elements 7 include pins and / or terminals, etc.; three electrodes 8 are arranged, respectively located in the first region 21, the second region 22, and the third region 23. It can be understood that each electrode 8 can be electrically connected to a region, thereby allowing the chip 3 and / or conductive blocks, etc., to be arranged in each region according to the needs of each electrode 8, maintaining the absolute position of the electrical connection elements 7 and electrodes 8, thus differentiating it from the existing method of adjusting the arrangement based on the chip 3, and improving the efficiency of producing semiconductor modules with multiple power levels.

[0050] It is understood that the aforementioned electrode 8 can be the source, drain, and gate, or other components as required by the scenario. The electrical connection element 7 includes, but is not limited to, AC terminal, DC positive terminal, DC negative terminal, ground pin, and chip 3 connection pin.

[0051] Based on the above, in a preferred embodiment, the trenches 5 forming the second region 22 are symmetrically arranged along the centerline of the lower substrate 2 perpendicular to the first direction. For illustration, the first direction is the horizontal direction, i.e. Figure 2 In the X-direction, the second region 22 is located between the first region 21 and the second region 22, with the electrode 8 located at one end. The second region 22 forms a relatively regular shape and is located below the lower substrate 2 in the figure, not extending to the end away from the electrode 8. Specifically, as an example, such as Figure 2 As shown, the trench 5 on the lower substrate 2 forms an approximately Y-shape, as... Figure 3As shown, the trench 5 on the upper substrate 1 forms an inclined broken line shape, and the trench 5 on the lower substrate 2 bends to the right in the part below the second region 22 to take into account the second conductive block 42 located in the first region 21. The specific bending size can be adjusted according to the size and position of the second conductive block 42.

[0052] The design of the trench 5 mentioned above takes into account the parasitic inductance inside the power module, providing a high power level compatibility, low commutation loop parasitic inductance, low cost, and reusable substrate design structure.

[0053] In a preferred embodiment, multiple chips 3 are disposed within the first region 21 and / or the third region 23; each of the chips 3 is arranged along a second direction, wherein the second direction is perpendicular to the first direction, i.e., multiple chips 3 are arranged vertically in each region. This improves the rationality of the chip arrangement, enhances the uniformity of spatial distribution, and optimizes the chip arrangement through regular layout. Furthermore, the chips 3 located in the first region 21 and the chips 3 located in the third region 23 can be arranged symmetrically along the centerline of the lower substrate 2 perpendicular to the first direction. This results in a symmetrical distribution of the chips 3 on the substrate, facilitating uniform stress distribution during subsequent assembly or epoxy resin encapsulation, reducing the risk of damage during manufacturing, and improving yield.

[0054] Specifically, it is understood that the aforementioned chip 3 includes, but is not limited to, IGBT chip 3, MOSFET chip 3, and / or FRD (Fast Recovery Diode) chip 3. As an example, as shown in the figure, IGBT chip 3 (bottom) and FRD chip 3 (top) are applied in the first region 21 / third region 23 for applications requiring fast switching and high-efficiency energy conversion. Different specifications of IGBT and FRD chips 3 can be flexibly selected.

[0055] In this embodiment, the electrical connection element 7 is fixed on the lower substrate 2 by a metal sheet 92. As an example, a copper foil is provided, with one end of the copper foil connected to the gate pin (a certain electrical connection element 7) and the chip 3 connection part at the other end connected to the power semiconductor chip 3, thereby connecting the power semiconductor chip 3 to the gate pin. The chip 3 is connected to the corresponding electrical connection element 7 by a connecting line 91 (such as an aluminum bonding wire). The specific connection can be achieved by means including but not limited to connectors, soldering, etc.

[0056] In this embodiment, by dividing the lower substrate 2 into three regions respectively connected to the electrodes 8, and by allowing the first region 21 and the third region 23 to accommodate different chip 3 arrangements based on the output power requirements of the application scenario without altering the structure of the lower substrate 2 itself, multiple power level semiconductor modules can be produced, reducing product manufacturing costs. The lower substrate 2 and upper substrate 1 are connected via conductive blocks (first conductive block 41 / second conductive block 42) and the chips 3, resulting in a simple structure and low complexity in the fabrication process. Furthermore, preferably, each chip 3 is arranged along a predetermined direction in each region, optimizing the chip 3 position through a regular distribution. This also ensures a relatively symmetrical distribution of the chips 3 on the substrate, facilitating uniform stress during the molding process and improving the final performance of the power module.

[0057] Figure 4 The connection between the upper substrate 1 and the lower substrate 2 is specifically shown in Figure (a), which shows the lower substrate 2, and Figure (b) shows the upper substrate 1. It should be noted that annotations 3-1, 3-2, 3-3, and 3-4 all refer to chip 3, which can be of the same or different types and are only used as examples. Annotations 41-1, 41-2, 41-3, and 41-4 all refer to the first conductive block 41; annotations 42-1 and 42-2 all refer to the second conductive block 42, and are marked on both the upper substrate 1 and the lower substrate 2 to show the corresponding relationship. Annotations 8-1, 8-2, and 8-3 all refer to the electrodes 8 described below. The above annotations are only used to clearly distinguish and show the connection relationship between the upper substrate 1 and the lower substrate 2. Due to the large number of annotations, the connecting line 91 and the metal cladding 6 are not marked; the corresponding markings can be found in the reference diagram. Figures 1-3 The annotations mentioned above, which are only used to illustrate the correspondence, are not included in the figure labels. They are only used as examples, and the specific positions and sizes of each chip 3 can be adjusted.

[0058] This embodiment also provides a semiconductor power module, which uses the semiconductor power module substrate structure described in any of the above embodiments. For illustrative purposes, strictly speaking, the substrate may only include an upper substrate 1 and a lower substrate 2. However, in this embodiment, the structure in which the chip 3 and the conductive block enable conduction between the upper substrate 1 and the lower substrate 2 is also incorporated into the substrate structure. This is to achieve the connection between the upper substrate 1 and the lower substrate 2. The upper substrate 1, lower substrate 2, and conductive block, etc., are all used to form the semiconductor power module. Other components in the substrate structure / semiconductor power module besides those described above (such as a temperature sampling module) can also be integrated here.

[0059] Alternatively, the back sides of the upper substrate 1 and lower substrate 2 of the semiconductor power module can be used as / set as heat dissipation surfaces. The heat dissipation surfaces are connected to the cooling components of the module through thermal interface materials, brazing, or sintering to achieve better heat conduction, realize double-sided heat dissipation, reduce the impact of heat on the chip 3 during use, and improve the performance of the semiconductor power module.

[0060] It should be noted that the embodiments of this utility model have better implementability and are not intended to limit this utility model in any way. Any person skilled in the art may use the above-disclosed technical content to change or modify it into equivalent effective embodiments. However, any modifications or equivalent changes and modifications made to the above embodiments based on the technical essence of this utility model without departing from the content of the technical solution of this utility model shall still fall within the scope of the technical solution of this utility model.

Claims

1. A semiconductor power module substrate structure, characterized in that: Including the upper substrate and the lower substrate; The lower substrate is divided into a first region, a second region, and a third region sequentially along a first direction by trenches; The upper substrate is divided into a fourth region and a fifth region sequentially along the first direction by trenches; At least one chip is provided in the first region and the third region; Each of the aforementioned chips is provided with a first conductive block; The first conductive block on the chip located in the first region is connected to the fourth region on the side away from the chip. The first conductive block on the chip located in the third region is connected to the fifth region on the side away from the chip. A second conductive block is further provided on the lower substrate in the first and second regions; The second conductive block located in the first region is connected to the fifth region on the side away from the lower substrate. The second conductive block located in the second region is connected to the fourth region on the side away from the lower substrate.

2. The semiconductor power module substrate structure according to claim 1, characterized in that: The trenches forming the second region are arranged symmetrically along the centerline of the lower substrate perpendicular to the first direction.

3. The semiconductor power module substrate structure according to claim 1, characterized in that: When multiple chips are provided in the first region and / or the third region; Each of the chips is arranged along a second direction, wherein the second direction is perpendicular to the first direction.

4. The semiconductor power module substrate structure according to claim 1, characterized in that: The chip located in the first region and the chip located in the third region are arranged symmetrically along the centerline on the lower substrate perpendicular to the first direction.

5. The semiconductor power module substrate structure according to claim 1, characterized in that: A metal cladding layer is provided on the lower substrate and / or the upper substrate, and the trench passes through the metal cladding layer to form the first region, the second region, and the third region.

6. The semiconductor power module substrate structure according to claim 1, characterized in that: The chip includes IGBT chips, MOSFET chips, and / or FRD chips.

7. The semiconductor power module substrate structure according to claim 1, characterized in that: It is also connected to several electrical connection elements and electrodes; The electrical connection element and the electrode are arranged opposite each other on both sides of the lower substrate.

8. The semiconductor power module substrate structure according to claim 7, characterized in that: The electrodes are arranged in three parts, located in the first region, the second region, and the third region, respectively.

9. The semiconductor power module substrate structure according to claim 7, characterized in that: The electrical connection element is fixed to the lower substrate by a metal sheet; The chip is connected to the corresponding electrical connection element via a connection line.

10. A semiconductor power module, characterized in that: The semiconductor power module substrate structure according to any one of claims 1-9.

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